Power semiconductor device, electronic apparatus, and vehicle

Abstract

The utility model relates to a power semiconductor device, an electronic device and a vehicle, two sides of a substrate are respectively provided with a first heat dissipation member and a second heat dissipation member, and a first power chip unit and a second power chip unit are embedded into the substrate. The distance between the first power chip unit and the first heat dissipation piece is smaller than the distance between the second power chip unit and the first heat dissipation piece, the first heat dissipation piece and the second heat dissipation piece are used for conducting heat dissipation on the first power chip unit and the second power chip unit respectively, and the double-face heat dissipation effect can be achieved. Therefore, the problem that the working performance is reduced due to the fact that the heat dissipation capability of the power semiconductor device is limited can be solved, and the working performance of the power semiconductor device can be enhanced while the integration level of the power semiconductor device is improved.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more particularly to a power semiconductor device, electronic equipment, and vehicle. Background Technology

[0002] Power semiconductor devices are devices that combine multiple power chips according to specific functions and patterns, and then encapsulate or mold them into a single unit. As power semiconductor devices develop towards higher power and higher integration, heat dissipation becomes increasingly prominent, thus requiring higher and higher heat dissipation capabilities. The chip is the core functional component that generates heat, and the accumulation of heat can severely affect the operating performance of power semiconductor devices. Therefore, developing power semiconductor devices with efficient heat dissipation is of paramount importance.

[0003] Currently, to improve the integration of power semiconductor devices, power chips are typically embedded entirely within circuit boards for wiring. However, because the power chips are encased in the circuit board substrate, their heat dissipation capacity is limited, leading to a decrease in the performance of the power semiconductor devices.

[0004] In summary, current power semiconductor devices suffer from a significant performance degradation due to limited heat dissipation capabilities. Therefore, it is necessary to provide a power semiconductor device, electronic device, and vehicle to mitigate this deficiency. Utility Model Content

[0005] This application provides a power semiconductor device that can improve the heat dissipation performance of the power semiconductor device, thereby improving the operating performance of the power semiconductor device.

[0006] To achieve the above objectives, according to a first aspect of this application, a power semiconductor device is provided, comprising:

[0007] The substrate includes a first surface and a second surface disposed opposite to each other;

[0008] The first power chip unit is embedded in the substrate;

[0009] The second power chip unit is embedded in the substrate;

[0010] A first heat sink is disposed on the first surface; and

[0011] A second heat sink is disposed on the second surface;

[0012] The distance between the first power chip unit and the first heat sink is less than the distance between the second power chip unit and the first heat sink.

[0013] Optionally, the first power chip unit includes at least one first power chip, the front side of the first power chip is conductive, the second power chip unit includes at least one second power chip, the front side of the second power chip is conductive, and at least one of the back sides of the first power chip and the back sides of the second power chip is insulated.

[0014] The first power chip unit is disposed on the side of the second power chip unit that is close to the first heat sink. The back side of the first power chip unit is closer to the first heat sink than the front side of the first power chip. The back side of the second power chip is closer to the second heat sink than the front side of the second power chip.

[0015] Optionally, the front side of the first power chip is positioned directly opposite the front side of the second power chip.

[0016] Optionally, the power semiconductor device includes at least one surface conductive layer disposed on the first surface and / or the second surface, the substrate includes multiple conductive layers disposed between the first power chip unit and the second power chip unit, the first power chip unit includes at least one first power chip, the second power chip unit includes at least one second power chip, the first power chip and the second power chip are respectively connected to the corresponding conductive layer, and the conductive layer is connected to the surface conductive layer.

[0017] Optionally, the first power chip unit includes a plurality of first power chips, which are arranged symmetrically about a symmetrical center line or a symmetrical center; the second power chip unit includes a plurality of second power chips, which are arranged symmetrically about a symmetrical center line or a symmetrical center.

[0018] Optionally, a plurality of the first power chips are arranged in rows at intervals along a first direction, at least two rows of the first power chips are arranged at intervals along a second direction, and at least two rows of the first power chips are arranged symmetrically about a symmetrical center line, wherein the first direction and the second direction are different;

[0019] Multiple second power chips are arranged in rows at intervals along the first direction, with at least two rows of second power chips arranged at intervals along the second direction, and at least two rows of second power chips arranged symmetrically about a symmetrical center line.

[0020] Optionally, the front side of the first power chip has a source, a drain, a gate, and a Kelvin source. The drain of the first power chip is disposed at one end of the first power chip, and the source, gate, and Kelvin source of the first power chip are disposed at the other end of the first power chip. The drains of one row of the first power chips are disposed far apart from the drains of another row of the first power chips.

[0021] The front side of the second power chip has a source, a drain, a gate, and a Kelvin source. The drain of the second power chip is disposed at one end of the second power chip, and the source, gate, and Kelvin source of the second power chip are disposed at the other end of the second power chip. The drains of one row of the second power chips are disposed close to each other with the drains of another row of the second power chips.

[0022] Optionally, the surface conductive layer includes a first conductive portion, the conductive layer includes a first conductive layer, the first conductive layer is disposed between the first power chip and the second power chip, the gate of the first power chip is connected to the first conductive layer, and the first conductive layer is connected to the first conductive portion.

[0023] Optionally, the power semiconductor device includes a heat dissipation area and a first conductive area, the first conductive area being disposed on one side of the heat dissipation area, the first heat dissipation component being disposed in the heat dissipation area, and the first conductive portion being disposed in the first conductive area;

[0024] The first conductive layer includes a first conductive segment and at least two second conductive segments. The first conductive segment is disposed in the first conductive region, and the second conductive segments are disposed in the heat dissipation region. Each second conductive segment is connected to the gate of a plurality of first power chips in a corresponding row, and the second conductive segment is connected to the first conductive segment.

[0025] Optionally, the second conductive segment extends along the first direction, and at least two second conductive segments are arranged at intervals along the second direction, wherein the first direction is different from the second direction.

[0026] Optionally, the surface conductive layer includes a second conductive portion, the conductive layer includes a second conductive layer, the second conductive layer is disposed between the first conductive layer and the second power chip, the Kelvin source of the first power chip is connected to the second conductive layer, and the second conductive layer is connected to the second conductive portion.

[0027] Optionally, the second conductive portion is disposed in the first conductive region, and the second conductive portion and the first conductive portion are arranged adjacent to each other at intervals along the second direction;

[0028] The second conductive layer includes a third conductive segment and at least two fourth conductive segments. The third conductive segment is disposed in the first conductive region, and the fourth conductive segment is disposed in the heat dissipation region. Each fourth conductive segment is connected to the Kelvin source of a plurality of first power chips in a corresponding row, and the fourth conductive segment is connected to the third conductive segment.

[0029] Optionally, the fourth conductive segment extends along a first direction, and at least two of the fourth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

[0030] Optionally, the surface conductive layer includes a third conductive portion, the conductive layer includes a third conductive layer, the third conductive layer is disposed between the second conductive layer and the second power chip, the drain of the first power chip is connected to the third conductive layer, and the third conductive layer is connected to the third conductive portion.

[0031] Optionally, the power semiconductor device further includes a second conductive region, which is spaced apart from the first conductive region, the heat dissipation region is disposed between the first conductive region and the second conductive region, and the third conductive portion is disposed in the second conductive region;

[0032] The third conductive layer includes a fifth conductive segment and at least two sixth conductive segments. The fifth conductive segment is disposed in the second conductive region, and the sixth conductive segment is disposed in the heat dissipation region. Each sixth conductive segment is connected to the drain of a plurality of first power chips in a corresponding row, and the sixth conductive segment is connected to the fifth conductive segment.

[0033] Optionally, the sixth conductive segment extends along a first direction, and at least two sixth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

[0034] Optionally, the surface conductive layer includes a fourth conductive portion, the conductive layer includes a fourth conductive layer and a fifth conductive layer, the fourth conductive layer is disposed between the third conductive layer and the second power chip, the fifth conductive layer is disposed between the fourth conductive layer and the second power chip, the source of the first power chip is connected to the fourth conductive layer, the drain of the second power chip is connected to the fifth conductive layer, the fifth conductive layer is connected to the fourth conductive layer, and the fourth conductive layer is connected to the fourth conductive portion.

[0035] Optionally, the fourth conductive portion is disposed in the first conductive region, the fourth conductive portion is located on the side of the second conductive portion away from the first conductive portion, the fourth conductive layer includes at least one seventh conductive segment and at least one eighth conductive segment, the seventh conductive segment is disposed in the first conductive region, the eighth conductive segment is disposed in the heat dissipation region, the eighth conductive segment is located between the two rows of the first power chips and is connected to the source of the two rows of the first power chips, the eighth conductive segment is connected to the seventh conductive segment, and the seventh conductive segment is connected to the fourth conductive portion;

[0036] The fifth conductive layer includes a ninth conductive segment and a tenth conductive segment. The ninth conductive segment is disposed in the first conductive area, and the tenth conductive segment is disposed in the heat dissipation area. The tenth conductive segment is located between the two rows of the second power chips and is connected to the drain of the two rows of the second power chips. The tenth conductive segment is connected to the ninth conductive segment, and the ninth conductive segment is connected to the seventh conductive segment.

[0037] Optionally, the eighth conductive segment extends along the first direction, and the tenth conductive segment extends along the first direction.

[0038] Optionally, the fourth conductive layer is symmetrically arranged about a center line, and the fifth conductive layer is symmetrically arranged about a center line.

[0039] Optionally, the surface conductive layer includes a fifth conductive portion, the conductive layer includes a sixth conductive layer, the sixth conductive layer is disposed between the fifth conductive layer and the second power chip, the source of the second power chip is connected to the sixth conductive layer, and the sixth conductive layer is connected to the fifth conductive portion.

[0040] Optionally, the fifth conductive portion is disposed in the second conductive region, and the fifth conductive portion and the third conductive portion are disposed adjacent to each other and spaced apart along the second direction. The sixth conductive layer includes an eleventh conductive segment and at least two twelfth conductive segments. The eleventh conductive segment is disposed in the second conductive region, and the twelfth conductive segment is disposed in the heat dissipation region. Each twelfth conductive segment is connected to the source of a plurality of second power chips in a corresponding row. The twelfth conductive segment is connected to the eleventh conductive segment, and the eleventh conductive segment is connected to the fifth conductive portion.

[0041] Optionally, the twelfth conductive segment extends along a first direction, and at least two twelfth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

[0042] Optionally, the surface conductive layer includes a sixth conductive portion, the conductive layer includes a seventh conductive layer, the seventh conductive layer is disposed between the sixth conductive layer and the second power chip, the gate of the second power chip is connected to the seventh conductive layer, and the seventh conductive layer is connected to the sixth conductive portion.

[0043] Optionally, the sixth conductive portion is disposed in the first conductive region, the seventh conductive layer includes a thirteenth conductive segment and a fourteenth conductive segment, the thirteenth conductive segment is disposed in the first conductive region, the fourteenth conductive segment is disposed in the heat dissipation region, the fourteenth conductive segment is connected to the gate of at least two rows of the second power chip, the fourteenth conductive segment is connected to the thirteenth conductive segment, and the thirteenth conductive segment is connected to the sixth conductive portion.

[0044] Optionally, the fourteenth conductive segment extends along a first direction.

[0045] Optionally, the surface conductive layer includes a seventh conductive portion, the conductive layer includes an eighth conductive layer, the eighth conductive layer is disposed between the seventh conductive layer and the second power chip, the Kelvin source of the second power chip is connected to the eighth conductive layer, and the eighth conductive layer is connected to the seventh conductive portion.

[0046] Optionally, the seventh conductive portion is disposed in the first conductive region, and the eighth conductive layer includes a fifteenth conductive segment and a sixteenth conductive segment. The fifteenth conductive segment is disposed in the first conductive region, and the sixteenth conductive segment is disposed in the heat dissipation region. The sixteenth conductive segment is connected to the Kelvin source of at least two rows of the second power chip, the sixteenth conductive segment is connected to the fifteenth conductive segment, and the fifteenth conductive segment is connected to the seventh conductive portion.

[0047] Optionally, the sixteenth conductive segment extends along a first direction.

[0048] Optionally, the surface conductive layer includes a first surface conductive layer, which is disposed on the first surface or partially embedded in the substrate on the side near the first heat sink. The first surface conductive layer includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, a fifth conductive portion, a sixth conductive portion, and a seventh conductive portion.

[0049] Optionally, the surface conductive layer includes:

[0050] A first surface conductive layer is disposed on the first surface or partially embedded in the substrate on the side near the first heat sink. The first surface conductive layer includes the third conductive portion, the fourth conductive portion, and the fifth conductive portion.

[0051] The second surface conductive layer is disposed on the second surface or partially embedded in the substrate on the side near the second heat sink. The second surface conductive layer includes the first conductive portion, the second conductive portion, the sixth conductive portion, and the seventh conductive portion.

[0052] Optionally, the first heat sink includes a first heat sink substrate and a plurality of first heat sinks, wherein the plurality of first heat sinks are arranged in an array on the surface of the first heat sink substrate away from the substrate.

[0053] The second heat sink includes a second heat sink substrate and a plurality of second heat sinks, wherein the plurality of second heat sinks are arranged in an array on the surface of the second heat sink substrate away from the substrate.

[0054] Optionally, the first heat dissipation part is a columnar structure or a bent sheet structure, and the second heat dissipation part is a columnar structure or a bent sheet structure.

[0055] Optionally, the first power chip unit includes at least one first power chip, and the second power chip unit includes at least one second power chip, wherein both the first power chip and the second power chip are gallium nitride high electron mobility transistors.

[0056] According to a second aspect of this application, an electronic device is provided, including the power semiconductor device as described above.

[0057] According to a third aspect of this application, a vehicle is also provided, including the electronic equipment described above.

[0058] In the power semiconductor device of this application embodiment, by providing a first heat sink and a second heat sink on both sides of the substrate, embedding the first power chip unit and the second power chip unit into the substrate, and making the distance between the first power chip unit and the first heat sink smaller than the distance between the second power chip unit and the first heat sink, the first heat sink is used to dissipate heat from the first power chip unit, and the second heat sink is used to dissipate heat from the second power chip unit, thereby achieving the effect of double-sided heat dissipation of the power semiconductor device, thereby improving the heat dissipation capacity of the power semiconductor device. Therefore, it can solve the problem of reduced working performance due to the limited heat dissipation capacity of the power semiconductor device, thereby improving the integration of the power semiconductor device while enhancing its working performance.

[0059] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0061] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0062] Figure 1 An overall structural diagram of a power semiconductor device provided for an embodiment of this application;

[0063] Figure 2 Exploded view of a power semiconductor device provided for an embodiment of this application;

[0064] Figure 3 A layout diagram of a first power chip in a power semiconductor device provided for embodiments of this application;

[0065] Figure 4 A layout diagram of the second power chip in a power semiconductor device provided for embodiments of this application;

[0066] Figure 5 A front view of a first conductive layer in a power semiconductor device provided for an embodiment of this application;

[0067] Figure 6 A bottom view of the first conductive layer in a power semiconductor device provided for an embodiment of this application;

[0068] Figure 7 A front view of a second conductive layer in a power semiconductor device provided for an embodiment of this application;

[0069] Figure 8 A bottom view of the second conductive layer in a power semiconductor device provided for an embodiment of this application;

[0070] Figure 9 A front view of a third conductive layer in a power semiconductor device provided for an embodiment of this application;

[0071] Figure 10 A bottom view of the third conductive layer in a power semiconductor device provided for an embodiment of this application;

[0072] Figure 11 A front view of the fourth and fifth conductive layers in a power semiconductor device provided for embodiments of this application;

[0073] Figure 12A bottom view of the fourth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0074] Figure 13 A top view of the fifth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0075] Figure 14 A front view of the sixth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0076] Figure 15 A top view of the sixth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0077] Figure 16 A front view of the seventh conductive layer in a power semiconductor device provided for an embodiment of this application;

[0078] Figure 17 A top view of the seventh conductive layer in a power semiconductor device provided for an embodiment of this application;

[0079] Figure 18 A front view of the eighth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0080] Figure 19 A top view of the eighth conductive layer in a power semiconductor device provided for an embodiment of this application;

[0081] Figure 20 An overall structural diagram of another power semiconductor device provided for an embodiment of this application;

[0082] Figure 21 A front view of another power semiconductor device provided for an embodiment of this application;

[0083] Figure 22 An overall structural diagram of another power semiconductor device provided for an embodiment of this application;

[0084] Figure 23 A block diagram of an electronic device provided for an embodiment of this application;

[0085] Figure 24 A block diagram of a vehicle provided for an embodiment of this application.

[0086] Explanation of reference numerals in the attached figures:

[0087] 1. Substrate; 1a. First surface; 1b. Second surface; 11. Insulating layer; 111. First insulating layer; 112. Second insulating layer; 113. Third insulating layer; 114. Fourth insulating layer; 115. Fifth insulating layer; 116. Sixth insulating layer; 117. Seventh insulating layer; 118. Eighth insulating layer; 119. Ninth insulating layer; 110. Tenth insulating layer; 12. Conductive layer; 121. First conductive layer; 1211. First conductive segment; 1212. Second conductive segment; 122. Second conductive layer; 1221. Third conductive segment; 1222. Fourth conductive segment ; 123, Third conductive layer; 1231, Fifth conductive segment; 1232, Sixth conductive segment; 124, Fourth conductive layer; 1241, Seventh conductive segment; 1242, Eighth conductive segment; 125, Fifth conductive layer; 1251, Ninth conductive segment; 1252, Tenth conductive segment; 126, Sixth conductive layer; 1261, Eleventh conductive segment; 1262, Twelfth conductive segment; 127, Seventh conductive layer; 1271, Thirteenth conductive segment; 1272, Fourteenth conductive segment; 128, Eighth conductive layer; 1281, Fifteenth conductive segment; 1282, Sixteenth conductive segment;

[0088] 2. First power chip unit; 20. First power chip; 20a. Front side of the first power chip; 20b. Back side of the first power chip; 201. Source; 202. Drain; 203. Gate; 204. Kelvin source;

[0089] 3. Second power chip unit; 30. Second power chip; 30a. Front side of the second power chip; 30b. Back side of the second power chip; 301. Source; 302. Drain; 303. Gate; 304. Kelvin source;

[0090] 4. First heat sink; 41. First heat sink substrate; 42. First heat sink section;

[0091] 5. Second heat sink; 51. Second heat sink substrate; 52. Second heat sink section;

[0092] 6. Surface conductive layer; 61. First surface conductive layer; 62. Second surface conductive layer; 601. First conductive part; 602. Second conductive part; 603. Third conductive part; 604. Fourth conductive part; 605. Fifth conductive part; 606. Sixth conductive part;

[0093] 100. Power semiconductor devices; 101. Electronic equipment; 1000. Vehicles;

[0094] A0, heat dissipation zone; A1, first conductive zone; A2, second conductive zone. Detailed Implementation

[0095] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0096] This application provides a power semiconductor device; please refer to [link / reference]. Figures 1 to 22 The power semiconductor device 100 includes a substrate 1, a first power chip unit 2, a second power chip unit 3, a first heat sink 4, and a second heat sink 5. The substrate 1 includes a first surface 1a and a second surface 1b disposed opposite to each other. The first power chip unit 2 is embedded in the substrate 1 and includes at least one first power chip 20. The second power chip unit 3 includes at least one second power chip 30. The first heat sink 4 is disposed on the side of the first surface 1a away from the second surface 1b, and the second heat sink 5 is disposed on the side of the second surface 1b away from the first surface 1a. The distance between the first power chip unit 2 and the first heat sink 4 is smaller than the distance between the second power chip unit 3 and the first heat sink 4. In this way, the first power chip 20 can be cooled by the closer first heat sink 4, and the second power chip 30 can be cooled by the second heat sink 5, achieving a double-sided heat dissipation effect. This improves the heat dissipation capacity of the power semiconductor device 100 and solves the problem of reduced performance caused by limited heat dissipation capacity of the power semiconductor device. Thus, the integration of the power semiconductor device 100 can be improved while enhancing its performance.

[0097] In some embodiments, the front side 20a of the first power chip is conductive, the front side 30a of the second power chip is conductive, and at least one of the back side 20b of the first power chip and the back side 30b of the second power chip is insulated. A first heat sink 4 is disposed on the side of the first surface 1a facing away from the second surface 1b, and a second heat sink 5 is disposed on the side of the second surface 1b facing away from the first surface 1a. A first power chip unit 2 is disposed on the side of the second power chip unit 3 near the first heat sink 4. The back side 20b of the first power chip is closer to the first heat sink 4 than the front side 20a of the first power chip, and the back side 30b of the second power chip is closer to the second heat sink 5 than the front side 30a of the second power chip. When the back side 20b of the first power chip is an insulating surface, it serves as the heat dissipation surface of the first power chip 20; when the back side 30b of the second power chip is an insulating surface, it serves as the heat dissipation surface of the second power chip 30.

[0098] In some embodiments, the front side 20a of the first power chip is conductive, and the back side 20b of the first power chip is insulated; the front side 30a of the second power chip is conductive, and the back side 30b of the second power chip is insulated. The first heat sink 4 is used to dissipate heat from the first power chip 20, and the second heat sink 5 is used to dissipate heat from the second power chip 30, thereby achieving a double-sided heat dissipation effect. This improves the heat dissipation capacity of the power semiconductor device 100, thus solving the problem of reduced performance caused by limited heat dissipation capacity of the power semiconductor device. As a result, the integration density of the power semiconductor device 100 can be increased while enhancing its performance.

[0099] In some embodiments, the front side 20a of the first power chip is conductive, the back side 20b of the first power chip is insulated, and both the front side 30a and the back side 30b of the second power chip are conductive; or, both the front side 20a and the back side 20b of the first power chip are conductive, and the front side 30a and the back side 30b of the second power chip are insulated. Similarly, the first heat sink 4 can be used to dissipate heat from the first power chip 20, and the second heat sink 5 can be used to dissipate heat from the second power chip 30.

[0100] In the embodiments of this application, the first power chip 20 is an upper-bridge power chip, and the second power chip 30 is a lower-bridge power chip.

[0101] In some embodiments, please refer to Figure 2 The substrate 1 is a printed circuit board. Specifically, the substrate 1 includes a plurality of insulating layers 11 and a plurality of conductive layers 12 stacked together. The conductive layers 12 are disposed on one side of the insulating layers 11 or between adjacent insulating layers 11. The first surface 1a can be regarded as the upper surface of the substrate 1, and the second surface 1b can be regarded as the lower surface of the substrate 1.

[0102] In some embodiments, the insulating layer 11 may be made of organic or inorganic insulating materials. Specifically, the insulating layer 11 may be made of epoxy resin or glass fiber reinforced epoxy resin.

[0103] In some embodiments, the material of the conductive layer 12 is selected from any one of metallic materials, semiconductor materials, conductive polymer materials, and carbon materials.

[0104] In some embodiments, please refer to Figure 3 and Figure 5The first power chip 20 is a gallium nitride high electron mobility transistor, specifically a planar gallium nitride high electron mobility transistor. The front side 20a of the first power chip is conductive, and the back side 20b is insulating. This means that all electrodes of the first power chip 20 are located on the front side 20a, giving it conductive properties, while the back side 20b has no electrodes, thus giving it insulating properties. The back side 20b can also be considered as the heat dissipation surface of the first power chip 20.

[0105] In some embodiments, please refer to Figure 4 and Figure 7 The second power chip 30 is a gallium nitride high electron mobility transistor, specifically a planar gallium nitride high electron mobility transistor. The front side 30a of the second power chip is conductive, and the back side 30b is insulating. This means that all electrodes of the second power chip 30 are located on the front side 30a, giving it conductive properties, while the back side 30b has no electrodes, thus giving it insulating properties. The back side 30b can also be considered as the heat dissipation surface of the second power chip 30.

[0106] In some embodiments, both the first heat sink 4 and the second heat sink 5 are components capable of heat dissipation, such as heat sinks, heat dissipation plates, or heat dissipation films. The first heat sink 4 being disposed on the side of the first surface 1a away from the second surface 1b can mean that the first heat sink 4 is disposed on the first surface 1a of the substrate 1 and in direct contact with the first surface 1a, or it can mean that the first heat sink 4 is disposed above the first surface 1a of the substrate 1 and separated from the first surface 1a by other insulating or protective layers. The second heat sink 5 being disposed on the side of the second surface 1b away from the first surface 1a means that the second heat sink 5 is disposed above the second surface 1b and in direct contact with the second surface 1b, or it can mean that the second heat sink 5 is disposed above the second surface 1b of the substrate 1 and separated from the second surface 1b by other insulating or protective layers.

[0107] In the embodiments of this application, by providing a first heat sink 4 and a second heat sink 5 on both sides of the substrate 1, a first power chip unit 2 and a second power chip unit 3 are embedded in the substrate 1, and the first power chip unit 2 is disposed on the side of the second power chip unit 3 closer to the first heat sink 4. The back surface 20b of the first power chip unit is closer to the first heat sink 4 than the front surface 20a of the first power chip, thereby utilizing the first heat sink 4 to dissipate heat from the first power chip 20. The back surface 30b of the second power chip is closer to the second heat sink 5 than the front surface 30a of the second power chip, thereby utilizing the second heat sink 5 to dissipate heat from the second power chip 30. This achieves the effect of double-sided heat dissipation of the power semiconductor device 100, which can improve the efficiency of absorbing heat from the first power chip 20 and the second power chip 30, thereby improving the heat dissipation capacity of the power semiconductor device 100. Therefore, it can solve the problem of reduced performance caused by the limited heat dissipation capacity of the power semiconductor device, thereby improving the integration of the power semiconductor device while enhancing its performance.

[0108] In some embodiments, refer to Figure 5 and Figure 7 The front side 20a of the first power chip and the front side 30a of the second power chip are positioned facing each other, while the back side 20b of the first power chip and the back side 30b of the second power chip are positioned opposite each other. The first power chip 20 and the second power chip 30 are stacked in the thickness direction of the substrate 1. This arrangement not only ensures that the conductive surfaces of the first power chip 20 and the second power chip 30 face the interior of the substrate 1, but also that the heat dissipation surfaces of the first power chip 20 and the second power chip 30 face the exterior of the substrate 1, allowing the first heat dissipation component 4 and the second heat dissipation component 5 on both sides of the substrate 1 to quickly absorb the heat generated by the first power chip 20 and the second power chip 30, achieving a double-sided heat dissipation effect, thereby improving the heat dissipation capacity of the power semiconductor device. Furthermore, by stacking the first power chip 20 and the second power chip 30 in the thickness direction of the substrate 1, the volume of the power semiconductor device can be reduced, thereby improving the integration density of the power semiconductor device.

[0109] In some embodiments, please refer to Figure 1The power semiconductor device 100 includes at least one surface conductive layer 6, which is disposed on a first surface 1a and / or a second surface 1b. The substrate 1 includes multiple insulating layers 11 and multiple conductive layers 12 stacked together. The conductive layer 12 is disposed between a first power chip 20 and a second power chip 30. The first power chip 20 and the second power chip 30 are respectively connected to their corresponding conductive layers 12, and the conductive layers 12 are connected to the surface conductive layer 6. By embedding the first power chip 20 and the second power chip 30 in the substrate 1, and disposing of or partially embedding the surface conductive layer 6 on the surface of the substrate 1, the conductive layers 12 in the substrate 1 and the surface conductive layer 6 on the surface of the substrate 1 can replace traditional binding wires and terminals for transmitting electrical signals. This not only reduces the stray inductance of the power semiconductor device 100 but also increases its power density. In addition, traditional methods can only connect the capacitor interface to the terminal via bolts. In this embodiment, by embedding a surface conductive layer 6 on the surface of the substrate 1, external devices can be connected to the surface conductive layer 6 by welding, pressing, or bolting. This provides more options for the interface of power semiconductor devices, thereby improving the compatibility of power semiconductor devices.

[0110] In some embodiments, please refer to Figure 2 The substrate 1 also includes conductive pillars. A plurality of vias are formed in the insulating layer 11 of the substrate 1. The conductive pillars fill each via. The first power chip 20 and the second power chip 30 can be connected to the corresponding conductive layer 12 through at least one conductive pillar. The conductive layer 12 is connected to the surface conductive layer 6 through at least one other conductive pillar.

[0111] In some embodiments, both the conductive layer 12 and the conductive pillars are made of metal, specifically copper.

[0112] In some embodiments, please refer to Figure 3 and Figure 4 , Figure 3 A layout diagram of the first power chip in a power semiconductor device provided for an embodiment of this application. Figure 4The diagram illustrates the arrangement of second power chips in a power semiconductor device provided in this application. The first power chip unit 2 includes multiple first power chips 20, and the second power chip unit 3 includes multiple second power chips 30. The multiple first power chips 20 and the multiple second power chips 30 are arranged symmetrically about a center line or a center of symmetry. By symmetrically arranging the multiple first power chips 20, interference between the traces of the electrodes of the multiple first power chips 20 can be avoided. Furthermore, the signal transmission path lengths of the multiple first power chips 20 are made the same, reducing the signal transmission delay between different first power chips 20. This ensures that the signal turn-on time of each first power chip 20 is consistent, thereby reducing the probability of the first power chips 20 being falsely turned on.

[0113] Similarly, symmetrically arranging multiple second power chips 30 can not only avoid interference between the traces of the electrodes of the multiple second power chips 30, but also make the signal transmission path length of the multiple second power chips 30 the same, reduce the signal transmission delay between different second power chips 30, so that the time when each second power chip 30 receives the signal to turn on is consistent, thereby reducing the probability of the second power chip 30 being turned on by mistake.

[0114] In some embodiments, a plurality of first power chips 20 are arranged in rows at intervals along a first direction X, and at least two rows of first power chips 20 are arranged at intervals along a second direction Y, with at least two rows of first power chips 20 symmetrically arranged about a center line of symmetry, wherein the first direction X and the second direction Y are opposite. This not only avoids interference between the traces of the electrodes of the plurality of first power chips 20, but also ensures that the signal transmission path lengths of the plurality of first power chips 20 are the same, reducing the signal transmission delay between different first power chips 20, and ensuring that the signal turn-on time of each first power chip 20 is consistent, thereby reducing the probability of the first power chip 20 being falsely turned on.

[0115] In some embodiments, please refer to Figure 3Multiple first power chips 20 are arranged in rows at intervals along a first direction X, and two rows of first power chips 20 are arranged at intervals along a second direction Y. One row of first power chips 20 and the other row of first power chips 20 are symmetrically arranged about a first symmetry center line L1. The first direction X and the second direction Y are opposite, and the first symmetry center line L1 is parallel to the first direction X. In this way, interference between the traces of the electrodes of the multiple first power chips 20 can be avoided, and the signal transmission path length of the multiple first power chips 20 can be made the same, reducing the signal transmission delay between different first power chips 20. This ensures that the signal turn-on time of each first power chip 20 is consistent, thereby reducing the probability of the first power chip 20 being turned on erroneously.

[0116] In some embodiments, the first power chip unit 2 may have 2n rows of first power chips 20, where n is an integer greater than or equal to 1. The 2n rows of first power chips 20 are arranged at intervals along the second direction Y. The n rows of first power chips 20 located on one side of the first symmetry center line L1 are symmetrically arranged with the n rows of first power chips 20 located on the other side of the first symmetry center line L1. This can also avoid interference between the traces of the electrodes of the multiple first power chips 20 and reduce the probability of the first power chips 20 being turned on by mistake.

[0117] In some embodiments, the first direction X and the second direction Y are set perpendicular to each other.

[0118] In some embodiments, a plurality of second power chips 30 are arranged in rows at intervals along a first direction X, and at least two rows of second power chips 30 are arranged at intervals along a second direction Y, with the at least two rows of second power chips 30 arranged symmetrically with a center line. This not only avoids interference between the traces of the electrodes of the plurality of second power chips 30, but also ensures that the signal transmission path lengths of the plurality of second power chips 30 are the same, reducing the signal transmission delay between different second power chips 30. This ensures that the signal activation time of each second power chip 30 is consistent, thereby reducing the probability of the second power chips 30 being falsely activated.

[0119] In some embodiments, please refer to Figure 4Multiple second power chips 30 are arranged in rows at intervals along a first direction X, and two rows of second power chips 30 are arranged at intervals along a second direction Y. One row of second power chips 30 and the other row of second power chips 30 are symmetrically arranged about a second symmetry center line L2, which is parallel to the first direction X. This not only avoids interference between the traces of the electrodes of the multiple second power chips 30, but also ensures that the signal transmission path lengths of the multiple second power chips 30 are the same, reducing the signal transmission delay between different second power chips 30. This ensures that the signal activation time of each second power chip 30 is consistent, thereby reducing the probability of false activation of the second power chips 30.

[0120] In some embodiments, the second power chip unit 3 may have 2n rows of second power chips 30, where n is greater than or equal to 1. The 2n rows of second power chips 30 are arranged at intervals along the second direction Y. The n rows of second power chips 30 located on one side of the second symmetry center line L2 are symmetrically arranged with the n rows of second power chips 30 located on the other side of the second symmetry center line L2. This can also avoid interference between the traces of the electrodes of the multiple second power chips 30 and reduce the probability of the first power chip 20 being turned on by mistake.

[0121] In some embodiments, please refer to Figure 3 The front side 20a of the first power chip has a source 201, a drain 202, a gate 203 and a Kelvin source 204. The drain 202 of the first power chip 20 is disposed at one end of the first power chip 20, and the source 201, gate 203 and Kelvin source 204 of the first power chip 20 are disposed at the other end of the first power chip 20. The drains 202 of one row of first power chips are disposed far apart from the drains 202 of another row of first power chips.

[0122] Please see Figure 4 The front side 30a of the second power chip has a source 301, a drain 302, a gate 303, and a Kelvin source 304. The drain 302 of the second power chip is disposed at one end of the second power chip 30, and the source 301, gate 303, and Kelvin source 304 of the second power chip are disposed at the other end of the second power chip 30. The drains 302 of one row of second power chips are disposed close to each other with the drains 302 of another row of second power chips.

[0123] Please see Figure 3 and Figure 4The first power chip 20 and the second power chip 30 are placed in opposite ways, which makes it easier to arrange the AC output phases symmetrically in space. This not only prevents interference between the traces of the electrodes in the first power chip 20 and the second power chip 30, but also makes it easier to control the length of the signal transmission path of multiple first power chips 20 and second power chips 30 to be the same, so that the signal turn-on time of multiple first power chips 20 or second power chips 30 is consistent, thereby reducing the probability of the first power chip 20 and the second power chip 30 being turned on by mistake.

[0124] In some embodiments, the arrangement of the first power chip 20 and the second power chip 30 is not limited to the symmetrical arrangement of adjacent rows of chips in the above embodiments. Multiple first power chips 20 or multiple second power chips 30 can also be arranged in a centrally symmetrical manner, which can achieve the same technical effect as described above.

[0125] In some embodiments, please refer to Figure 5 and Figure 6 The surface conductive layer 6 includes a first conductive portion 601, and the conductive layer 12 includes a first conductive layer 121. The first conductive layer 121 is disposed between the first power chip 20 and the second power chip 30. The gate 203 of the first power chip is connected to the first conductive layer 121, and the first conductive layer 121 is connected to the first conductive portion 601. The gate 203 of the first power chip is electrically connected to the first conductive portion 601 of the surface conductive layer 6 through the first conductive layer 121 inside the substrate 1. Since the stray inductance of the copper wire is low, the interference on the control waveform is minimized, thereby improving the stability and safety of the power semiconductor device.

[0126] In some embodiments, please refer to Figure 2 , Figure 5 and Figure 6The insulating layer 11 includes a first insulating layer 111, which can be considered as the uppermost insulating layer of the substrate 1. The outer surface of the first insulating layer 111 is the first surface 1a of the substrate 1. The first heat sink 4 is disposed on the surface of the first insulating layer 111. The surface conductive layer 6 includes a first surface conductive layer 61, which is partially embedded in the first insulating layer 111 and partially exposed outside the first insulating layer 111. The first surface conductive layer 61 includes a first conductive portion 601. The insulating layer 11 also includes a second insulating layer 112 and a third insulating layer 113. The second insulating layer 112 is disposed on the side of the first insulating layer 111 away from the first heat sink 4, and the third insulating layer 113 is disposed on the side of the second insulating layer 112 away from the first insulating layer 111. The first power chip 20 is embedded in the second insulating layer 112 or disposed on the surface of the second insulating layer 112. The first conductive layer 121 is embedded in the second insulating layer 112 or disposed on the surface of the second insulating layer 112.

[0127] In some embodiments, please refer to Figure 5 and Figure 6 The power semiconductor device 100 includes a heat dissipation area A0 and a first conductive area A1. The first conductive area A1 is disposed on one side of the heat dissipation area A0. The first heat sink 4 is disposed in the heat dissipation area A0. The first conductive part 601 is disposed in the first conductive area A1, with space reserved for placing the first heat sink 4 at the top.

[0128] In some embodiments, the first conductive layer 121 includes a first conductive segment 1211 and at least two second conductive segments 1212. The first conductive segment 1211 is disposed in a first conductive region A1, and the second conductive segments 1212 are disposed in a heat dissipation region A0. Each second conductive segment 1212 is located on one side of one row of first power chips 20 near another row of first power chips 20. Each second conductive segment 1212 is connected to the gate of a plurality of first power chips in the corresponding row, and the second conductive segment 1212 is connected to the first conductive segment 1211. The second conductive segments 1212 extend along a first direction X, and at least two second conductive segments 1212 are arranged at intervals along a second direction Y.

[0129] In some embodiments, please refer to Figure 5 and Figure 6The first conductive layer 121 includes a first conductive segment 1211 and two second conductive segments 1212. The first conductive segment 1211 is disposed in the first conductive region A1, and the second conductive segments 1212 are disposed in the heat dissipation region A0. Each second conductive segment 1212 is located on the side of one row of first power chips 20 close to another row of first power chips 20. A plurality of vias are formed on the second insulating layer 112, and conductive pillars are filled in the vias. Each second conductive segment 1212 is connected to the gate 203 of the plurality of first power chips in the corresponding row through the conductive pillar in the via. The second conductive segment 1212 extends along the first direction X to connect with the first conductive segment 1211. The first conductive segment 1211 is connected to the first conductive part 601 through the conductive pillar in at least one other via, thereby electrically connecting the gate 203 of the first power chip to the first conductive part 601. By connecting the two second conductive segments 1212 to the gates 203 of the multiple first power chips in the corresponding row, the control paths of the two rows of first power chips 20 can be made relatively short and of similar length. This not only reduces stray inductance in the circuit, but also reduces signal transmission delay and ensures that the signal turn-on time of each first power chip 20 is consistent, thereby improving the uniformity of current distribution of each first power chip 20, and thus improving the stability and safety of power semiconductor devices.

[0130] In some embodiments, please refer to Figure 7 and Figure 8 , Figure 7 A front view of the second conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 8 This is a bottom view of the second conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a second conductive portion 602, and the conductive layer 12 includes a second conductive layer 122. The second conductive layer 122 is disposed between the first conductive layer 121 and the second power chip 30. The Kelvin source 204 of the first power chip is connected to the second conductive layer 122, and the second conductive layer 122 is connected to the second conductive portion 602. The second conductive layer 122 inside the substrate 1 electrically connects the Kelvin source 204 of the first power chip to the second conductive portion 602 of the surface conductive layer 6. Because the stray inductance of the copper wire is low, the interference on the control waveform is minimized, thereby improving the stability and safety of the power semiconductor device.

[0131] In some embodiments, please refer to Figure 2 , Figure 7 and Figure 8A second conductive portion 602 is disposed in the first conductive region A1. The second conductive portion 602 and the first conductive portion 601 are arranged adjacent to each other along the second direction Y, with space reserved at the top for placing the first heat sink 4. The second conductive layer 122 includes a third conductive segment 1221 and at least two fourth conductive segments 1222. Each fourth conductive segment 1222 is connected to the Kelvin source 204 of a plurality of first power chips in a corresponding row. The fourth conductive segment 1222 is connected to the third conductive segment 1221, and the third conductive segment 1221 is connected to the second conductive portion 602. The fourth conductive segments 1222 extend along the first direction X, and at least two fourth conductive segments 1222 are arranged at intervals along the second direction Y.

[0132] In some embodiments, please refer to Figure 2 , Figure 7 and Figure 8 The second conductive layer 122 includes a third conductive segment 1221 and two fourth conductive segments 1222. The third conductive segment 1221 is disposed in the first conductive region A1, and the fourth conductive segments 1222 are disposed in the heat dissipation region A0. The insulating layer 11 also includes a fourth insulating layer 114. The second conductive layer 122 is embedded in the fourth insulating layer 114 or disposed on the surface of the fourth insulating layer 114. A via is formed on the third insulating layer 113, and the via is filled with a conductive post. Each fourth conductive segment 1222 is connected to the Kelvin source 204 of a plurality of first power chips in a corresponding row through the conductive post in the via. The fourth conductive segment 1222 extends along the first direction X to connect with the third conductive segment 1221. The third conductive segment 1221 is connected to the second conductive part 602 through the conductive post in at least one other via, thereby electrically connecting the Kelvin source 204 of the first power chip to the second conductive part 602. By connecting the two fourth conductive segments 1222 to the Kelvin source 204 of the corresponding row of multiple first power chips, the signal transmission paths of the two rows of first power chips 20 can be made relatively short and similar in length. This not only reduces stray inductance in the circuit, but also reduces signal transmission delay, thereby improving the uniformity of current distribution of each first power chip 20, and thus improving the stability and safety of power semiconductor devices.

[0133] In some embodiments, please refer to Figure 9 and Figure 10 , Figure 9 A front view of the third conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 10This is a bottom view of the third conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a third conductive portion 603, which is the DC positive input terminal. The conductive layer 12 includes a third conductive layer 123, which is disposed between the second conductive layer 122 and the second power chip 30. The drain 202 of the first power chip is connected to the third conductive layer 123, and the third conductive layer 123 is connected to the third conductive portion 603. The drain 202 of the first power chip is electrically connected to the third conductive portion 603 of the surface conductive layer 6 through the third conductive layer 123 inside the substrate 1. Since the stray inductance of the copper wire is low, the interference on the control waveform is minimized, thereby improving the stability and safety of the power semiconductor device.

[0134] In some embodiments, please refer to Figure 9 and Figure 10 The power semiconductor device 100 also includes a second conductive region A2, which is spaced apart from the first conductive region A1. A heat dissipation region A0 is disposed between the first conductive region A1 and the second conductive region A2. A third conductive portion 603 is disposed in the second conductive region A2, with a space reserved at the top for placing the first heat sink 4. The third conductive layer 123 includes a fifth conductive segment 1231 and at least two sixth conductive segments 1232. The fifth conductive segment 1231 is disposed in the second conductive region A2, and the sixth conductive segments 1232 are disposed in the heat dissipation region A0. Each sixth conductive segment 1232 is connected to the drain 202 of a plurality of first power chips in a corresponding row, and the sixth conductive segment 1232 is connected to the fifth conductive segment 1231.

[0135] In some embodiments, please refer to Figure 9 and Figure 10 The sixth conductive segment 1232 extends along the first direction X, and at least two sixth conductive segments 1232 are arranged at intervals along the second direction Y.

[0136] In some embodiments, please refer to Figure 9 and Figure 10The third conductive layer 123 includes a fifth conductive segment 1231 and two sixth conductive segments 1232. The fifth conductive segment 1231 is disposed in the second conductive region A2, and the sixth conductive segments 1232 are disposed in the heat dissipation region A0. The insulating layer 11 also includes a fifth insulating layer 115. The third conductive layer 123 is embedded in the fifth insulating layer 115 or disposed on the surface of the fifth insulating layer 115. A via is formed on the fourth insulating layer 114, and the via is filled with a conductive post. Each sixth conductive segment 1232 is connected to the drain 202 of a plurality of first power chips in a corresponding row through the conductive post in the via. The sixth conductive segment 1232 extends along the first direction X to connect with the fifth conductive segment 1231. The fifth conductive segment 1231 is connected to the third conductive part 603 through the conductive post in at least one other via, thereby electrically connecting the drain 202 of the first power chip to the third conductive part 603. By connecting the two sixth conductive segments 1232 to the drains 202 of multiple first power chips in a corresponding row, the signal transmission paths of the two rows of first power chips 20 can be made relatively short and of similar length. This not only reduces stray inductance in the circuit, but also reduces signal transmission delay, thereby improving the uniformity of current distribution of each first power chip 20, and thus improving the stability and safety of power semiconductor devices.

[0137] In some embodiments, please refer to Figure 11 , Figure 12 and Figure 13 , Figure 11 A front view of the fourth and fifth conductive layers in a power semiconductor device provided for embodiments of this application. Figure 12 A bottom view of the fourth conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 13This is a top view of the fifth conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a fourth conductive portion 604, and the conductive layer 12 includes a fourth conductive layer 124 and a fifth conductive layer 125. The fourth conductive layer 124 is disposed between the third conductive layer 123 and the second power chip 30, and the fifth conductive layer 125 is disposed between the fourth conductive layer 124 and the second power chip 30. The source 201 of the first power chip is connected to the fourth conductive layer 124, and the drain 302 of the second power chip is connected to the fifth conductive layer 125. The fifth conductive layer 125 is connected to the fourth conductive layer 124, and the fourth conductive layer 124 is connected to the fourth conductive portion 604. The source 201 of the first power chip is electrically connected to the fourth conductive portion 604 of the surface conductive layer 6 and the drain 302 of the second power chip through the fourth conductive layer 124 and the fifth conductive layer 125 inside the substrate 1. Because the stray inductance of the copper wire is low, the interference to the control waveform is minimized, thereby improving the stability and safety of the power semiconductor device. Based on this, since the first power chip 20 and the second power chip 30 are symmetrically arranged in space, it is beneficial to the current sharing of each conductive layer, and the first power chip 20 and the second power chip 30 require the same via depth, which is beneficial to simplifying the process.

[0138] In some embodiments, please refer to Figure 2 , Figure 11 , Figure 12 and Figure 13 The fourth conductive part 604 is disposed in the first conductive area A1. The fourth conductive part 604 is located on the side of the second conductive part 602 away from the first conductive part 601. The fourth conductive layer 124 includes at least one seventh conductive segment 1241 and at least one eighth conductive segment 1242. The seventh conductive segment 1241 is disposed in the first conductive area A1, and the eighth conductive segment 1242 is disposed in the heat dissipation area A0. The eighth conductive segment 1242 is located between the two rows of first power chips 20.

[0139] In some embodiments, please refer to Figure 2 , Figure 11 , Figure 12 and Figure 13 The fourth conductive layer 124 includes a seventh conductive segment 1241 and an eighth conductive segment 1242. The seventh conductive segment 1241 is disposed in the first conductive region A1, and the eighth conductive segment 1242 is disposed in the heat dissipation region A0. The eighth conductive segment 1242 is located between two rows of first power chips 20. The fifth conductive layer 125 includes a ninth conductive segment 1251 and a tenth conductive segment 1252. The ninth conductive segment 1251 is disposed in the first conductive region A1, and the tenth conductive segment 1252 is disposed in the heat dissipation region A0. The tenth conductive segment 1252 is located between two rows of second power chips 30.

[0140] The insulating layer 11 also includes a sixth insulating layer 116 and a seventh insulating layer 117. The fourth conductive layer 124 is embedded in the sixth insulating layer 116 or disposed on the surface of the sixth insulating layer 116. The fifth conductive layer 125 is embedded in the seventh insulating layer 117 or disposed on the surface of the seventh insulating layer 117. Through holes are formed on the sixth insulating layer 116 and the seventh insulating layer 117, and conductive pillars are filled in the through holes. The eighth conductive segment 1242 is connected to the source 201 of the two rows of first power chips through conductive posts in multiple vias. The eighth conductive segment 1242 extends along the first direction X to connect with the seventh conductive segment 1241. The tenth conductive segment 1252 is connected to the drain 302 of the two rows of second power chips through conductive posts in multiple vias. The tenth conductive segment 1252 extends along the first direction X to connect with the ninth conductive segment 1251. The seventh conductive segment 1241 is connected to the ninth conductive segment 1251 and the fourth conductive part 604 through conductive posts in at least another via, thereby electrically connecting the source 201 of the first power chip to the fourth conductive part 604 of the surface conductive layer 6 and the drain 302 of the second power chip.

[0141] In some embodiments, please refer to Figure 12 The fourth conductive layer 124 is symmetrically arranged about a third symmetry center line L3. The width of the eighth conductive segment 1242 along the second direction Y is greater than the distance between the two rows of first power chips 20. This can increase the area of ​​the fourth conductive layer 124, thereby improving the overcurrent capability of the fourth conductive layer 124, and thus improving the stability and output current capability of the power semiconductor device.

[0142] In some embodiments, please refer to Figure 13 The fifth conductive layer 125 is symmetrically arranged about a fourth symmetry center line L4. The width of the tenth conductive segment 1252 along the second direction Y is greater than the distance between the two rows of second power chips 30. This can increase the area of ​​the fifth conductive layer 125, thereby improving the current carrying capacity of the fifth conductive layer 125, and thus improving the stability and output current capability of the power semiconductor device.

[0143] In some embodiments, please refer to Figure 14 and Figure 15 , Figure 14 A front view of the sixth conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 15This is a top view of the sixth conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a fifth conductive portion 605, which is the DC negative output terminal. The conductive layer 12 includes a sixth conductive layer 126, which is disposed between the fifth conductive layer 125 and the second power chip 30. The source 301 of the second power chip is connected to the sixth conductive layer 126, and the sixth conductive layer 126 is connected to the fifth conductive portion 605. In this way, a current loop can be formed, which is input from the third conductive portion 603, flows sequentially through the first power chip 20 and the second power chip 30, and is finally output from the fifth conductive portion 605. The current flow direction in the current loop is opposite in the conductive layer corresponding to the first power chip 20 and the conductive layer corresponding to the second power chip 30. The induced electromotive forces formed in the different conductive layers cancel each other out, thereby reducing the stray inductance in the power semiconductor device.

[0144] In some embodiments, please refer to Figure 14 and Figure 15 A fifth conductive portion 605 is disposed in the second conductive region A2. The fifth conductive portion 605 and the third conductive portion 603 are arranged adjacent to each other along the second direction Y, with space reserved at the top for placing the first heat sink 4. The sixth conductive layer 126 includes an eleventh conductive segment 1261 and at least two twelfth conductive segments 1262. The eleventh conductive segment 1261 is disposed in the second conductive region A2, and the twelfth conductive segment 1262 is disposed in the heat sink region A0. Each twelfth conductive segment 1262 is connected to the source 301 of a plurality of second power chips in a corresponding row. The twelfth conductive segment 1262 is connected to the eleventh conductive segment 1261, and the eleventh conductive segment 1261 is connected to the fifth conductive portion 605. The twelfth conductive segment 1262 extends along the first direction X, and at least two twelfth conductive segments 1262 are arranged at intervals along the second direction Y.

[0145] In some embodiments, please refer to Figure 14 and Figure 15 The sixth conductive layer 126 includes an eleventh conductive segment 1261 and two twelfth conductive segments 1262. The eleventh conductive segment 1261 is disposed in the second conductive region A2, and the twelfth conductive segments 1262 are disposed in the heat dissipation region A0. The insulating layer 11 also includes an eighth insulating layer 118. The sixth conductive layer 126 is embedded in the eighth insulating layer 118 or disposed on the surface of the eighth insulating layer 118. Through holes are formed on the eighth insulating layer 118, and conductive pillars are filled in the through holes. Each twelfth conductive segment 1262 is connected to the source 301 of a plurality of second power chips in a corresponding row through the conductive pillars in the plurality of through holes. The twelfth conductive segment 1262 extends along the first direction X to connect with the eleventh conductive segment 1261. The eleventh conductive segment 1261 is connected to the fifth conductive part 605 through the conductive pillars in at least one through hole, thereby realizing the electrical connection between the source 301 of the second power chip and the fifth conductive part 605.

[0146] In some embodiments, please refer to Figure 16 and Figure 17 , Figure 16 A front view of the seventh conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 17 This is a top view of the seventh conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a sixth conductive portion 606, and the conductive layer 12 includes a seventh conductive layer 127. The seventh conductive layer 127 is disposed between the sixth conductive layer 126 and the second power chip 30. The gate 303 of the second power chip is connected to the seventh conductive layer 127, and the seventh conductive layer 127 is connected to the sixth conductive portion 606. The gate 303 of the second power chip is electrically connected to the sixth conductive portion 606 of the surface conductive layer 6 through the seventh conductive layer 127 inside the substrate 1. Because the stray inductance of the copper wire is low, the interference on the control waveform is minimized, thereby improving the stability and safety of the power semiconductor device.

[0147] In some embodiments, please refer to Figure 16 and Figure 17 The sixth conductive portion 606 is disposed in the first conductive region A1, with space reserved at the top for placing the first heat sink 4. The seventh conductive layer 127 includes a thirteenth conductive segment 1271 and a fourteenth conductive segment 1272. The thirteenth conductive segment 1271 is disposed in the first conductive region A1, and the fourteenth conductive segment 1272 is disposed in the heat sink region A0. The insulating layer 11 also includes a ninth insulating layer 119. The seventh conductive layer 127 is embedded in the ninth insulating layer 119 or disposed on the surface of the ninth insulating layer 119. Through holes are formed in the ninth insulating layer 119, and conductive pillars are filled in the through holes. The fourteenth conductive segment 1272 is connected to the gate 303 of at least two rows of the second power chip through the conductive pillars in the multiple through holes. The fourteenth conductive segment 1272 extends along the first direction X to connect with the thirteenth conductive segment 1271. The thirteenth conductive segment 1271 is connected to the sixth conductive portion 606 through the conductive pillar in at least one through hole, thereby realizing the electrical connection between the gate 303 of the second power chip and the sixth conductive portion 606. By connecting the fourteenth conductive segment 1272 to the gate 303 of the two rows of second power chips, the transmission path of the control signal of the two rows of second power chips 30 can be made relatively short and close to the transmission path of the control signal of the first power chip 20. This can not only reduce stray inductance in the circuit, but also reduce signal transmission delay and ensure that the signal turn-on time of each second power chip 30 is consistent, thereby improving the uniformity of current distribution of each second power chip 30, reducing false turn-on records, and thus improving the stability and safety of power semiconductor devices.

[0148] In some embodiments, please refer to Figure 18 and Figure 19, Figure 18 A front view of the eighth conductive layer in a power semiconductor device provided for an embodiment of this application. Figure 19 This is a top view of the eighth conductive layer in a power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a seventh conductive portion 607, and the conductive layer 12 includes an eighth conductive layer 128. The eighth conductive layer 128 is disposed between the seventh conductive layer 127 and the second power chip 30. The Kelvin source 304 of the second power chip is connected to the eighth conductive layer 128, and the eighth conductive layer 128 is connected to the seventh conductive portion 607. By electrically connecting the Kelvin source 304 of the second power chip to the seventh conductive portion 607 of the surface conductive layer 6 through the eighth conductive layer 128 inside the substrate 1, the stray inductance of the copper wire is low, minimizing interference to the control waveform, thereby improving the stability and safety of the power semiconductor device.

[0149] In some embodiments, please refer to Figure 1 and Figure 5 The seventh conductive part 607 is disposed in the first conductive area A1, with a reserved space at the top for placing the first heat sink 4. The eighth conductive layer 128 includes a fifteenth conductive segment 1281 and a sixteenth conductive segment 1282, with the fifteenth conductive segment 1281 disposed in the first conductive area A1 and the sixteenth conductive segment 1282 disposed in the heat sink area A0. The insulating layer 11 also includes a tenth insulating layer 110. An eighth conductive layer 128 is embedded in the tenth insulating layer 110 or disposed on the surface of the tenth insulating layer 110. A via is formed on the ninth and tenth insulating layers 110, and a conductive post is filled in the via. A sixteenth conductive segment 1282 is connected to the Kelvin source 304 of the two rows of second power chips through the conductive post in the via. The sixteenth conductive segment 1282 extends along the first direction X to connect with the fifteenth conductive segment 1281. The fifteenth conductive segment 1281 is connected to the seventh conductive part 607 through the conductive post in at least one via, thereby realizing the electrical connection between the Kelvin source 304 of the second power chip and the seventh conductive part 607. By connecting the sixteenth conductive segment 1282 to the Kelvin source 304 of at least two rows of second power chips, the signal transmission paths of the two rows of second power chips 30 can be made relatively short and close. This can not only reduce stray inductance in the circuit, but also reduce signal transmission delay, thereby improving the uniformity of current distribution of each second power chip 30.

[0150] In some embodiments, please refer to Figure 1 and Figure 5The surface conductive layer 6 includes a first surface conductive layer 61, which is disposed on the first surface 1a or partially embedded in the substrate 1 on the side near the first heat sink 4. The first surface conductive layer 61 includes a first conductive part 601, a second conductive part 602, a third conductive part 603, a fourth conductive part 604, a fifth conductive part 605, a sixth conductive part 606, and a seventh conductive part 607.

[0151] In some embodiments, please refer to Figure 20 and Figure 21 The first surface 1a is provided with a surface conductive layer, while the second surface 1b is not provided with a surface conductive layer. The area of ​​the second heat sink 5 is larger than the area of ​​the first heat sink 4. The first heat sink 4 is only provided in the heat dissipation area A0. The second heat sink 5 covers the heat dissipation area A0, the first conductive area A1, and the second conductive area A2. This can further improve the heat dissipation capacity of the power semiconductor.

[0152] In some embodiments, please refer to Figure 20 and Figure 21 , Figure 1 An overall structural diagram of another power semiconductor device provided for an embodiment of this application. Figure 5 This is a front view of another power semiconductor device provided in an embodiment of this application. The surface conductive layer 6 includes a first surface conductive layer 61 and a second surface conductive layer 62. The first surface conductive layer 61 is disposed on the first surface 1a or partially embedded in the side of the substrate 1 near the first heat sink 4. The first surface conductive layer 61 includes a third conductive portion 603, a fourth conductive portion 604, and a fifth conductive portion 605. The second surface conductive layer 62 is disposed on the second surface 1b or partially embedded in the side of the substrate 1 near the second heat sink 5. The second surface conductive layer 62 includes a first conductive portion 601, a second conductive portion 602, a sixth conductive portion 606, and a seventh conductive portion 607. By disposing the second surface conductive layer 62 on the second surface 1b of the substrate, interference between high-current signals and low-current signals can be reduced, thereby further improving the stability and safety of the power semiconductor device.

[0153] In some implementations, please refer to Figure 22 and Figure 22 The first heat sink 4 includes a first heat sink substrate 41 and a plurality of first heat sink sections 42. The plurality of first heat sink sections 42 are arranged in an array on the surface of the first heat sink substrate 41 away from the substrate 1. The first heat sink section 42 has a columnar structure, that is, the first heat sink 4 is a heat sink pin type heat sink. The second heat sink 5 includes a second heat sink substrate 51 and a plurality of second heat sink sections 52. The plurality of second heat sink sections 52 are arranged in an array on the surface of the second heat sink substrate 51 away from the substrate 1. The second heat sink section 52 has a columnar structure, that is, the second heat sink 5 is a heat sink pin type heat sink.

[0154] In some embodiments, please refer to Figure 23 , Figure 23 The following is an overall structural diagram of another power semiconductor device provided for an embodiment of this application. The first heat sink 4 includes a first heat sink substrate 41 and a plurality of first heat sink portions 42. The plurality of first heat sink portions 42 are arranged in an array on the surface of the first heat sink substrate 41 away from the substrate 1. The first heat sink portion 42 is a bent sheet structure, that is, the first heat sink 4 is a heat sink fin type heat sink.

[0155] The second heat sink 5 includes a second heat sink substrate and a plurality of second heat sinks. The plurality of second heat sinks are arranged in an array on the surface of the second heat sink substrate away from the substrate. The second heat sinks are bent sheet-like structures, that is, the second heat sink 5 is a heat sink fin type heat sink.

[0156] In the power semiconductor device of this application embodiment, by providing a first heat sink and a second heat sink on both sides of the substrate, a first power chip unit and a second power chip unit are embedded in the substrate, and the first power chip unit is disposed on the side of the second power chip unit closer to the first heat sink. The back side of the first power chip unit is closer to the first heat sink than the front side of the first power chip, and the back side of the second power chip is closer to the second heat sink than the front side of the second power chip. By using the first heat sink to dissipate heat from the first power chip unit and the second heat sink to dissipate heat from the second power chip unit, the effect of double-sided heat dissipation of the power semiconductor device can be achieved, thereby improving the heat dissipation capacity of the power semiconductor device. Therefore, the problem of reduced performance caused by the limited heat dissipation capacity of the power semiconductor device can be solved, thereby improving the integration of the power semiconductor device while enhancing its performance.

[0157] According to a second aspect of this application, an electronic device 101 is provided, which includes the power semiconductor device 100 described above. The electronic device 101 possesses all the beneficial effects of the power semiconductor device 100 described above, which will not be elaborated further herein.

[0158] In some embodiments, please refer to Figure 24 , Figure 24 The block diagram of the electronic device provided in the embodiments of this application shows that the electronic device 101 includes at least one power semiconductor device 100 as described in the above embodiments. For example, it may include one power semiconductor device 100, or it may include two or more power semiconductor devices 100. In the embodiments, the electronic device 101 may include, but is not limited to, a rectifier, an inverter, etc.

[0159] In some embodiments, electronic device 101 can be a power electronic device, such as an inverter, rectifier, frequency converter, electric drive system, electric vehicle controller, etc. This electronic device 101 is used to process high-power electrical signals and achieve efficient power conversion. By integrating power semiconductor devices 100, electronic device 101 can achieve efficient and reliable power circuit control and thermal management to meet the requirements of various application areas, such as industrial control, energy conversion, transportation, etc.

[0160] The electronic device 101 according to the present invention employs the power semiconductor device 100 described in the above embodiment. By providing a first heat sink and a second heat sink on both sides of the substrate, the first power chip unit and the second power chip unit are embedded in the substrate, and the distance between the first power chip unit and the first heat sink is made smaller than the distance between the second power chip unit and the first heat sink. The first heat sink dissipates heat from the first power chip unit, and the second heat sink dissipates heat from the second power chip unit. This achieves the effect of double-sided heat dissipation of the power semiconductor device, thereby improving the heat dissipation capacity of the power semiconductor device. Therefore, it can solve the problem of reduced performance caused by the limited heat dissipation capacity of the power semiconductor device, thereby improving the integration of the power semiconductor device while enhancing its performance.

[0161] According to a third aspect of this application, a vehicle is provided, please refer to... ​ , ​ The block diagram of the vehicle provided in the embodiments of this application shows that the vehicle 1000 includes at least one electronic device 101 as described in the above embodiments. The vehicle 1000 has all the beneficial effects of the electronic device 101 described above, which will not be repeated here.

[0162] According to the vehicle 1000 of this utility model embodiment, by employing the electronic device 101 described in the above embodiment, a first power chip unit and a second power chip unit are embedded in the substrate by respectively providing a first heat sink and a second heat sink on both sides of the substrate, and the distance between the first power chip unit and the first heat sink is made smaller than the distance between the second power chip unit and the first heat sink. The first heat sink is used to dissipate heat from the first power chip unit, and the second heat sink is used to dissipate heat from the second power chip unit. This achieves the effect of double-sided heat dissipation of the power semiconductor device, thereby improving the heat dissipation capacity of the power semiconductor device. Therefore, it can solve the problem of reduced working performance due to the limited heat dissipation capacity of the power semiconductor device, thereby improving the working performance of the power semiconductor device while increasing the integration of the power semiconductor device.

[0163] In some embodiments, the vehicle 1000 may be a gasoline-powered vehicle, a plug-in hybrid electric vehicle, or a new energy vehicle, etc., and this application does not specifically limit it.

[0164] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0165] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0166] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0167] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A power semiconductor device, characterized in that, include: The substrate includes a first surface and a second surface disposed opposite to each other; The first power chip unit is embedded in the substrate; The second power chip unit is embedded in the substrate; A first heat sink is disposed on the first surface; as well as A second heat sink is disposed on the second surface; The distance between the first power chip unit and the first heat sink is less than the distance between the second power chip unit and the first heat sink.

2. The power semiconductor device as described in claim 1, characterized in that, The first power chip unit includes at least one first power chip, the front side of the first power chip is conductive, the second power chip unit includes at least one second power chip, the front side of the second power chip is conductive, and at least one of the back sides of the first power chip and the back sides of the second power chip is insulated. The first power chip unit is disposed on the side of the second power chip unit that is close to the first heat sink. The back side of the first power chip unit is closer to the first heat sink than the front side of the first power chip. The back side of the second power chip is closer to the second heat sink than the front side of the second power chip.

3. The power semiconductor device as described in claim 2, characterized in that, The front of the first power chip is positioned directly opposite the front of the second power chip.

4. The power semiconductor device as described in claim 1, characterized in that, The power semiconductor device includes at least one surface conductive layer disposed on the first surface and / or the second surface. The substrate includes multiple conductive layers disposed between the first power chip unit and the second power chip unit. The first power chip unit includes at least one first power chip, and the second power chip unit includes at least one second power chip. The first power chip and the second power chip are respectively connected to the corresponding conductive layer, and the conductive layer is connected to the surface conductive layer.

5. The power semiconductor device as described in claim 4, characterized in that, The first power chip unit includes a plurality of first power chips, which are arranged symmetrically about a symmetrical center line or a symmetrical center; the second power chip unit includes a plurality of second power chips, which are arranged symmetrically about a symmetrical center line or a symmetrical center.

6. The power semiconductor device as described in claim 4, characterized in that, Multiple first power chips are arranged in rows at intervals along a first direction, at least two rows of first power chips are arranged at intervals along a second direction, and at least two rows of first power chips are arranged symmetrically about a symmetrical center line, wherein the first direction and the second direction are different; Multiple second power chips are arranged in rows at intervals along the first direction, with at least two rows of second power chips arranged at intervals along the second direction, and at least two rows of second power chips arranged symmetrically about a symmetrical center line.

7. The power semiconductor device as described in claim 4, characterized in that, The front side of the first power chip has a source, a drain, a gate, and a Kelvin source. The drain of the first power chip is disposed at one end of the first power chip, and the source, gate, and Kelvin source of the first power chip are disposed at the other end of the first power chip. The drains of one row of the first power chips are disposed far apart from the drains of another row of the first power chips. The front side of the second power chip has a source, a drain, a gate, and a Kelvin source. The drain of the second power chip is disposed at one end of the second power chip, and the source, gate, and Kelvin source of the second power chip are disposed at the other end of the second power chip. The drains of one row of the second power chips are disposed close to each other with the drains of another row of the second power chips.

8. The power semiconductor device as described in claim 7, characterized in that, The surface conductive layer includes a first conductive portion, the conductive layer includes a first conductive layer, the first conductive layer is disposed between the first power chip and the second power chip, the gate of the first power chip is connected to the first conductive layer, and the first conductive layer is connected to the first conductive portion.

9. The power semiconductor device as described in claim 8, characterized in that, The power semiconductor device includes a heat dissipation area and a first conductive area, the first conductive area being disposed on one side of the heat dissipation area, the first heat dissipation component being disposed in the heat dissipation area, and the first conductive portion being disposed in the first conductive area; The first conductive layer includes a first conductive segment and at least two second conductive segments. The first conductive segment is disposed in the first conductive region, and the second conductive segments are disposed in the heat dissipation region. Each second conductive segment is connected to the gate of a plurality of first power chips in a corresponding row, and the second conductive segment is connected to the first conductive segment.

10. The power semiconductor device as claimed in claim 9, characterized in that, The second conductive segment extends along the first direction, and at least two second conductive segments are arranged at intervals along the second direction, wherein the first direction is different from the second direction.

11. The power semiconductor device as claimed in claim 9, characterized in that, The surface conductive layer includes a second conductive portion, and the conductive layer includes a second conductive layer. The second conductive layer is disposed between the first conductive layer and the second power chip. The Kelvin source of the first power chip is connected to the second conductive layer, and the second conductive layer is connected to the second conductive portion.

12. The power semiconductor device as claimed in claim 11, characterized in that, The second conductive part is disposed in the first conductive area, and the second conductive part and the first conductive part are arranged adjacent to each other at intervals; The second conductive layer includes a third conductive segment and at least two fourth conductive segments. The third conductive segment is disposed in the first conductive region, and the fourth conductive segment is disposed in the heat dissipation region. Each fourth conductive segment is connected to the Kelvin source of a plurality of first power chips in a corresponding row, and the fourth conductive segment is connected to the third conductive segment.

13. The power semiconductor device as claimed in claim 12, characterized in that, The fourth conductive segment extends along a first direction, and at least two of the fourth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

14. The power semiconductor device as claimed in claim 12, characterized in that, The surface conductive layer includes a third conductive portion, the conductive layer includes a third conductive layer, the third conductive layer is disposed between the second conductive layer and the second power chip, the drain of the first power chip is connected to the third conductive layer, and the third conductive layer is connected to the third conductive portion.

15. The power semiconductor device as claimed in claim 14, characterized in that, The power semiconductor device further includes a second conductive region, which is spaced apart from the first conductive region. The heat dissipation region is disposed between the first conductive region and the second conductive region, and the third conductive portion is disposed in the second conductive region. The third conductive layer includes a fifth conductive segment and at least two sixth conductive segments. The fifth conductive segment is disposed in the second conductive region, and the sixth conductive segment is disposed in the heat dissipation region. Each sixth conductive segment is connected to the drain of a plurality of first power chips in a corresponding row, and the sixth conductive segment is connected to the fifth conductive segment.

16. The power semiconductor device as claimed in claim 15, characterized in that, The sixth conductive segment extends along a first direction, and at least two sixth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

17. The power semiconductor device as claimed in claim 15, characterized in that, The surface conductive layer includes a fourth conductive portion. The conductive layer includes a fourth conductive layer and a fifth conductive layer. The fourth conductive layer is disposed between the third conductive layer and the second power chip. The fifth conductive layer is disposed between the fourth conductive layer and the second power chip. The source of the first power chip is connected to the fourth conductive layer. The drain of the second power chip is connected to the fifth conductive layer. The fifth conductive layer is connected to the fourth conductive layer. The fourth conductive layer is connected to the fourth conductive portion.

18. The power semiconductor device as claimed in claim 17, characterized in that, The fourth conductive portion is disposed in the first conductive region. The fourth conductive portion is located on the side of the second conductive portion away from the first conductive portion. The fourth conductive layer includes at least one seventh conductive segment and at least one eighth conductive segment. The seventh conductive segment is disposed in the first conductive region. The eighth conductive segment is disposed in the heat dissipation region. The eighth conductive segment is located between the two rows of the first power chips and is connected to the source of the two rows of the first power chips. The eighth conductive segment is connected to the seventh conductive segment. The seventh conductive segment is connected to the fourth conductive portion. The fifth conductive layer includes a ninth conductive segment and a tenth conductive segment. The ninth conductive segment is disposed in the first conductive area, and the tenth conductive segment is disposed in the heat dissipation area. The tenth conductive segment is located between the two rows of the second power chips and is connected to the drain of the two rows of the second power chips. The tenth conductive segment is connected to the ninth conductive segment, and the ninth conductive segment is connected to the seventh conductive segment.

19. The power semiconductor device as claimed in claim 18, characterized in that, The eighth conductive segment extends along the first direction, and the tenth conductive segment extends along the first direction.

20. The power semiconductor device as claimed in claim 17, characterized in that, The fourth conductive layer is symmetrically arranged about a center line, and the fifth conductive layer is symmetrically arranged about a center line.

21. The power semiconductor device as claimed in claim 17, characterized in that, The surface conductive layer includes a fifth conductive portion, and the conductive layer includes a sixth conductive layer. The sixth conductive layer is disposed between the fifth conductive layer and the second power chip. The source of the second power chip is connected to the sixth conductive layer, and the sixth conductive layer is connected to the fifth conductive portion.

22. The power semiconductor device as claimed in claim 21, characterized in that, The fifth conductive portion is disposed in the second conductive region. The fifth conductive portion and the third conductive portion are disposed adjacent to each other and spaced apart along the second direction. The sixth conductive layer includes an eleventh conductive segment and at least two twelfth conductive segments. The eleventh conductive segment is disposed in the second conductive region, and the twelfth conductive segment is disposed in the heat dissipation region. Each twelfth conductive segment is connected to the source of a plurality of second power chips in a corresponding row. The twelfth conductive segment is connected to the eleventh conductive segment, and the eleventh conductive segment is connected to the fifth conductive portion.

23. The power semiconductor device as claimed in claim 22, characterized in that, The twelfth conductive segment extends along a first direction, and at least two of the twelfth conductive segments are arranged at intervals along a second direction, wherein the first direction is different from the second direction.

24. The power semiconductor device as claimed in claim 21, characterized in that, The surface conductive layer includes a sixth conductive portion, and the conductive layer includes a seventh conductive layer. The seventh conductive layer is disposed between the sixth conductive layer and the second power chip. The gate of the second power chip is connected to the seventh conductive layer, and the seventh conductive layer is connected to the sixth conductive portion.

25. The power semiconductor device as claimed in claim 24, characterized in that, The sixth conductive portion is disposed in the first conductive region. The seventh conductive layer includes a thirteenth conductive segment and a fourteenth conductive segment. The thirteenth conductive segment is disposed in the first conductive region, and the fourteenth conductive segment is disposed in the heat dissipation region. The fourteenth conductive segment is connected to the gate of at least two rows of the second power chip. The fourteenth conductive segment is connected to the thirteenth conductive segment, and the thirteenth conductive segment is connected to the sixth conductive portion.

26. The power semiconductor device as claimed in claim 25, characterized in that, The fourteenth conductive segment extends along the first direction.

27. The power semiconductor device as claimed in claim 24, characterized in that, The surface conductive layer includes a seventh conductive portion, and the conductive layer includes an eighth conductive layer. The eighth conductive layer is disposed between the seventh conductive layer and the second power chip. The Kelvin source of the second power chip is connected to the eighth conductive layer, and the eighth conductive layer is connected to the seventh conductive portion.

28. The power semiconductor device as claimed in claim 27, characterized in that, The seventh conductive portion is disposed in the first conductive region. The eighth conductive layer includes a fifteenth conductive segment and a sixteenth conductive segment. The fifteenth conductive segment is disposed in the first conductive region, and the sixteenth conductive segment is disposed in the heat dissipation region. The sixteenth conductive segment is connected to the Kelvin source of at least two rows of the second power chip. The sixteenth conductive segment is connected to the fifteenth conductive segment, and the fifteenth conductive segment is connected to the seventh conductive portion.

29. The power semiconductor device as claimed in claim 28, characterized in that, The sixteenth conductive segment extends along the first direction.

30. The power semiconductor device as claimed in claim 27, characterized in that, The surface conductive layer includes a first surface conductive layer, which is disposed on the first surface or partially embedded in the substrate on the side near the first heat sink. The first surface conductive layer includes a first conductive portion, a second conductive portion, a third conductive portion, a fourth conductive portion, a fifth conductive portion, a sixth conductive portion, and a seventh conductive portion.

31. The power semiconductor device as claimed in claim 27, characterized in that, The surface conductive layer includes: A first surface conductive layer is disposed on the first surface or partially embedded in the substrate on the side near the first heat sink. The first surface conductive layer includes the third conductive portion, the fourth conductive portion, and the fifth conductive portion. The second surface conductive layer is disposed on the second surface or partially embedded in the substrate on the side near the second heat sink. The second surface conductive layer includes the first conductive portion, the second conductive portion, the sixth conductive portion, and the seventh conductive portion.

32. The power semiconductor device according to any one of claims 1 to 31, characterized in that, The first heat sink includes a first heat sink substrate and a plurality of first heat sinks, wherein the plurality of first heat sinks are arranged in an array on the surface of the first heat sink substrate away from the substrate. The second heat sink includes a second heat sink substrate and a plurality of second heat sinks, wherein the plurality of second heat sinks are arranged in an array on the surface of the second heat sink substrate away from the substrate.

33. The power semiconductor device as described in claim 32, characterized in that, The first heat dissipation part is a columnar structure or a bent sheet structure, and the second heat dissipation part is a columnar structure or a bent sheet structure.

34. The power semiconductor device according to any one of claims 1 to 31, characterized in that, The first power chip unit includes at least one first power chip, and the second power chip unit includes at least one second power chip. Both the first power chip and the second power chip are gallium nitride high electron mobility transistors.

35. An electronic device, characterized in that, Includes the power semiconductor device as described in any one of claims 1 to 34.

36. A vehicle, characterized in that, Including the electronic device as described in claim 35.

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