Chip packaging structure

Abstract

A chip packaging structure comprises a first chip structure, the chip packaging structure comprises a heat dissipation substrate, the heat dissipation substrate is located above the first chip structure, the chip packaging structure comprises a second chip structure, the second chip structure is located above the heat dissipation substrate, and the second chip structure is electrically connected to the first chip structure through a conductive plug structure. The first thermal conductivity of the substrate is higher than the third thermal conductivity of the second chip structure, and the heat dissipation substrate is in direct contact with the first chip structure and the second chip structure.

Description

TECHNICAL FIELD

[0001] The utility model relates to semiconductor technology, especially to chip packaging structure. BACKGROUND

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each generation having features and capabilities that were previously considered to be the province of generals only. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] In the history of integrated circuits, function density (i.e., the number of interconnected devices per chip area) has increased while geometry size (i.e., the smallest component or line that can be produced) has decreased. This scaling down of component size benefits production efficiency and lowers costs.

[0004] However, as component size continues to shrink, chips generate more heat. Therefore, it is a challenge to form a package with good heat dissipation performance. SUMMARY

[0005] The utility model discloses a chip packaging structure to solve at least one of the above problems.

[0006] In some embodiments, a chip packaging structure is provided, the chip packaging structure includes a first chip structure; a heat dissipation substrate located above the first chip structure, wherein the heat dissipation substrate includes a substrate and a conductive plug structure, a first thermal conductivity of the substrate is higher than a second thermal conductivity of the first chip structure, the substrate has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, and the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; and a second chip structure located above the heat dissipation substrate, wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the substrate is higher than a third thermal conductivity of the second chip structure, and the heat dissipation substrate contacts the first chip structure and the second chip structure.

[0007] According to one of the embodiments of the utility model, the heat dissipation substrate further includes: a first bonding layer located above the first surface of the substrate, the first bonding layer directly contacts the first chip structure, and the first bonding pad portion passes through the first bonding layer.

[0008] According to one of the embodiments of the utility model, the heat dissipation substrate further includes: a second bonding layer located above the second surface of the substrate, the second bonding layer directly contacts the second chip structure, and the second bonding pad portion passes through the second bonding layer.

[0009] According to one of the embodiments of the present application, the heat dissipation substrate further comprises: a first planarization layer located between the first bonding layer and the substrate, and a third surface of the first planarization layer is away from the substrate and is more planar than the first surface of the substrate.

[0010] According to one of the embodiments of the present application, the heat dissipation substrate further comprises: a second planarization layer located between the second bonding layer and the substrate, and a fourth surface of the second planarization layer is away from the substrate and is more planar than the second surface of the substrate.

[0011] In some embodiments, a chip package structure is provided, which includes a first chip structure; a first heat dissipation substrate located on and bonded with the first chip structure, wherein the first heat dissipation substrate includes a substrate and a conductive plug structure, the first thermal conductivity of the substrate is higher than the second thermal conductivity of the first chip structure, the substrate has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; and a conductive bump located below and bonded with the first chip structure.

[0012] According to one of the embodiments of the present application, it further includes: a second chip structure located above the first heat dissipation substrate, wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the substrate is higher than the third thermal conductivity of the second chip structure, and the first heat dissipation substrate directly contacts the second chip structure; and a second heat dissipation substrate located above the second chip structure, wherein the fourth thermal conductivity of the second heat dissipation substrate is higher than the third thermal conductivity of the second chip structure.

[0013] According to one of the embodiments of the present application, the first heat dissipation substrate is thicker than the second heat dissipation substrate.

[0014] According to one of the embodiments of the present application, the first chip structure has a first conductive bonding pad, the first conductive bonding pad is directly bonded with the first bonding pad portion of the first heat dissipation substrate, and the first bonding pad portion is wider than the first conductive bonding pad.

[0015] According to one of the embodiments of the present application, the second chip structure has a second conductive bonding pad, the second conductive bonding pad is directly bonded with the second bonding pad portion of the first heat dissipation substrate, and the second bonding pad portion is wider than the second conductive bonding pad. BRIEF DESCRIPTION OF DRAWINGS

[0016] The embodiments of the present application will be understood more clearly from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that the various features illustrated in the drawings are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily expanded or reduced for the sake of clarity. Embodiments of the application will support these concepts and realize other advantages as described in the following detailed description when taken in conjunction with the accompanying drawings.

[0017] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G are cross-sectional schematic diagrams showing various stages of a process for forming a chip package structure according to some embodiments.

[0018] Figure 2 are cross-sectional schematic diagrams showing a chip package structure according to some embodiments.

[0019] Figure 3 are cross-sectional schematic diagrams showing a chip package structure according to some embodiments.

[0020] Figure 4 are cross-sectional schematic diagrams showing a chip package structure according to some embodiments.

[0021] The reference signs are as follows:

[0022] 10, 10A: heat dissipation base

[0023] 20, 30, 40: chip structure

[0024] 100, 200, 300, 400: chip package structure

[0025] 110: base

[0026] 112, 114, 122, 152: surface

[0027] 120, 120A, 150, 150A: planarization layer

[0028] 130, 130A, 160, 160A, 240, 340, B1, B2: bonding layer

[0029] 132, 162: opening

[0030] 140, 140A, 250, 350: conductive plug structure

[0031] 140a, 140b: conductive structure

[0032] 142, 142A, 144, 144A, 252, 352: bonding pad portion

[0033] 146, 146A, 254, 354: via portion

[0034] 210, 310, 410: semiconductor substrate

[0035] 212, 312, 412: front surface

[0036] 214, 314, 414: back surface

[0037] 220, 320, 420: interconnect structure

[0038] 230: bonding pad

[0039] 330, 430: conductive bonding pad

[0040] 510: conductive bump

[0041] TH: through hole

[0042] T10, T10A, T20, T30, T40, T110, T110A, T120, T130, T150, T160: thickness

[0043] W142, W144, W146: width DETAILED DESCRIPTION

[0044] It is to be understood that the following description provides many different embodiments, or examples, to implement various aspects of the subject matter provided. Some of these embodiments can be made in the course of design, while others can be fabricated. For the purpose of clarity, specific examples of components and arrangements are described as being employed in the embodiments. Of course, these are only examples and are not intended to limit the subject matter to the specific examples described. For example, dimensions of the elements can not be limited to the ranges or values provided in one embodiment, but can depend on processing conditions and / or desired properties of the elements. In addition, the following description includes embodiments in which a first component is formed over or on a second component, and embodiments in which the first and second components are formed in direct contact with each other, as well as embodiments in which additional components can be formed between the first and second components, such that the first and second components can not be in direct contact with each other. Furthermore, different examples in the description can use repeated references to a reference sign and / or a word. These repeated references are for the purpose of simplification and clarity and are not intended to limit the relationship between the various embodiments and / or the appearance of the structures described.

[0045] In order to facilitate the description of the relationship between one element or component and another (plurality of) element(s) or component(s) in the drawings, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used. The spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] Some embodiments are described herein. Additional operations can be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some stages described can be removed, others can be added, or some stages can be modified. Additional components can be added to the chip package structure. For different embodiments, some components described below can be removed, others can be added, or some components can be modified. Although the operations discussed for some embodiments are performed in a particular order, these operations can be performed in other logical order.

[0047] Other components and processes can also be included. For example, test structures can be included to assist in verification testing of the three-dimensional package or three-dimensional integrated circuit device. The test structures can include test pads formed in the redistribution layer or on the substrate, for example, that allow for testing of the three-dimensional package or three-dimensional integrated circuit, use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate structures and on final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0048] Figures 1A to 1G Cross-sectional schematic illustrations of stages of a process for forming a chip package structure are provided in accordance with some embodiments. In accordance with some embodiments, as shown in Figure 1A A substrate 110 is provided in accordance with some embodiments. In accordance with some embodiments, the substrate 110 has two side surfaces 112 and 114. In accordance with some embodiments, the substrate 110 is made of a dielectric material having a high thermal conductivity.

[0049] In accordance with some embodiments, the substrate 110 has a thermal conductivity greater than about 50 W / (m-K). In accordance with some embodiments, the substrate 110 has a thermal conductivity in a range from about 50 W / (m-K) to about 2000 W / (m-K).

[0050] In accordance with some embodiments, the substrate 110 is made of diamond (e.g., single crystal diamond or nanocrystalline diamond), carbon (e.g., nanocrystalline diamond-like carbon), or a crystalline material (e.g., crystalline Bas or crystalline BeO). In accordance with some embodiments, the substrate 110 has a thickness T110 in a range from about 0.5 pm to about 50 pm.

[0051] In accordance with some embodiments, as shown in Figure 1A A planarization layer 120 is formed over the surface 112 in accordance with some embodiments. In accordance with some embodiments, the planarization layer 120 has a surface 122. In accordance with some embodiments, the surface 122 is more planar than the surface 112 of the substrate 110. That is, in accordance with some embodiments, the surface 122 has a roughness that is less than the roughness of the surface 112. In accordance with some embodiments, the planarization layer 120 is used to provide a planar surface (e.g., the surface 122) for subsequent processes.

[0052] According to some embodiments, the thermal conductivity of the substrate 110 is higher than the thermal conductivity of the planarization layer 120. According to some embodiments, the planarization layer 120 is thinner than the substrate 110. According to some embodiments, the planarization layer 120 has a thickness T120 in a range from about 5 nm to about 5000 nm.

[0053] According to some embodiments, the planarization layer 120 is made of a dielectric material, such as amorphous silicon, SiN, or SiC. According to some embodiments, the planarization layer 120 and the substrate 110 are made of different materials.

[0054] According to some embodiments, as shown in FIG. 1C, a portion of the planarization layer 120 is removed to form an opening 122 in the planarization layer 120. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process. Figure 1A According to some embodiments, as shown in FIG. 1D, a bonding layer 130 is formed over the planarization layer 120. According to some embodiments, the bonding layer 130 is used to bond with a chip structure in a subsequent process. According to some embodiments, the thermal conductivity of the substrate 110 is higher than the thermal conductivity of the bonding layer 130.

[0055] According to some embodiments, the bonding layer 130 is thinner than the substrate 110. According to some embodiments, the bonding layer 130 has a thickness T130 in a range from about 5 nm to about 5000 nm. According to some embodiments, the bonding layer 130 is made of a dielectric material, such as amorphous silicon, SiO, SiON, SiN, SiCN, or AlN. According to some embodiments, the bonding layer 130, the planarization layer 120, and the substrate 110 are made of different materials.

[0056] According to some embodiments, as shown in FIG. 1E, a portion of the bonding layer 130 is removed to form an opening 132 in the bonding layer 130. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process. Figure 1B According to some embodiments, as shown in FIG. 1F, a portion of the substrate 110 and the planarization layer 120 is removed to form a through-hole TH. According to some embodiments, the through-hole TH passes through the substrate 110 and the planarization layer 120.

[0057] Figure 1B According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0058] According to some embodiments, as shown in FIG. 1G, a conductive structure 140a is formed in the opening 132 of the bonding layer 130 and the through-hole TH. According to some embodiments, the conductive structure 140a is made of a conductive material, such as a metal (e.g., titanium, copper, nickel, aluminum, gold, silver, or tungsten) or an alloy of the foregoing. According to some embodiments, the conductive structure 140a is formed by using a plating process, such as an electroplating process.

[0059] According to some embodiments, as shown in FIG. 1H, a portion of the conductive structure 140a is removed to form a conductive structure 140b. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process. Figure 1B According to some embodiments, as shown in FIG. 1H, a portion of the conductive structure 140a is removed to form a conductive structure 140b. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.​

[0060] According to some embodiments, as shown in FIG. 1A, a substrate 110 is provided. According to some embodiments, the substrate 110 is a semiconductor substrate. According to some embodiments, the substrate 110 is a silicon substrate. According to some embodiments, the substrate 110 has a surface 114. Figure 1C According to some embodiments, as shown in FIG. 1B, the substrate 110 is flipped upside down. According to some embodiments, as shown in FIG. 1C, a planarization layer 150 is formed over the surface 114 of the substrate 110. According to some embodiments, the planarization layer 150 has a surface 152. Figure 1C According to some embodiments, as shown in FIG. 1C, the planarization layer 150 is formed over the surface 114 of the substrate 110. According to some embodiments, the planarization layer 150 has a surface 152.

[0061] According to some embodiments, the surface 152 is flatter than the surface 114 of the substrate 110. That is, according to some embodiments, the surface 152 has a roughness that is less than the roughness of the surface 114. According to some embodiments, the planarization layer 150 is used to provide a flat surface (e.g., the surface 152) for subsequent processes.

[0062] According to some embodiments, the substrate 110 has a higher thermal conductivity than the planarization layer 150. According to some embodiments, the planarization layer 150 is thinner than the substrate 110.

[0063] According to some embodiments, the planarization layer 150 has a thickness T150 in a range from about 5 nm to about 5000 nm. According to some embodiments, the planarization layer 150 is made of a dielectric material, such as amorphous silicon, SiN, or SiC.

[0064] According to some embodiments, as shown in FIG. 1D, a bonding layer 160 is formed over the planarization layer 150. According to some embodiments, the bonding layer 160 is used to bond with a chip structure in subsequent processes. According to some embodiments, the substrate 110 has a higher thermal conductivity than the bonding layer 160. Figure 1C According to some embodiments, the bonding layer 160 is thinner than the substrate 110. According to some embodiments, the bonding layer 160 has a thickness T160 in a range from about 5 nm to about 5000 nm. According to some embodiments, the bonding layer 160 is made of a dielectric material, such as amorphous silicon, SiO, SiON, SiN, SiCN, or AlN. According to some embodiments, the bonding layer 160, the planarization layer 150, and the substrate 110 are made of different materials.

[0065] According to some embodiments, as shown in FIG. 1E, a portion of the bonding layer 160 is removed to form an opening 162 in the bonding layer 160. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0066] Figure 1D According to some embodiments, as shown in FIG. 1F, a portion of the bonding layer 160 is removed to form an opening 162 in the bonding layer 160. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0067] According to some embodiments, as shown in FIG. 1G, a portion of the bonding layer 160 is removed to form an opening 162 in the bonding layer 160. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process. Figure 1D ​As shown, the planarization layer 150 is partially removed to form an opening 152 in the planarization layer 150. According to some embodiments, the removal process includes a lithography process and an etching process. According to some embodiments, the etching process includes an anisotropic etching process, such as a dry etching process.

[0068] According to some embodiments, as shown in FIG. 1C, a conductive structure 140b is formed in the opening 162 of the bonding layer 160 and the opening 152 of the planarization layer 150. According to some embodiments, the conductive structure 140b is made of a conductive material, such as a metal (e.g., titanium, copper, nickel, aluminum, gold, silver, or tungsten) or an alloy of the foregoing. According to some embodiments, the conductive structure 140b is formed by using a plating process, such as an electroplating process. Figure 1D

[0069] According to some embodiments, the conductive structure 140a and the conductive structure 140b over the conductive structure 140a collectively form a conductive plug structure 140. According to some embodiments, the substrate 110, the planarization layer 120, the bonding layer 130, the conductive plug structure 140, the planarization layer 150, and the bonding layer 160 collectively form a heat dissipation substrate 10. According to some embodiments, the heat dissipation substrate 10 has a thickness T10 in a range from about 0.5 μιη to about 50 μιη.

[0070] According to some embodiments, each conductive plug structure 140 has a bond pad portion 142, a bond pad portion 144, and a via portion 146. According to some embodiments, each bond pad portion 142 is over the surface 112. According to some embodiments, each bond pad portion 142 is in a corresponding opening 132 of the bonding layer 130. According to some embodiments, each bond pad portion 142 is through the bonding layer 130.

[0071] According to some embodiments, each bond pad portion 144 is over the surface 114. According to some embodiments, each bond pad portion 144 is in a corresponding opening 162 of the bonding layer 160. According to some embodiments, each bond pad portion 144 is through the bonding layer 160.

[0072] According to some embodiments, each via portion 146 is through the substrate 110. According to some embodiments, each via portion 146 is narrower than the bond pad portion 142 thereunder. That is, according to some embodiments, a width W146 of each via portion 146 is less than a width W142 of the bond pad portion 142 thereunder.

[0073] According to some embodiments, each via portion 146 is narrower than the bond pad portion 144 thereover. That is, according to some embodiments, a width W146 of each via portion 146 is less than a width W144 of the bond pad portion 144 thereover.

[0074] ​According to some embodiments, as shown in FIG. 1A, chip structures 20, 30, and 40, and heat spreading base 10A are provided. According to some embodiments, heat spreading base 10A includes base 110A, planarization layer 120A, bonding layer 130A, conductive plug structure 140A, planarization layer 150A, and bonding layer 160A. Figure 1E

[0075] According to some embodiments, the structures and materials of base 110A, planarization layer 120A, bonding layer 130A, conductive plug structure 140A, planarization layer 150A, and bonding layer 160A are similar to or the same as the structures and materials of base 110, planarization layer 120, bonding layer 130, conductive plug structure 140, planarization layer 150, and bonding layer 160, respectively.

[0076] According to some embodiments, the relative positions among base 110A, planarization layer 120A, bonding layer 130A, conductive plug structure 140A, planarization layer 150A, and bonding layer 160A are similar to or the same as the relative positions among base 110, planarization layer 120, bonding layer 130, conductive plug structure 140, planarization layer 150, and bonding layer 160.

[0077] In some embodiments, chip structures 20, 30, and 40 are wafers. In some other embodiments, chip structures 20, 30, and 40 are chips (or dies). According to some embodiments, thickness T20 of chip structure 20 is in a range from about 5 μιη to about 800 μιη. According to some embodiments, thickness T30 of chip structure 30 is in a range from about 5 μιη to about 800 μιη. According to some embodiments, thickness T40 of chip structure 40 is in a range from about 5 μιη to about 800 μιη.

[0078] According to some embodiments, as shown in FIG. 1A, chip structures 20, 30, and 40, and heat spreading base 10A are provided. According to some embodiments, heat spreading base 10A includes base 110A, planarization layer 120A, bonding layer 130A, conductive plug structure 140A, planarization layer 150A, and bonding layer 160A. Figure 1E

[0079] According to some embodiments, semiconductor base 210 has front surface 212 and back surface 214. According to some embodiments, devices, interconnect structures 220, and bonding pads 230 are formed over front surface 212 of semiconductor base 210. For simplicity and clarity purposes, these devices are not shown in the drawings.

[0080] ​​According to some embodiments, the semiconductor substrate 210 is made of an elemental semiconductor material including silicon or germanium in single-crystalline, poly crystalline, or amorphous structures. In some other embodiments, the semiconductor substrate 210 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination of the foregoing. The semiconductor substrate 210 can also include multiple layers of semiconductor, a semiconductor on insulator (SOI) (e.g., silicon on insulator or germanium on insulator), or a combination of the foregoing.

[0081] In some embodiments, devices are formed in and / or over the semiconductor substrate 210. Examples of various devices include active devices, passive devices, other suitable elements, or a combination of the foregoing. Active devices can include transistors or diodes formed at a surface of the semiconductor substrate 210. Passive devices include resistors, capacitors, or other suitable passive devices.

[0082] For example, a transistor can be a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS) field effect transistor, a bipolar junction transistor (BJT), a high voltage transistor, a high frequency transistor, a p-channel and / or n-channel field effect transistor (PFET / NFET), etc.

[0083] Various processes (e.g., front-end-of-line (FEOL) semiconductor fabrication processes) are performed to form various device elements. The front-end-of-line semiconductor fabrication processes can include deposition, etching, implantation, lithography, annealing, planarization, one or more other applicable processes, or a combination of the foregoing.

[0084] In some embodiments, isolation components (not shown) are formed in the semiconductor substrate 210. The isolation components are used to define active regions and various devices formed in and / or above the semiconductor substrate 210 that are electrically isolated. In some embodiments, the isolation components include shallow trench isolation (STI) components, local oxidation of silicon (LOCOS) components, other suitable isolation components, or combinations thereof.

[0085] According to some embodiments, an interconnect structure 220 is formed above the devices and the semiconductor substrate 210. According to some embodiments, the interconnect structure 220 includes dielectric layers, wiring layers, and vias. According to some embodiments, the wiring layers and vias are in the dielectric layers. According to some embodiments, the vias are electrically connected between the wiring layers and the devices.

[0086] According to some embodiments, the dielectric layers are made of an oxygen-containing material (e.g., silicon oxide or tetraethylorthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or fluorinated silicate glass (FSG)), or combinations thereof.

[0087] Alternatively, according to some embodiments, the dielectric layers include a low dielectric constant material or a porous dielectric material having a dielectric constant value less than that of silicon oxide or less than about 3.0 or about 2.5. According to some embodiments, the wiring layers and vias are made of an electrically conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0088] According to some embodiments, a bond pad 230 is formed above the interconnect structure 220. According to some embodiments, the bond pad 230 is electrically connected to the wiring layers and vias of the interconnect structure 220. According to some embodiments, the bond pad 230 is made of an electrically conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0089] According to some embodiments, a bonding layer 240 is formed above the back surface 214 of the semiconductor substrate 210. According to some embodiments, the bonding layer 240 is made of a dielectric material, such as amorphous silicon, SiO, SiON, SiN, SiCN, or AIN.

[0090] According to some embodiments, the conductive plug structures 250 pass through the semiconductor base 210 and the bonding layer 240. According to some embodiments, the conductive plug structures 250 are electrically connected to the wiring levels and vias of the interconnect structure 220 and the devices.

[0091] According to some embodiments, each conductive plug structure 250 has a bond pad portion 252 and a via portion 254. According to some embodiments, the bond pad portion 252 passes through the bonding layer 240. According to some embodiments, the via portion 254 passes through the semiconductor base 210.

[0092] According to some embodiments, the conductive plug structures 250 are made of a conductive material, such as a metal (e.g., titanium, copper, nickel, aluminum, gold, silver, or tungsten) or an alloy of the foregoing. According to some embodiments, the conductive plug structures 250 are formed by using a plating process, such as an electroplating process.

[0093] According to some embodiments, as shown in FIG. 3A, the chip structure 30 includes a semiconductor base 310, devices, an interconnect structure 320, conductive bond pads 330, bonding layers B1 and 340, and conductive plug structures 350. Figure 1E

[0094] According to some embodiments, the semiconductor base 310 has a front surface 312 and a back surface 314. According to some embodiments, the devices, the interconnect structure 320, the bonding layers B1, and the conductive bond pads 330 are formed over the front surface 312 of the semiconductor base 310. For simplicity and clarity, these devices are not shown in the drawings.

[0095] According to some embodiments, the semiconductor base 310 is made of an elemental semiconductor material including silicon or germanium in a single crystalline structure, a polycrystalline structure, or an amorphous structure. In some other embodiments, the semiconductor base 310 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination of the foregoing. The semiconductor base 310 can also include a multi-layer semiconductor, a semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or a combination of the foregoing.

[0096] In some embodiments, the devices are formed in and / or over the semiconductor base 310. Examples of various devices include active devices, passive devices, other suitable elements, or a combination of the foregoing. Active devices can include transistors or diodes formed at a surface of the semiconductor base 310. Passive devices include resistors, capacitors, or other suitable passive devices.

[0097] ​By way of example, the transistors can be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) field effect transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc. Various processes are performed (e.g., front end of line (FEOL) semiconductor manufacturing processes) to form various device elements. The FEOL semiconductor manufacturing processes can include deposition, etching, implantation, lithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

[0098] In some embodiments, isolation features (not shown) are formed in the semiconductor substrate 310. The isolation features are used to define active regions and electrically isolate various devices formed in and / or above the semiconductor substrate 310 in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

[0099] According to some embodiments, an interconnect structure 320 is formed above the devices and the semiconductor substrate 310. According to some embodiments, the interconnect structure 320 includes dielectric layers, wiring layers, and vias. According to some embodiments, the wiring layers and vias are in the dielectric layers. According to some embodiments, the vias are electrically connected between the wiring layers and the devices.

[0100] According to some embodiments, the dielectric layers are made of an oxygen-containing material (e.g., silicon oxide or tetraethyl orthosilicate (TEOS) oxide), a nitrogen-containing oxide material (e.g., silicon oxynitride), a glass material (e.g., borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorosilicate glass (FSG)), or a combination thereof.

[0101] Alternatively, according to some embodiments, the dielectric layers include a low dielectric constant material or a porous dielectric material having a dielectric constant value less than that of silicon oxide or less than about 3.0 or about 3.5. According to some embodiments, the wiring layers and vias are made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy thereof.

[0102] According to some embodiments, a bonding layer B1 is formed above the interconnect structure 320. According to some embodiments, the bonding layer B1 is made of a dielectric material, such as amorphous silicon, SiO, SiON, SiN, SiCN, or AIN.

[0103] According to some embodiments, electrically conductive bonding pads 330 are formed in the bonding layer Bl and the interconnect structure 320. According to some embodiments, the electrically conductive bonding pads 330 are electrically connected to the wiring levels and vias of the interconnect structure 320. According to some embodiments, the electrically conductive bonding pads 330 are made of an electrically conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy of the foregoing.

[0104] According to some embodiments, a bonding layer 340 is formed over the back surface 314 of the semiconductor substrate 310. According to some embodiments, electrically conductive plug structures 350 pass through the semiconductor substrate 310 and the bonding layer 340. According to some embodiments, each electrically conductive plug structure 350 has a bonding pad portion 352 and a via portion 354.

[0105] According to some embodiments, the bonding pad portion 352 passes through the bonding layer 340. According to some embodiments, the via portion 354 passes through the semiconductor substrate 310. According to some embodiments, the electrically conductive plug structures 350 are electrically connected to the wiring levels and vias of the interconnect structure 320 as well as the devices.

[0106] According to some embodiments, the electrically conductive plug structures 350 are made of an electrically conductive material, such as a metal (e.g., titanium, copper, nickel, aluminum, gold, silver, or tungsten) or an alloy of the foregoing. According to some embodiments, the electrically conductive plug structures 350 are formed using a plating process, such as an electroplating process.

[0107] According to some embodiments, as shown in FIG. 4B, the chip structure 40 includes a semiconductor substrate 410, devices, an interconnect structure 420, a bonding layer B2, and electrically conductive bonding pads 430. According to some embodiments, the semiconductor substrate 410 has a front surface 412 and a back surface 414. Figure 1E

[0108] According to some embodiments, the devices, the interconnect structure 420, the bonding layer B2, and the electrically conductive bonding pads 430 are formed over the front surface 412 of the semiconductor substrate 410. For simplicity and clarity purposes, these devices are not shown in the figures.

[0109] According to some embodiments, the semiconductor substrate 410 is made of an elemental semiconductor material including silicon or germanium in a single crystalline structure, a poly crystalline structure, or an amorphous structure. In some other embodiments, the semiconductor substrate 410 is made of a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide), an alloy semiconductor (e.g., SiGe or GaAsP), or a combination of the foregoing. The semiconductor substrate 410 can also include a multi-layer semiconductor, a semiconductor-on-insulator (SOI) (e.g., silicon-on-insulator or germanium-on-insulator), or a combination of the foregoing.

[0110] ​In some embodiments, devices are formed in and / or above semiconductor substrate 410. Examples of various devices include active devices, passive devices, other suitable elements, or combinations thereof. Active devices can include transistors or diodes formed at a surface of semiconductor substrate 410. Passive devices include resistors, capacitors, or other suitable passive devices.

[0111] For example, transistors can be metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) field effect transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), etc. Various processes, such as front end of line (FEOL) semiconductor manufacturing processes, are performed to form various device elements. FEOL semiconductor manufacturing processes can include deposition, etching, implantation, lithography, annealing, planarization, one or more other applicable processes, or combinations thereof.

[0112] In some embodiments, isolation components (not shown) are formed in semiconductor substrate 410. Isolation components are used to define active regions and electrically isolate various devices formed in and / or above semiconductor substrate 410 in the active regions. In some embodiments, isolation components include shallow trench isolation (STI) components, local oxidation of silicon (LOCOS) components, other suitable isolation components, or combinations thereof.

[0113] According to some embodiments, interconnect structure 420 is formed above devices and semiconductor substrate 410. According to some embodiments, interconnect structure 420 includes dielectric layers, wiring layers, and vias. According to some embodiments, wiring layers and vias are in dielectric layers. According to some embodiments, vias are electrically connected between wiring layers and devices.

[0114] According to some embodiments, dielectric layers are made of oxygen-containing materials (such as silicon oxide or tetraethyl orthosilicate (TEOS) oxide), nitrogen-containing oxide materials (such as silicon oxynitride), glass materials (such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or fluorosilicate glass (FSG)), or combinations thereof.

[0115] Alternatively, according to some embodiments, dielectric layers include low dielectric constant materials or porous dielectric materials having dielectric constant values less than silicon oxide or less than about 4.0 or about 4.5. According to some embodiments, wiring layers and vias are made of conductive materials, such as metals (such as copper, aluminum, gold, silver, or tungsten) or alloys thereof.

[0116] According to some embodiments, a bonding layer B2 is formed over the interconnect structure 420. According to some embodiments, the bonding layer B2 is made of a dielectric material, such as amorphous silicon, SiO, SiON, SiN, SiCN, or AIN.

[0117] According to some embodiments, a conductive bonding pad 430 is formed in the bonding layer B2. According to some embodiments, the conductive bonding pad 430 is electrically connected to the wiring layers and the via of the interconnect structure 320. According to some embodiments, the conductive bonding pad 430 is made of a conductive material, such as a metal (e.g., copper, aluminum, gold, silver, or tungsten) or an alloy of the foregoing.

[0118] According to some embodiments, the thermal conductivity of the substrate 110 (or the heat spreading substrate 10) is higher than the thermal conductivity of the chip structure 20. According to some embodiments, the thermal conductivity of the substrate 110 (or the heat spreading substrate 10) is higher than the thermal conductivity of the chip structure 30.

[0119] According to some embodiments, the thermal conductivity of the substrate 110A (or the heat spreading substrate 10A) is higher than the thermal conductivity of the chip structure 30. According to some embodiments, the thermal conductivity of the substrate 110A (or the heat spreading substrate 10A) is higher than the thermal conductivity of the chip structure 40.

[0120] According to some embodiments, as shown in FIG. 1A, the heat spreading substrate 10 is bonded between the chip structure 20 and the chip structure 30, and the heat spreading substrate 10A is bonded between the chip structure 30 and the chip structure 40. In some embodiments, the chip structure 20, the heat spreading substrate 10, the chip structure 30, the heat spreading substrate 10A, and the chip structure 40 are simultaneously bonded to each other. Figure 1F

[0121] According to some embodiments, the chip structure 30 is electrically connected to the chip structure 20 through the conductive plug structure 140 of the heat spreading substrate 10. According to some embodiments, the chip structure 40 is electrically connected to the chip structure 30 through the conductive plug structure 140A of the heat spreading substrate 10A.

[0122] According to some embodiments, the heat spreading substrate 10 directly contacts the chip structures 20 and 30. According to some embodiments, the bonding pad portion 142 of the heat spreading substrate 10 directly contacts the bonding pad portion 252 of the corresponding chip structure 20. According to some embodiments, the bonding pad portion 144 of the heat spreading substrate 10 directly contacts the conductive bonding pad 330 of the corresponding chip structure 30.

[0123] According to some embodiments, the bonding layer 240 of the chip structure 20 directly contacts the bonding layer 130 of the heat spreading substrate 10. According to some embodiments, the bonding layer B1 of the chip structure 30 directly contacts the bonding layer 160 of the heat spreading substrate 10.

[0124] ​According to some embodiments, the heat spreading base 10A directly contacts the chip structures 30 and 40. According to some embodiments, the bonding pad portion 142A of the heat spreading base 10A directly contacts the bonding pad portion 352 of the corresponding chip structure 30. According to some embodiments, the bonding pad portion 144A of the heat spreading base 10A directly contacts the conductive bonding pad 430 of the corresponding chip structure 40.

[0125] According to some embodiments, the bonding layer 340 of the chip structure 30 directly contacts the bonding layer 130A of the heat spreading base 10A. According to some embodiments, the bonding layer B2 of the chip structure 40 directly contacts the bonding layer 160A of the heat spreading base 10A.

[0126] According to some embodiments, as shown in FIG. 5, the conductive bumps 510 are formed on the bonding pads 230 of the chip structure 20. According to some embodiments, the conductive bumps 510 are made of metal or the aforementioned alloys, such as tin alloys. Figure 1G

[0127] According to some embodiments, if the chip structures 20, 30 and 40 are wafers, a dicing process (or sawing process) is performed to cut through the chip structures 20, 30 and 40 and the heat spreading bases 10 and 10A to form the chip package structures 100. According to some embodiments, for brevity, Figure 1G only one of the chip package structures 100 is shown.

[0128] According to some embodiments, when the chip package structure 100 is in operation, if the heat from the chip structures 20, 30 and 40 accumulates at hot spots, the hot spots can damage the chip structures 20, 30 and 40. According to some embodiments, since the thermal conductivities of the heat spreading bases 10 and 10A are greater than the thermal conductivities of the chip structures 20, 30 and 40, the heat spreading bases 10 and 10A can laterally spread the heat of the chip structures 20, 30 and 40, which prevents the heat from accumulating at the hot spots. Therefore, the reliability and performance of the chip package structure 100 are improved.

[0129] According to some embodiments, since this application does not change the structures and materials of the chip structures 20, 30 and 40, this application is compatible with the formation processes of existing chip package structures.

[0130] Figure 2 According to some embodiments, a cross-sectional schematic view of a chip package structure 200 is shown. According to some embodiments, as shown in FIG. 6, the chip package structure 200 is similar to the chip package structure 100 of Figure 2 Figure 1G except that the heat spreading base 10 is thicker than the heat spreading base 10A.

[0131] ​​According to some embodiments, the thickness T10 of the heat spreading base 10 is greater than the thickness T10A of the heat spreading base 10A. According to some embodiments, the thickness T110 of the base 110 of the heat spreading base 10 is greater than the thickness T110A of the base 110A of the heat spreading base 10A.

[0132] In some embodiments, the chip structure 20 has a greater heat generation efficiency than the chip structure 40. According to some embodiments, the chip structure 20 is hotter than the chip structure 40 when the chip package structure 200 is in operation.

[0133] According to some embodiments, the heat spreading base 10 can more effectively spread the heat of the chip structure 20 laterally because the heat spreading base 10 is thicker, which can effectively reduce the temperature of the chip structure 20. Therefore, according to some embodiments, the temperature of the chip package structure 200 is reduced, which improves the reliability and performance of the chip package structure 200.

[0134] Figure 3 According to some embodiments, a cross-sectional view of a chip package structure 300 is shown. According to some embodiments, as shown in FIG. 3, the chip package structure 300 is similar to the chip package structure 100 of FIG. 1, except that the heat spreading base 10A is thicker than the heat spreading base 10. Figure 3 Figure 1G

[0135] According to some embodiments, the thickness T10A of the heat spreading base 10A is greater than the thickness T10 of the heat spreading base 10. According to some embodiments, the thickness T110A of the base 110A of the heat spreading base 10A is greater than the thickness T110 of the base 110 of the heat spreading base 10.

[0136] In some embodiments, the chip structure 40 has a greater heat generation efficiency than the chip structure 20. According to some embodiments, the chip structure 40 is hotter than the chip structure 20 when the chip package structure 300 is in operation.

[0137] According to some embodiments, the heat spreading base 10A can more effectively spread the heat of the chip structure 40 laterally because the heat spreading base 10A is thicker, which can effectively reduce the temperature of the chip structure 40. Therefore, according to some embodiments, the temperature of the chip package structure 300 is reduced, which improves the reliability and performance of the chip package structure 300.

[0138] Figure 4 According to some embodiments, a cross-sectional view of a chip package structure 400 is shown. According to some embodiments, as shown in FIG. 4, the chip package structure 400 is similar to the chip package structure 100 of FIG. 1, except that the heat spreading base 10B is thicker than the heat spreading base 10. Figure 4 Figure 1G ​​​The chip package structure 100 is similar to the chip package structure 100 except that the bond pad portion 142 of each conductive plug structure 140 is wider than the bond pad portion 252 of each conductive plug structure 250, and the bond pad portion 142A of each conductive plug structure 140A is wider than the bond pad portion 352 of each conductive plug structure 350.

[0139] According to some embodiments, the bond pad portion 144 of each conductive plug structure 140 is wider than the conductive bond pad 330. According to some embodiments, the bond pad portion 144A of each conductive plug structure 140A is wider than the conductive bond pad 430.

[0140] According to some embodiments, the heat spreading base 10 does not have devices (including active devices and passive devices) and wiring layers, so the heat spreading base 10 has more space to accommodate the bond pad portions 142 and 144. According to some embodiments, the (wide) bond pad portion 142 can improve the yield of the bonding process of the bond pad portion 142 with the bond pad portion 252 of the conductive plug structure 250 of the chip structure 20. According to some embodiments, the (wide) bond pad portion 144 can improve the yield of the bonding process of the bond pad portion 144 with the conductive bond pad 330 of the chip structure 30.

[0141] According to some embodiments, the heat spreading base 10A does not have devices (including active devices and passive devices) and wiring layers, so the heat spreading base 10A has more space to accommodate the bond pad portions 142A and 144A.

[0142] According to some embodiments, the (wide) bond pad portion 142A can improve the yield of the bonding process of the bond pad portion 142A with the bond pad portion 352 of the conductive plug structure 350 of the chip structure 30. According to some embodiments, the (wide) bond pad portion 144A can improve the yield of the bonding process of the bond pad portion 144A with the conductive bond pad 430 of the chip structure 40.

[0143] The processes and materials for forming the chip package structures 200, 300 and 400 can be similar to or the same as the processes and materials described above for forming the chip package structure 100. Figures 1A to 4 Elements that are labeled by the same reference symbols in the various figures have the same or similar structures and materials. Therefore, their detailed descriptions are not repeated here.

[0144] According to some embodiments, chip package structures and methods of forming the same are provided. The methods (for forming the chip package structures) form a heat spreading base between two chip structures to spread the heat of the chip structures laterally, which prevents heat from accumulating at hot spots. Therefore, the reliability and performance of the chip package structures with the heat spreading base are improved.

[0145] According to some embodiments, a chip package structure is provided, the chip package structure includes a first chip structure; the chip package structure includes a heat dissipation base located above the first chip structure, the heat dissipation base includes a base and a conductive plug structure, a first thermal conductivity of the base is higher than a second thermal conductivity of the first chip structure, the base has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, and the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; the chip package structure includes a second chip structure located above the heat dissipation base, the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the base is higher than a third thermal conductivity of the second chip structure, and the heat dissipation base contacts the first chip structure and the second chip structure.

[0146] In some other embodiments, wherein the base of the heat dissipation base is made of a dielectric material.

[0147] In some other embodiments, wherein the heat dissipation base further includes: a first bonding layer located above the first surface of the base, the first bonding layer directly contacts the first chip structure, and the first bonding pad portion passes through the first bonding layer.

[0148] In some other embodiments, wherein the first thermal conductivity of the base is higher than a fourth thermal conductivity of the first bonding layer.

[0149] In some other embodiments, wherein the heat dissipation base further includes: a second bonding layer located above the second surface of the base, the second bonding layer directly contacts the second chip structure, and the second bonding pad portion passes through the second bonding layer.

[0150] In some other embodiments, wherein the heat dissipation base further includes: a first planarization layer located between the first bonding layer and the base, and a third surface of the first planarization layer is away from the base and is flatter than the first surface of the base.

[0151] In some other embodiments, wherein the heat dissipation base further includes: a second planarization layer located between the second bonding layer and the base, and a fourth surface of the second planarization layer is away from the base and is flatter than the second surface of the base.

[0152] In some other embodiments, wherein the via portion passes through the base and is narrower than both the first bonding pad portion and the second bonding pad portion.

[0153] According to some embodiments, a chip package structure is provided, the chip package structure includes a first chip structure; the chip package structure includes a first heat dissipation base located on and engaged with the first chip structure, the first heat dissipation base includes a base and a conductive plug structure, the first thermal conductivity of the base is higher than the second thermal conductivity of the first chip structure, the base has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; the chip package structure includes a conductive bump located below and engaged with the first chip structure.

[0154] In some other embodiments, the chip package structure further includes a second chip structure located above the first heat dissipation base, wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the base is higher than the third thermal conductivity of the second chip structure, and the first heat dissipation base directly contacts the second chip structure; and a second heat dissipation base located above the second chip structure, wherein the fourth thermal conductivity of the second heat dissipation base is higher than the third thermal conductivity of the second chip structure.

[0155] In some other embodiments, the first heat dissipation base is thicker than the second heat dissipation base.

[0156] In some other embodiments, the first chip structure has a first conductive bonding pad, the first conductive bonding pad is directly engaged with the first bonding pad portion of the first heat dissipation base, and the first bonding pad portion is wider than the first conductive bonding pad.

[0157] In some other embodiments, the second chip structure has a second conductive bonding pad, the second conductive bonding pad is directly engaged with the second bonding pad portion of the first heat dissipation base, and the second bonding pad portion is wider than the second conductive bonding pad.

[0158] According to some embodiments, a method for forming a chip package structure is provided, the method includes forming a first heat dissipation base, the first heat dissipation base includes a base and a conductive plug structure, the base has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; the method includes engaging the first heat dissipation base to a first chip structure, the first thermal conductivity of the base is higher than the second thermal conductivity of the first chip structure; the method includes engaging a second chip structure to the first heat dissipation base, the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the base is higher than the third thermal conductivity of the second chip structure, and the first heat dissipation base contacts the first chip structure and the second chip structure.

[0159] In some other embodiments, the first heat spreading base is simultaneously bonded to the first chip structure and the second chip structure is simultaneously bonded to the first heat spreading base.

[0160] In some other embodiments, the step of forming the first heat spreading base includes: providing a base; partially removing the base to form a via through the base; and forming a conductive plug structure in the via and over the first surface and the second surface.

[0161] In some other embodiments, the step of forming the first heat spreading base includes: forming a bonding layer over the first surface of the base prior to partially removing the base; and partially removing the bonding layer to form an opening in the bonding layer prior to partially removing the base, wherein the first bonding pad portion is located in the opening.

[0162] In some other embodiments, the step of forming the first heat spreading base includes forming a planarization layer over the first surface of the base prior to forming the bonding layer, wherein the step of partially removing the base further includes partially removing the planarization layer, and the via is through the planarization layer.

[0163] In some other embodiments, the method further includes bonding a second heat spreading base to the second chip structure, wherein a fourth thermal conductivity of the second heat spreading base is higher than a third thermal conductivity of the second chip structure.

[0164] In some other embodiments, the method further includes forming a conductive bump on a surface of the first chip structure, wherein the surface is away from the first heat spreading base.

[0165] The foregoing outlines features of many embodiments, such that those skilled in the art can improve the design of other processes and structures without departing from the spirit and scope of the present embodiments. Those skilled in the art will appreciate that they can readily use the conception disclosed with this document for the purposes listed above. Those skilled in the art will appreciate that they can readily use the conception disclosed with this document for the purposes listed above. Their applications thus are not limited to those implementations disclosed but are only limited by the true spirit and scope of this document. Embodiments disclosed in this document encompass all alternatives, modifications, and equivalents of the methods and structures disclosed.

Claims

1. A chip package structure, characterized by, comprising: a first chip structure; a heat dissipation base located above the first chip structure, wherein the heat dissipation base comprises a base and a conductive plug structure, a first thermal conductivity of the base is higher than a second thermal conductivity of the first chip structure, the base has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, and the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; and a second chip structure located above the heat dissipation base, wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the base is higher than a third thermal conductivity of the second chip structure, and the heat dissipation base contacts the first chip structure and the second chip structure. The heat dissipation base further comprises:

2. The chip package structure of claim 1, wherein, a first bonding layer located above the first surface of the base, the first bonding layer directly contacts the first chip structure, and the first bonding pad portion passes through the first bonding layer. The heat dissipation base further comprises:

3. The chip package structure of claim 2, wherein, a second bonding layer located above the second surface of the base, the second bonding layer directly contacts the second chip structure, and the second bonding pad portion passes through the second bonding layer. The heat dissipation base further comprises:

4. The chip package structure of claim 3, wherein, a first planarization layer located between the first bonding layer and the base, and a third surface of the first planarization layer is away from the base and is flatter than the first surface of the base. The heat dissipation base further comprises:

5. The chip package structure of claim 4, wherein, a second planarization layer located between the second bonding layer and the base, and a fourth surface of the second planarization layer is away from the base and is flatter than the second surface of the base. comprising:

6. A chip package structure, characterized by, a first chip structure; a first heat dissipation base located on and bonded to the first chip structure, wherein the first heat dissipation base comprises a base and a conductive plug structure, a first thermal conductivity of the base is higher than a second thermal conductivity of the first chip structure, the base has a first surface and a second surface, the conductive plug structure has a first bonding pad portion, a second bonding pad portion and a via portion, and the first bonding pad portion and the second bonding pad portion are located above the first surface and the second surface respectively; and a conductive bump located below and bonded to the first chip structure. Further comprising: a second chip structure located above the first heat dissipation base, wherein the second chip structure is electrically connected to the first chip structure through the conductive plug structure, the first thermal conductivity of the base is higher than a third thermal conductivity of the second chip structure, and the first heat dissipation base directly contacts the second chip structure; and 7. The chip package structure of claim 6, wherein, a second heat dissipation base located above the second chip structure, wherein a fourth thermal conductivity of the second heat dissipation base is higher than the third thermal conductivity of the second chip structure. The first heat dissipation base is thicker than the second heat dissipation base. The first chip structure has a first conductive bonding pad, the first conductive bonding pad is directly bonded to the first bonding pad portion of the first heat dissipation base, and the first bonding pad portion is wider than the first conductive bonding pad.

8. The chip package structure of claim 7, wherein, ​ 9. The chip package structure of claim 7 or 8, wherein, ​ 10. The chip package structure of claim 9, wherein, The second chip structure has a second conductive bonding pad that is directly bonded to the second bonding pad portion of the first heat spreading base, and the second bonding pad portion is wider than the second conductive bonding pad.

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