Narrow memory bank

Abstract

The narrow memory bank comprises a memory bank body, two ends of the memory bank body are provided with a first groove, a second groove, a third groove and a fourth groove, the first groove and the second groove are symmetrically arranged, the third groove and the fourth groove are symmetrically arranged, the edge of the bottom side of the memory bank body is provided with a fifth groove, and the distance between the upper edge of the first groove and the upper peripheral edge of the second groove is 3.65-12.65 mm. The distance between the upper edge of the groove III and the upper peripheral edge of the groove IV is 10.25-19.25 mm; the distance between the inner top end of the fifth groove and the upper peripheral edge is 17.4-26.4 mm, the distance between the bottom edge where the fifth groove is located and the upper peripheral edge is 30.25 mm, the distance between the side bottom edges where the first groove and the second groove are located and the upper peripheral edge is 29.75 mm, and a typical address line AO of the memory bank body is connected to the inner layer L6 in the layer L1 through wiring and holes from the second position of the concave corner. By optimizing the distance between the groove and the upper peripheral edge and adjusting the layout structure of the address lines, the memory bank is narrowed, the signal transmission performance is optimized, and the memory bank not only has a compact size, but also has high stability and reliability.

Description

Technical Field

[0001] This utility model belongs to the field of memory module technology, and specifically relates to a narrow memory module. Background Technology

[0002] Memory modules, also known as random access memory (RAM) or main memory, are internal storage devices that directly exchange data with the CPU. The primary function of memory modules is to temporarily store programs, data, and intermediate results so that the CPU can access them quickly. Compared to hard drives, memory modules have much faster read and write speeds, significantly improving the computer's operating speed and efficiency. When a computer runs a program, it loads the necessary data and instructions from the hard drive into the memory modules, and then the CPU reads the data from the memory modules for processing.

[0003] Current memory modules still have the following drawbacks:

[0004] 1. For example Figure 1 As shown, the traditional design distance is:

[0005] The distance between the upper edge of groove 1 and groove 2 5 and the upper outer edge is 13.65mm;

[0006] The upper edge of groove 3.2 and groove 4 is 20.25mm away from the upper outer edge;

[0007] The distance from the top of the inner edge of groove 53 is 27.4mm.

[0008] The bottom edge of groove 53 is wider than the side edge of groove 1 and groove 25. That is, the bottom edge of groove 53 is 31.25mm away from the upper outer edge, and the bottom edge of groove 1 and groove 25 is 30.75mm away from the upper outer edge.

[0009] 2. Typical address line AO:

[0010] like Figure 2 As shown, AO starts from the second position of the concave corner, and is connected to the inner L6 layer through wiring on the L1 surface via holes. When the wiring on the L6 layer passes under the chip BGA, the surface pads of the chip BGA are connected to the inner L6 layer through holes.

[0011] 3. Typical address line A11:

[0012] like Figure 4 As shown, A11 starts from the second position of the concave corner, and is connected to the inner L3 layer through wiring on the L1 surface via a hole. When the wiring on the L3 layer passes under the chip BGA, the surface pads of the chip BGA are connected to the inner L3 layer through a hole.

[0013] The above traditional design results in current memory modules having problems such as signal instability, high interference, and severe signal attenuation.

[0014] To address this, a narrow-type memory module is proposed. Utility Model Content

[0015] The purpose of this invention is to provide a narrow memory module to solve the technical defects of existing memory modules, such as signal instability, large interference, and severe attenuation.

[0016] To achieve the above objectives, this utility model provides the following technical solution:

[0017] A narrow memory module includes a memory module body, the two ends of which have symmetrically arranged grooves one and two, and symmetrically arranged grooves three and four, and the bottom edge of the memory module body has a groove five;

[0018] The distance between the upper edge of groove one and groove two and the upper outer edge is 3.65-12.65mm;

[0019] The distance from the upper edge of grooves three and four to the upper outer edge is 10.25-19.25mm;

[0020] The distance from the top of the innermost groove to the outermost edge is 17.4-26.4 mm;

[0021] The bottom edge of groove five is 30.25mm from the upper outer edge, and the bottom edge of groove one and groove two is 29.75mm from the upper outer edge.

[0022] As a further embodiment of this invention, the typical address line AO ​​of the memory module body starts from the second position of the concave corner, is routed on the L1 layer, and connected to the inner L6 layer through a hole. The trace is then routed on the L6 layer. When it passes under the chip BGA, the surface pad of the chip BGA is connected to the inner L6 layer through a hole. At the same time, a line is added at the corresponding position on the L3 layer to improve the signal transmission effect.

[0023] As a further embodiment of this invention, the typical address line A11 of the memory module body starts from the second position of the concave corner or the finger position, and is routed through the L1 layer or L8 layer, respectively, and connected to the inner L3 layer through a hole. The trace is then routed in the L3 layer. When it passes under the chip BGA, the surface pad of the chip BGA is connected to the inner L3 layer through a hole. At the same time, a line is added at the corresponding position in the L6 layer to reduce signal attenuation and improve transmission effect.

[0024] Compared with existing technologies, the narrow memory module provided by this utility model has the following advantages:

[0025] This narrow memory module achieves a narrow design and optimizes signal transmission performance by modifying the distance between the groove and the periphery and adjusting the layout of the address lines. It not only has a compact size but also high stability and reliability, making it suitable for various electronic devices that require high-performance signal transmission. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only examples of embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a memory module in the prior art;

[0028] Figure 2 This is a schematic diagram of typical address line (AO) routing for memory modules in the prior art.

[0029] Figure 3 This is a schematic diagram of typical address line (AO) wiring of a memory module according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of typical address line A11 routing in a memory module in the prior art;

[0031] Figure 5 This is a schematic diagram of typical address line A11 wiring of a memory module according to an embodiment of the present invention.

[0032] Figure label:

[0033] 1. Groove One; 2. Groove Three; 3. Groove Five; 4. Groove Four; 5. Groove Two. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the embodiments of this utility model will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0035] In the description of the embodiments of this utility model, it should be understood that the terms "upper", "lower", "front", "rear", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this utility model.

[0036] In the description of the embodiments of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, an integral connection, or a detachable connection; they can refer to the internal connection of two components; they can refer to a direct connection or an indirect connection through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in the embodiments of this utility model can be understood according to the specific circumstances.

[0037] See appendix Figure 1-5 As shown in the figure, a narrow memory module according to an embodiment of the present invention includes a memory module body. The two ends of the memory module body have symmetrically arranged grooves 1 and 5, grooves 2 and 4, and the bottom edge of the memory module body has a groove 3.

[0038] The distance from the upper edge of groove 1 and groove 2 5 to the upper outer edge is 3.65-12.65mm;

[0039] The distance from the upper edge of groove 3 (2) and groove 4 (4) to the upper outer edge is 10.25-19.25mm;

[0040] The distance from the top of the inner edge of groove 53 to the outer edge is 17.4-26.4mm.

[0041] Compared to the traditional groove 1 and groove 2 5, where the distance between the upper edge of the groove 1 and groove 2 5 is 13.65mm from the upper outer edge; the distance between the upper edge of the groove 3 2 and groove 4 4 ​​is 20.25mm from the upper outer edge; and the distance between the inner top of the groove 5 3 and the upper outer edge is 27.4mm, the distance between the groove 1 and groove 2 5, groove 3 2 and groove 4 4, and groove 5 3 and the upper outer edge in the narrow memory module of this utility model embodiment is greatly optimized.

[0042] The bottom edge of groove 53 is 30.25mm from the upper outer edge, and the bottom edge of groove 1 and groove 25 is 29.75mm from the upper outer edge. Compared with the traditional memory module body, the memory module body of this utility model embodiment is shortened and narrowed as a whole.

[0043] like Figure 3 As shown, the typical address line AO ​​of the memory module starts from the second position of the concave corner, is routed on the L1 surface, and connected to the inner L6 layer through a via. When the L6 layer trace passes under the chip BGA, the surface pads of the chip BGA are connected to the inner L6 layer through a via. The via will generate a capacitance effect, affecting signal transmission. The connection lines under the BGA and the via positions will cause signal attenuation. By adding a small line at the corresponding position on the L3 layer, the improvement effect is obvious after simulation and actual application, and the signal transmission effect can be improved.

[0044] like Figure 5As shown, the typical address line A11 of the memory module starts from the finger position, is routed on the L8 side, and connected to the inner L3 layer through a via. When the L3 layer trace passes under the chip BGA, the surface pads of the chip BGA are connected to the inner L3 layer through vias. The vias will generate a capacitance effect, affecting signal transmission. The connection lines under the BGA and the via positions will cause signal attenuation. By adding a small line at the corresponding position on the L6 layer, simulation and actual application show that the improvement effect is obvious, which can significantly reduce signal attenuation and improve transmission performance.

[0045] The above-mentioned solution for a narrow memory module not only achieves a narrower physical size by reducing the distance between the groove and the periphery and adjusting the layout of the address lines, but also optimizes signal transmission performance, improves signal stability, reduces interference and attenuation, and enhances the stability and reliability of the memory module.

[0046] In summary, this embodiment of the invention provides a narrow memory module that achieves a narrow design and optimizes signal transmission performance by modifying the distance between the groove and the periphery and adjusting the layout of the address lines. This memory module not only has a compact size but also high stability and reliability, making it suitable for various electronic devices requiring high-performance signal transmission.

[0047] The above description illustrates the basic principles of the present invention. The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. The above embodiments and descriptions in the specification are only for illustrating the principles of the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and scope of the present invention without departing from the scope of the present invention should be included within the protection scope of the present invention.

Claims

1. A narrow memory module, comprising a memory module body, characterized in that: The memory module body has symmetrically arranged groove 1 (1) and groove 2 (5) at both ends, and symmetrically arranged groove 3 (2) and groove 4 (4) at both ends, and groove 5 (3) is provided on the bottom edge of the memory module body. The distance between the upper edge of the first groove (1) and the second groove (5) and the upper outer edge is 3.65-12.65mm; The distance between the upper edge of the third (2) and the fourth (4) groove and the upper outer edge is 10.25-19.25 mm; the distance between the inner top of the fifth (3) groove and the upper outer edge is 17.4-26.4 mm; The bottom edge of groove five (3) is 30.25mm from the upper outer edge, and the bottom edge of groove one (1) and groove two (5) is 29.75mm from the upper outer edge.

2. A narrow memory module according to claim 1, characterized in that: The typical address line AO ​​of the memory module body starts from the second position of the concave corner, is routed in the L1 layer, and connected to the inner L6 layer through a hole. The trace is then routed in the L6 layer. When it passes under the chip BGA, the surface pad of the chip BGA is connected to the inner L6 layer through a hole. At the same time, a line is added at the corresponding position in the L3 layer.

3. A narrow memory module according to claim 2, characterized in that: The typical address line A11 of the memory module body starts from the second position of the concave corner or the finger position, and is routed through the L1 layer or L8 layer, respectively, and connected to the inner L3 layer through the hole. The trace is then routed in the L3 layer. When it passes under the chip BGA, the surface pad of the chip BGA is connected to the inner L3 layer through the hole. At the same time, a line is added at the corresponding position in the L6 layer.

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