Discrete magnitude input and output card
By designing a discrete input/output card that integrates a main control module, a power conversion module, and an ESD module, the reliability and electrostatic protection issues of discrete input/output signals are solved, enabling highly reliable inter-device communication.
Patent Information
- Application Number
- CN202423188649.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-12-23
AI Technical Summary
In existing technologies, the reliability of discrete input/output signals and electrostatic discharge protection issues have not been effectively resolved, affecting the quality of communication between devices.
A discrete input/output card was designed, comprising a main control module, a power conversion module, a driver module, and an ESD module. It uses components such as an FPGA chip, a CPCI bridge chip, a driver chip, a PMOS transistor, and a TVS transistor to achieve signal control and electrostatic protection.
It improves the reliability of discrete signal input and output, has electrostatic protection function, and ensures the stability and efficiency of communication between devices.
Smart Images
Figure CN223552027U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of discrete input / output control, and in particular to a discrete input / output card. Background Technology
[0002] Electronic devices communicate, access status, and control data through discrete input and output signals. For example, in vehicle-mounted, airborne, and shipborne control systems, discrete input signals are responsible for acquiring status information from these devices or receiving control information from them; discrete output signals are responsible for sending control information to these devices or returning status information to them. The quality of both discrete input and output signals is crucial to the quality of communication between devices; therefore, highly reliable discrete signal input / output devices are essential. Utility Model Content
[0003] In response to the aforementioned problems and technical requirements, the applicant has proposed a discrete input / output card.
[0004] The technical solution of this utility model is as follows:
[0005] A discrete input / output card includes a main control module, a power conversion module, a driver module, and an ESD module;
[0006] The power conversion module is connected to the main control module and the drive module, and is used to supply power to the main control module and the drive module; the main control module is connected to the drive module, and is used to control the drive module to output discrete output signals or receive discrete input signals; the ESD module is connected to the drive module, and is used to provide electrostatic protection.
[0007] A further technical solution is that the driving module includes several driving units, each driving unit including a first driving chip, a second driving chip, and multiple level control circuits. The first driving chip and the second driving chip each include multiple signal pins. The multiple signal pins of the second driving chip are connected one-to-one with the multiple level control circuits, and the multiple level control circuits are connected one-to-one with the multiple signal pins of the first driving chip.
[0008] A further technical solution is that the level control circuit includes a switching device Q1, a resistor R139, a resistor R155, and a resistor R631, wherein...
[0009] The third electrode of the switching device Q1 is grounded through resistor R155. The second electrode of the switching device Q1 is connected to the corresponding signal pins of the first driver chip and the second driver chip. The second electrode of the switching device Q1 is connected to one end of resistor R139 through resistor R631 and connected to the power supply voltage. The other end of resistor R139 is connected to the first electrode of the switching device Q1.
[0010] A further technical solution is that the switching device Q1 is a PMOS transistor.
[0011] A further technical solution is that the ESD module includes multiple ESD branches that are connected one-to-one with the level control circuit, and the multiple ESD branches are connected in parallel with each other.
[0012] The ESD branch includes a first TVS diode and a second TVS diode. The anode of the first TVS diode is connected to the cathode of the second TVS diode and is connected to the third electrode of the switching device Q1 in the corresponding level control circuit. The anode of the second TVS diode is grounded.
[0013] A further technical solution is that the ESD module also includes a total TVS diode connected in parallel with multiple ESD branches;
[0014] The cathode of the main TVS tube is connected to the cathode of the first TVS tube in each ESD branch, and the anode of the main TVS tube is grounded.
[0015] A further technical solution is that the main control module includes an FPGA chip and a CPCI bridge chip, the CPCI bridge chip is connected to the FPGA chip, and the FPGA chip is connected to the driver module.
[0016] The further technical solution is that the FPGA chip is model XC7A75T-2FGG484I and the CPCI bridge chip is model PCI9054.
[0017] A further technical solution is that the power conversion module includes a first power conversion chip for supplying power to the FPGA chip;
[0018] The first power conversion chip is model TPS54821RHLR. The first power conversion chip includes VIN pin, EN pin, PVIN1 pin, PVIN2 pin, BOOT pin, PH1 pin, PH2 pin and V_SNS pin.
[0019] A further technical solution is that the PVIN1 pin, PVIN2 pin, and VIN pin are grounded through capacitor C195, and the PVIN1 pin, PVIN2 pin, and VIN pin are also grounded through capacitor C197 and connected to the input voltage.
[0020] The EN pin is connected to the PVIN1 pin, PVIN2 pin, and VIN pin via resistor R599;
[0021] The BOOT pin is connected to the PH1 and PH2 pins through capacitor C196. The PH1 and PH2 pins are connected to one end of resistor R600 and the power supply pin of the FPGA chip through inductor L1. The other end of resistor R600 is connected to the V_SNS pin and grounded through resistor R602.
[0022] The power supply pin of the FPGA chip is grounded through capacitor C198, which is connected in parallel with capacitor C199.
[0023] The beneficial technical effects of this utility model are:
[0024] The discrete input / output card provided by this utility model integrates discrete input / output functions. It can control the driver module to output discrete output signals or receive discrete input signals through the main control module. It can independently control the on / off state of each discrete output / input path and the pull-up / pull-down state of the discrete signal. It also has electrostatic discharge protection, ensuring high reliability. Attached Figure Description
[0025] Figure 1 This is a schematic block diagram of one embodiment of the discrete input / output card provided by this utility model.
[0026] Figure 2 This is a pin diagram of one embodiment of the driver chip provided by this utility model.
[0027] Figure 3 This is a circuit diagram of one embodiment of the level control circuit provided by this utility model.
[0028] Figure 4 This is a circuit schematic diagram of one embodiment of the ESD module provided by this utility model.
[0029] Figure 5 This is a circuit schematic diagram of one embodiment of the first power conversion chip provided by this utility model. Detailed Implementation
[0030] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings.
[0031] This utility model provides a discrete input / output card, including a main control module, a power conversion module, a driver module, and an ESD module;
[0032] The power conversion module is connected to the main control module and the drive module, and is used to supply power to the main control module and the drive module; the main control module is connected to the drive module, and is used to control the drive module to output discrete output signals or receive discrete input signals; the ESD module is connected to the drive module, and is used to provide electrostatic protection.
[0033] Specifically, the main control module includes an FPGA chip and a CPCI bridge chip. The CPCI bridge chip is connected to the FPGA chip, and the FPGA chip is connected to the driver module. The CPCI bridge chip is also connected to connector J1. Connector J1 receives PCI signals and transmits them to the FPGA chip through the CPCI bridge chip. The FPGA chip controls the driver module according to the PCI signals. In this embodiment, the FPGA chip used is the Xilinx XC7A75T-2FGG484I, which has abundant built-in Block RAM resources and 75,520 logic units. The CPCI bridge chip used is the PCI9054, a 32-bit, 33MHz PCI bus master I / O accelerator from PLX. The FPGA chip is also connected to a JTAG interface, a FLASH chip, and a clock chip for providing a clock reference.
[0034] Furthermore, the driving module includes several driving units, each driving unit including a first driving chip, a second driving chip, and multiple level control circuits. Both the first driving chip and the second driving chip include multiple signal pins. The multiple signal pins of the second driving chip are connected one-to-one with the multiple level control circuits, and the multiple level control circuits are connected one-to-one with the multiple signal pins of the first driving chip.
[0035] Specifically, the signal pins of the first driver chip are used to form discrete input / output paths, and under the control of the FPGA chip, it can receive discrete input signals and output discrete output signals. The driver chip model can be SN74ALVC164245DGGR. Figure 2 The diagram shows a pinout of one embodiment of the driver chip, where pins 1Q-8Q are signal pins.
[0036] like Figure 3 As shown, any level control circuit includes a switching device Q1, a resistor R139, a resistor R155, and a resistor R631. The third electrode of the switching device Q1 is grounded through the resistor R155. The second electrode of the switching device Q1 is electrically connected to the corresponding signal pins of the first driver chip and the second driver chip. The second electrode of the switching device Q1 is connected to one end of the resistor R139 through the resistor R631 and connected to the power supply voltage. The other end of the resistor R139 is connected to the first electrode of the switching device Q1.
[0037] In this embodiment, the switching device Q1 is a PMOS transistor. For a PMOS transistor, the first electrode is the source, the second electrode is the gate, and the third electrode is the drain. In specific implementations, the switching device Q1 can also be other power devices with switching functions. The gate of the PMOS transistor is connected to the corresponding signal pin of the first driver chip through a protection resistor. The second driver chip is used to control the conduction state of the PMOS transistor, thereby controlling the pull-up or pull-down of the discrete output signal of the corresponding signal pin of the first driver chip. When the PMOS transistor is on, the discrete output signal is pulled down to ground potential; when the PMOS transistor is off, the discrete output signal is pulled up to the supply voltage. In this embodiment, the supply voltage is 5V.
[0038] Furthermore, the ESD module includes multiple ESD branches that are connected one-to-one with the level control circuit, and the multiple ESD branches are connected in parallel with each other.
[0039] Figure 4 Four ESD branches are shown, such as Figure 4 As shown, the ESD branch includes a first TVS (transient voltage suppressor) transistor and a second TVS transistor. The anode of the first TVS transistor is connected to the cathode of the second TVS transistor and is connected to the third electrode of the switching device Q1 in the corresponding level control circuit. The anode of the second TVS transistor is grounded.
[0040] Specifically, the ESD module is also connected to a connector, and the ESD module also includes a main TVS diode connected in parallel with multiple ESD branches; the cathode of the main TVS diode is connected to the cathode of the first TVS diode in each ESD branch, and the anode of the main TVS diode is grounded. The anode of the first TVS diode in the ESD branch is connected to the cathode of the second TVS diode to form a connection terminal that is connected to the drain of the PMOS transistor. When the reverse voltage of the TVS diode is greater than the breakdown voltage, the TVS diode conducts, protecting the circuit from transient high-voltage spike pulses.
[0041] Furthermore, the power conversion module includes a first power conversion chip for powering the FPGA chip; the first power conversion chip is model TPS54821RHLR, and the first power conversion chip includes VIN pin, EN pin, PVIN1 pin, PVIN2 pin, BOOT pin, PH1 pin, PH2 pin and V_SNS pin.
[0042] Figure 5The pin diagram of the first power conversion chip is shown. The PVIN1, PVIN2, and VIN pins are grounded through capacitor C195. The PVIN1, PVIN2, and VIN pins are also grounded and connected to the input voltage through capacitor C197. Capacitors C195 and C197 serve as voltage regulators and filters. The input voltage, 5V, can be introduced from the power supply pins of the CPCI bridge chip. The EN pin is connected to the PVIN1, PVIN2, and VIN pins through resistor R599. The first power conversion chip also includes a COMP pin, which is grounded through resistor R605 and capacitor C204. Resistor R605 and capacitor C204 are connected in series and then in parallel with capacitor C205.
[0043] The BOOT pin is connected to the PH1 and PH2 pins via capacitor C196. The PH1 and PH2 pins are connected to one end of resistor R600 and the power supply pins of the FPGA chip via inductor L1. The other end of resistor R600 is connected to the V_SNS pin and grounded via resistor R602. The power supply pins of the FPGA chip are grounded via capacitor C198, which is connected in parallel with capacitor C199. The first power conversion chip converts the 5V input voltage to a 1V supply voltage to power the FPGA chip. It should be noted that the power conversion module also includes multiple power conversion chips for powering the driver chip and CPCI bridge chip, each converting the supply voltage to the operating voltage required by its corresponding chip.
[0044] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. A discrete input / output card, characterized in that, It includes a main control module, a power conversion module, a driver module, and an ESD module; The power conversion module is connected to the main control module and the drive module, and is used to supply power to the main control module and the drive module; the main control module is connected to the drive module, and is used to control the drive module to output discrete output signals or receive discrete input signals; the ESD module is connected to the drive module, and is used to provide electrostatic protection.
2. The discrete input / output card according to claim 1, characterized in that, The driving module includes several driving units. Each driving unit includes a first driving chip, a second driving chip, and multiple level control circuits. Both the first driving chip and the second driving chip include multiple signal pins. The multiple signal pins of the second driving chip are connected one-to-one with the multiple level control circuits. The multiple level control circuits are connected one-to-one with the multiple signal pins of the first driving chip.
3. The discrete input / output card according to claim 2, characterized in that, The level control circuit includes a switching device Q1, resistors R139, R155, and R631, wherein... The third electrode of the switching device Q1 is grounded through resistor R155. The second electrode of the switching device Q1 is connected to the corresponding signal pins of the first driver chip and the second driver chip. The second electrode of the switching device Q1 is connected to one end of resistor R139 through resistor R631 and connected to the power supply voltage. The other end of resistor R139 is connected to the first electrode of the switching device Q1.
4. The discrete input / output card according to claim 3, characterized in that, The switching device Q1 is a PMOS transistor.
5. The discrete input / output card according to claim 3, characterized in that, The ESD module includes multiple ESD branches that are connected one-to-one with the level control circuit, and the multiple ESD branches are connected in parallel with each other. The ESD branch includes a first TVS diode and a second TVS diode. The anode of the first TVS diode is connected to the cathode of the second TVS diode and is connected to the third electrode of the switching device Q1 in the corresponding level control circuit. The anode of the second TVS diode is grounded.
6. The discrete input / output card according to claim 3, characterized in that, The ESD module also includes a main TVS tube connected in parallel with multiple ESD branches; The cathode of the main TVS tube is connected to the cathode of the first TVS tube in each ESD branch, and the anode of the main TVS tube is grounded.
7. The discrete input / output card according to claim 1, characterized in that, The main control module includes an FPGA chip and a CPCI bridge chip. The CPCI bridge chip is connected to the FPGA chip, and the FPGA chip is connected to the driver module.
8. The discrete input / output card according to claim 7, characterized in that, The FPGA chip is model XC7A75T-2FGG484I, and the CPCI bridge chip is model PCI9054.
9. The discrete input / output card according to claim 7, characterized in that, The power conversion module includes a first power conversion chip for supplying power to the FPGA chip; The first power conversion chip is model TPS54821RHLR. The first power conversion chip includes VIN pin, EN pin, PVIN1 pin, PVIN2 pin, BOOT pin, PH1 pin, PH2 pin and V_SNS pin.
10. The discrete input / output card according to claim 9, characterized in that, The PVIN1, PVIN2, and VIN pins are grounded through capacitor C195, and the PVIN1, PVIN2, and VIN pins are also grounded and connected to the input voltage through capacitor C197. The EN pin is connected to the PVIN1 pin, PVIN2 pin, and VIN pin through a resistor R599; The BOOT pin is connected to the PH1 and PH2 pins through capacitor C196. The PH1 and PH2 pins are connected to one end of resistor R600 and the power supply pin of the FPGA chip through inductor L1. The other end of resistor R600 is connected to the V_SNS pin and grounded through resistor R602. The power supply pin of the FPGA chip is grounded through capacitor C198, which is connected in parallel with capacitor C199.