Chip stacking unit, chip stacking structure and chip packaging structure
By connecting the upper and lower chips with a flexible substrate and conductive vias, the problem of uneven HBM chip stacking is solved, the packaging process is simplified, costs are reduced, and chip strength is improved.
Patent Information
- Application Number
- CN202423090192.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-11-14
- Estimated Expiration
- 2034-12-13
AI Technical Summary
In existing high bandwidth memory (HBM) chip stacking processes, the upper and lower layers of chips are prone to uneven stacking, resulting in difficulty in filling and unstable connections.
The chip stacking unit is used to connect the front sides of the upper and lower chips through a flexible substrate. Conductive vias and conductive lines are set on the flexible substrate, and electrical connection is achieved by using conductive blocks or conductive lines, avoiding the deformation problem caused by traditional solder ball welding.
It simplifies the chip packaging process, reduces process costs, improves chip strength, and ensures electrical connection even with misalignment, eliminating the need for chips with through-silicon vias (TSVs).
Smart Images
Figure CN223552527U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of chip packaging, and in particular to a chip stacking unit, a chip stacking structure, and a chip packaging structure. Background Technology
[0002] High-bandwidth memory (HBM) is used for high-speed data transfer between the graphics processing unit (GPU) and the central processing unit (CPU). The uniqueness of HBM lies primarily in its stacking and interconnection. HBM vertically stacks multiple memory modules (DRAM) using advanced packaging technologies such as through-silicon vias (TSV) and micro-bump technology, interconnecting them with the GPU through an interposer layer. This achieves high capacity, high bandwidth, low latency, and low power consumption within a relatively small physical space.
[0003] The existing HBM process uses Mass Reflow Bonding with Molded Underfill (MR-MUF). The specific steps of the MR-MUF process are: (1) the microbumps of the chip are coated with flux and axially bonded and stacked; (2) all the flux of the microbumps is melted at once and pressure is applied, the microbumps shorten axially, and after cooling, the chip and circuit connection is completed; (3) liquid epoxy molding compound (LMC) is used to fill the gaps between the chips or between the substrates, while simultaneously performing insulation and molding. However, the MR-MUF process has problems such as difficulty in filling and uneven stacking of upper and lower layers of chips.
[0004] Therefore, how to improve the unevenness of the stacking of upper and lower chips in the chip stacking process is a problem that needs to be solved. Summary of the Invention
[0005] The technical problem to be solved by this utility model is how to improve the unevenness of the upper and lower layers of chips in the chip stacking process, and to provide a chip stacking unit, a chip stacking structure and a chip packaging structure.
[0006] To address the aforementioned problems, this utility model provides a chip stacking unit, comprising: two stacked chips, each chip having a first surface and a second surface, the first surfaces of the two chips being connected together and the second surfaces of the two chips being disposed opposite to each other; a flexible substrate having a third surface and a fourth surface, the flexible substrate being bent toward the third surface to form an accommodating space, the two chips being located within the accommodating space, the second surfaces of the chips facing the third surface of the flexible substrate; a plurality of chip pads being disposed on the second surface of the chips; a plurality of conductive vias penetrating the flexible substrate being disposed within the flexible substrate, and the conductive vias being disposed corresponding to the chip pads; conductive lines being disposed on the fourth surface of the flexible substrate, the conductive lines extending into the conductive vias and electrically connected to the chip pads; and conductive blocks being disposed within the conductive vias, the conductive blocks being electrically connected to the chip pads.
[0007] In some embodiments, the first surfaces of the two chips are connected by an adhesive.
[0008] In some embodiments, the conductive block is a solder ball.
[0009] In some embodiments, the thickness of the conductive block is the same as the thickness of the flexible substrate.
[0010] In some embodiments, the conductive lines are in direct contact with the chip pads and are electrically connected.
[0011] In some embodiments, the conductive block is an elastic element.
[0012] In some embodiments, the thickness of the conductive block is greater than the thickness of the flexible substrate.
[0013] In some embodiments, the third surface of the flexible substrate has a gap with the second surface of the chip.
[0014] In some embodiments, the conductive lines are electrically connected to the chip pads via the conductive block.
[0015] To address the aforementioned problems, this invention provides a chip stacking structure comprising multiple sequentially stacked chip stacking units. The chip stacking units are constructed using the methods described in this invention, and adjacent chip stacking units are electrically connected via conductive blocks or conductive lines.
[0016] To address the aforementioned problems, this utility model provides a chip packaging structure, comprising: a substrate; a chip stack structure disposed on the surface of the substrate, wherein the chip stack structure adopts the chip stack structure described in this utility model, and the chip stack structure is electrically connected to the substrate through conductive blocks or conductive lines; a top chip disposed on the surface of the chip stack structure, wherein the surface of the top chip in contact with the chip stack structure is provided with a plurality of solder bumps, and the solder bumps are in contact with the conductive blocks; and a molding compound layer located on the surface of the substrate, which covers the chip stack structure and the top chip.
[0017] The above technical solution connects the back sides of two chips and then connects the front sides of the two chips through a bent flexible substrate. Within a chip stacking unit, the first surfaces of the two chips are directly connected, eliminating the need for solder balls and avoiding the problem of uneven chip stacking caused by solder ball deformation during chip soldering in traditional processes. In subsequent stacking and packaging processes, chip stacking units can be directly stacked repeatedly to complete chip packaging, simplifying the packaging process. When repeatedly stacking chip stacking units, conductive blocks are aligned for electrical connection between the upper and lower chip stacking units; in addition, conductive lines are provided on the fourth surface of the flexible substrate to ensure electrical connection even when there are misalignments between the upper and lower chip stacking units. Compared with traditional processes, the chips in the chip stacking unit described in this invention can use ordinary chips, eliminating the need for chips with through-silicon vias (TSVs), saving process costs and improving chip strength.
[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the present invention. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the specific embodiments of this utility model, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0020] Figure 1 This is a schematic diagram of the structure of one embodiment of the chip stacking unit described in this utility model.
[0021] Figure 2 This is a schematic diagram of another embodiment of the chip stacking unit described in this utility model.
[0022] Figure 3 This is a schematic diagram of one embodiment of the chip stacking structure described in this utility model.
[0023] Figure 4 This is a schematic diagram of one embodiment of the chip packaging structure described in this utility model. Detailed Implementation
[0024] The technical solutions in the embodiments of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.
[0025] Please see Figure 1 This is a schematic diagram of the structure of one embodiment of the chip stacking unit described in this utility model. Figure 1 As shown, the chip stacking unit includes two stacked chips 11 and a flexible substrate 12. Each chip 11 has a first surface S1 and a second surface S2. The first surfaces S1 of the two chips 11 are connected, and the second surfaces S2 of the two chips 11 are opposite to each other. The flexible substrate 12 has a third surface S3 and a fourth surface S4. The flexible substrate 12 is bent towards the third surface S3 to form a receiving space 120. The two chips 11 are located within the receiving space 120, with the second surfaces S2 of the chips 11 facing the third surface S3 of the flexible substrate 12. The second surface S2 of the chips 11 is provided with a plurality of chip pads 110. The flexible substrate 12 has a plurality of through-holes 121 penetrating the flexible substrate 12, and the through-holes 121 are correspondingly arranged with the chip pads 110. The fourth surface S4 of the flexible substrate 12 is provided with conductive lines 122, which extend into the conductive through-holes 121 and are electrically connected to the chip pads 110. A conductive block 123 is provided inside the conductive through-hole 121, and the conductive block 123 is electrically connected to the chip pad 110.
[0026] The above technical solution connects the back sides of two chips and then connects the front sides of the two chips through a bent flexible substrate. Within a chip stacking unit, the first surfaces of the two chips are directly connected, eliminating the need for solder balls and avoiding the problem of uneven chip stacking caused by solder ball deformation during chip soldering in traditional processes. In subsequent stacking and packaging processes, chip stacking units can be directly stacked repeatedly to complete chip packaging, simplifying the packaging process. When repeatedly stacking chip stacking units, conductive blocks are aligned for electrical connection between the upper and lower chip stacking units; in addition, conductive lines are provided on the fourth surface of the flexible substrate to ensure electrical connection even when there are misalignments between the upper and lower chip stacking units. Compared with traditional processes, the chips in the chip stacking unit described in this invention can use ordinary chips, eliminating the need for chips with through-silicon vias (TSVs), thus saving process costs.
[0027] In some embodiments, the first surfaces S1 of the two chips 11 are connected by an adhesive 13. The adhesive 13 is used to fix the chips and also acts as a buffer to prevent the chips 11 from colliding and breaking. In addition, by directly connecting the first surfaces S1 of the two chips 11 through the adhesive 13, there is no need to use solder balls, thus avoiding the problem of uneven stacking of upper and lower chips caused by solder ball deformation during chip soldering in traditional processes.
[0028] In some embodiments, the conductive block 123 is a solder ball. Since the solder ball is disposed within the conductive via 121, the fourth surface S4 of the flexible substrate 12 of the upper and lower chip stacking units is in direct contact during subsequent stacking processes. In subsequent soldering processes, the deformation of the solder ball will not cause uneven stacking.
[0029] In other embodiments, the conductive block 123 can also be a commonly used conductive material, which can be set according to actual process requirements.
[0030] In some embodiments, the thickness of the conductive block 123 is the same as the thickness of the flexible substrate 12.
[0031] In some embodiments, the conductive line 122 is in direct contact with the chip pad 110 for electrical connection. In this embodiment, the third surface S3 of the flexible substrate 12 contacts the second surface S2 of the chip 11, and the conductive line 122 extends to the bottom of the conductive via 121 and is in direct contact with the chip pad 110. Simultaneously, the conductive block 123 is disposed within the conductive via 121 to further achieve better conductivity.
[0032] Please see Figure 2 This is a schematic diagram of another embodiment of the chip stacking unit described in this utility model. Figure 2 The illustrated embodiments and Figure 1 The difference in the illustrated embodiment is that the conductive block 223 is an elastic element. The conductive block 223, made of an elastic material, can fully fill the conductive vias 221 in the flexible substrate 22, achieving better electrical connection with the conductive lines 222 and the chip pads 210. Furthermore, in subsequent stacking and packaging processes, the elastic conductive block 223 can also achieve better electrical connection between upper and lower chip stacking units.
[0033] In some embodiments, the thickness of the conductive block 223 is slightly greater than the thickness of the flexible substrate 22. Since the conductive block 223 is an elastic element made of an elastic material, its thickness can be appropriately greater than that of the flexible substrate 22. In subsequent stacking and packaging processes, the conductive block 223 deforms when compressed, enabling better electrical connections between upper and lower chip stacking units, as well as between the conductive lines 222 and the chip pads 210.
[0034] In some embodiments, the third surface S3 of the flexible substrate 22 and the second surface S2 of the chip 21 are spaced apart. This space between the flexible substrate 22 and the chip 21 effectively buffers the pressure generated during chip stacking and packaging, preventing damage to the surface of the chip 21.
[0035] In this embodiment, the conductive line 222 is electrically connected to the chip pad 210 through the conductive block 223. Since there is a gap between the flexible substrate 22 and the chip 21, the conductive line 222 cannot directly contact the chip pad 210. Therefore, a conductive block 223 with a thickness greater than that of the flexible substrate 22 is provided, and the conductive line 222 is electrically connected to the chip pad 210 through the conductive block 223.
[0036] Please see Figure 3 This is a schematic diagram of one embodiment of the chip stacking structure described in this utility model. Figure 3 As shown, the chip stacking structure includes multiple chip stacking units 31 stacked sequentially, and the chip stacking units 31 adopt the present invention. Figure 1 The chip stacking units shown are described above (and will not be repeated here), and two adjacent chip stacking units 31 are electrically connected by conductive blocks 123 or conductive lines 122.
[0037] The above technical solution directly uses the chip stacking unit 31 to repeatedly stack to complete chip packaging, which simplifies the packaging process. When repeatedly stacking the chip stacking unit 31, the conductive block 123 is aligned for electrical connection between the upper and lower layers of the chip stacking unit 31. Furthermore, even if there is an alignment error between the upper and lower layers of the chip stacking unit 31, the conductive line 122 disposed on the fourth surface S4 of the flexible substrate 12 can still ensure an electrical connection between the upper and lower layers of the chip stacking unit 31. Compared to traditional processes, the chip 11 in the chip stacking structure of this invention can use ordinary chips, eliminating the need for chips with through-silicon vias (TSVs), thus saving process costs.
[0038] In other embodiments, the chip stacking unit 31 adopts the present invention. Figure 2 The chip stacking unit shown is described above and will not be repeated here.
[0039] Please see Figure 4 This is a schematic diagram of one embodiment of the chip packaging structure described in this utility model. Figure 4 As shown, the chip packaging structure includes: a substrate 41, a chip stacking structure 42, a top chip 43, and a molding compound 44. The chip stacking structure 42 is disposed on the surface of the substrate 41, and the chip stacking structure 42 adopts the present invention. Figure 3 The chip stack structure shown (see previous description, not repeated here) is electrically connected to the substrate 41 via conductive blocks 122 or conductive lines 123. The top layer chip 43 is disposed on the surface of the chip stack structure 42, and the surface of the top layer chip 43 in contact with the chip stack structure 42 has multiple solder bumps 430, which contact the conductive blocks 123. The molding compound 44 is located on the surface of the substrate 41 and covers the chip stack structure 42 and the top layer chip 43.
[0040] The above technical solution directly uses chip stacking units to repeatedly stack to form a chip stacking structure 42 to complete chip packaging, which simplifies the packaging process. When connecting the chip stacking structure 42 to the substrate 41 or the top chip 43, the conductive block 123 electrically connects to the substrate 41 or the top chip 43. Furthermore, even if there is an alignment error between the chip stacking structure 42 and the substrate 41 or the top chip 43, the conductive line 122 disposed on the fourth surface of the flexible substrate can still ensure an electrical connection between the chip stacking structure 42 and the substrate 41 or the top chip 43. Compared to traditional processes, the chips in the chip stacking structure of this invention can use ordinary chips, eliminating the need for chips with through-silicon vias (TSVs), thus saving process costs.
[0041] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.
[0042] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.
[0043] It should be noted that the terms "comprising" and "having," and their variations, used in this utility model document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this utility model can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this utility model. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.
[0044] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.
Claims
1. A chip stacking unit, characterized in that, include: Two chips are stacked together, each chip having a first surface and a second surface, the first surfaces of the two chips being connected, and the second surfaces of the two chips being disposed opposite to each other; A flexible substrate has a third surface and a fourth surface. The flexible substrate is bent toward the third surface to form a receiving space. Two chips are located in the receiving space, and the second surface of the chips faces the third surface of the flexible substrate. The second surface of the chip is provided with a plurality of chip pads, and the flexible substrate is provided with a plurality of conductive vias penetrating the flexible substrate, and the conductive vias are provided corresponding to the chip pads; the fourth surface of the flexible substrate is provided with conductive lines, the conductive lines extend into the conductive vias and are electrically connected to the chip pads. A conductive block is provided inside the conductive via, and the conductive block is electrically connected to the chip pad.
2. The chip stacking unit according to claim 1, characterized in that, The first surfaces of the two chips are connected by adhesive.
3. The chip stacking unit according to claim 1, characterized in that, The conductive block is a solder ball.
4. The chip stacking unit according to claim 1, characterized in that, The thickness of the conductive block is the same as the thickness of the flexible substrate.
5. The chip stacking unit according to claim 1, characterized in that, The conductive line is in direct contact with the chip pad and electrically connected.
6. The chip stacking unit according to claim 1, characterized in that, The conductive block is an elastic element.
7. The chip stacking unit according to claim 6, characterized in that, The thickness of the conductive block is greater than the thickness of the flexible substrate.
8. The chip stacking unit according to claim 7, characterized in that, The third surface of the flexible substrate has a gap with the second surface of the chip.
9. The chip stacking unit according to claim 8, characterized in that, The conductive lines are electrically connected to the chip pads via the conductive block.
10. A chip stacking structure, characterized in that, It includes multiple chip stacking units stacked sequentially, wherein the chip stacking units are as described in any one of claims 1 to 9, and adjacent chip stacking units are electrically connected by conductive blocks or conductive lines.
11. A chip packaging structure, characterized in that, include: Base; A chip stacking structure is disposed on the surface of the substrate, the chip stacking structure adopts the chip stacking structure as described in claim 10, and the chip stacking structure is electrically connected to the substrate through conductive blocks or conductive lines; A top-layer chip is disposed on the surface of the chip stack structure. The surface of the top-layer chip that contacts the chip stack structure is provided with multiple solder bumps, and the solder bumps are in contact with the conductive blocks. A molding layer is located on the surface of the substrate and covers the chip stack structure and the top chip.