Light emitting diode

Abstract

The utility model relates to the technical field of semiconductors, and discloses a light-emitting diode, which comprises a substrate, and an N-type GAN layer, a quantum well layer, a P-type GAN layer and a metal reflecting layer which are sequentially laminated on the substrate, the metal reflecting layer is provided with a first groove extending to the middle of the N-type GAN layer and a second groove extending to the P-type GAN layer, and the first groove and the second groove are communicated with each other. The first electrode is located in the first groove and electrically connected with the N-type GAN layer, and the second electrode is located in the second groove and electrically connected with the P-type GAN layer; a first insulating layer and a second insulating layer are sequentially arranged on the metal reflecting layer; wherein the N-type GAN layer is provided with an ISO platform, the ISO platform is provided with a flat surface, the distance between the surface of the ISO platform and the substrate is recorded as L, the height of the pattern on the substrate is recorded as h, and L is greater than h. The device is low in cost and high in productivity, and the reliability is greatly improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a light-emitting diode. Background Technology

[0002] In existing technologies, there are two structures for the inter-die channel position in light-emitting diodes, such as... Figure 1-2 As shown. Figure 1 For channel positions without ISO etching: In this structure, because there are insulating materials such as GaN, CBL, DBR, Al2O3, and Si3N4 in the scribe line, the insulating layer may break during scribe, affecting the appearance yield; at the same time, since there is no insulating layer to protect the chip side, it may fail due to moisture or conductive impurities during application, resulting in insufficient chip reliability. Figure 2 The diagram shows the die cutting of the ISO over-etched LED, illustrating the channel location structure. Figure 3 This structure is costly and inefficient. Furthermore, due to excessive etching, the pattern on the substrate is exposed, forming an uneven surface. This makes it easy for the thick insulating layer stacked on these uneven surfaces to chip during chip cutting, thereby reducing the effectiveness of insulation protection and causing chip leakage. Utility Model Content

[0003] Purpose of the utility model: To address the problems existing in the prior art, this utility model provides a light-emitting diode that is low in cost, has high production capacity, and significantly improves reliability.

[0004] Technical Solution: This utility model provides a light-emitting diode, comprising: a substrate, an N-type GAN layer, a quantum well layer, a P-type GAN layer, and a metal reflective layer sequentially stacked on the substrate. The metal reflective layer has a first groove extending to the middle of the N-type GAN layer and a second groove extending to the P-type GAN layer. A first electrode is located in the first groove and electrically connected to the N-type GAN layer, and a second electrode is located in the second groove and electrically connected to the P-type GAN layer. A first insulating layer is provided on the metal reflective layer and on the sidewalls of the first and second grooves. A second insulating layer is provided on the first insulating layer. The N-type GAN layer has an etched ISO platform that completely covers the pattern on the substrate and has a flat surface. Let L be the distance from the surface of the ISO platform to the substrate, and h be the height of the pattern on the substrate; then L > h. The ISO platform is the die-cutting position, and its flat surface prevents chipping of the insulating layer during die cutting.

[0005] Further, it further includes a DBR layer, the DBR layer is disposed between the metal reflection layer and the first insulating layer, the DBR layer exposes the N-type GAN layer through the first groove and exposes the P-type GAN layer through the second groove;

[0006] Alternatively, it further includes a DBR layer, the DBR layer is disposed between the metal reflection layer and the N-type GAN layer, the DBR layer exposes the N-type GAN layer through the first groove and exposes the P-type GAN layer through the second groove.

[0007] Further, the distance △h = L - h from the surface of the ISO platform to the pattern on the substrate is less than 1.0 μm.

[0008] Further, a third insulating layer is disposed on the second insulating layer, and the third insulating layer has a first through hole exposing the first electrode and a second through hole exposing the second electrode; a third electrode is electrically connected to the first electrode through the first through hole, and a fourth electrode is electrically connected to the second electrode through the second through hole.

[0009] Further, let the coverage area of the DBR layer on the ISO platform be a, the coverage area of the first insulating layer on the ISO platform be b, and the coverage area of the third insulating layer on the ISO platform be c, then a < b < c. Setting a < b < c, if the third insulating layer covered on the grain cutting position of the ISO platform is not etched, during grain cutting, even if chipping occurs due to the third insulating layer, it does not affect the protection effect of the DBR layer, the first insulating layer, and the second insulating layer on the chip.

[0010] Preferably, the third insulating layer is a single-layer or multi-layer composite structure including an ALD layer. ALD can achieve preferential reflection of large-angle light, avoid weak reflection of large angles by the DBR and reduce absorption of large-angle light, thereby improving the light extraction efficiency.

[0011] Further, the thickness of the P-type GAN layer is 2 - 4 μm; the thickness of the N-type GAN layer is 1 - 2 μm.

[0012] Beneficial effects: Compared with the prior art, the present utility model sets the ISO platform, so that no insulating layer chipping problem occurs during grain cutting. The present utility model has low cost, high reliability, and while the production capacity is improved, the yield of the AOI appearance is improved in multiple models compared with the ISO unetched appearance, and is equivalent to or slightly superior to the yield of the ISO full etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a channel position structure diagram without ISO etching;

[0014] Figure 2 This is a diagram showing the location and structure of the ISO-etched trench.

[0015] Figure 3 A schematic diagram of die cutting for ISO over-etched light-emitting diodes:

[0016] Figure 4 This is a schematic diagram of the structure of the light-emitting diode in Implementation Method 1;

[0017] Figure 5 This is a schematic diagram of the die cutting of the light-emitting diode in Embodiment 1;

[0018] Figure 6 This is a schematic diagram of the structure of the light-emitting diode in Embodiment 2;

[0019] Figure 7 The images show a comparison of the appearance of the LED in Embodiment 1 and the ISO over-etched LED; where (a) is a schematic diagram of the appearance of the ISO over-etched LED, (b) is a schematic diagram of the appearance of the ISO over-etched LED OM, (c) is a schematic diagram of the appearance of the ISO over-etched LED FIB, (d) is a schematic diagram of the appearance of the LED in Embodiment 1, (e) is a schematic diagram of the appearance of the LED OM in Embodiment 1, and (f) is a schematic diagram of the appearance of the LED FIB in Embodiment 1.

[0020] Illustration: 101, Substrate; 102, Pattern; 201, N-type GAN layer; 301, Quantum well layer; 401, P-type GAN layer; 501, Metal reflective layer; 601, DBR layer; 701, First electrode; 702, Second electrode; 703, Third electrode; 704, Fourth electrode; 801, First insulating layer; 802, Second insulating layer; 803, Third insulating layer; 901, ISO platform. Detailed Implementation

[0021] The following detailed description of exemplary embodiments of the present invention, with reference to illustrations, is intended to enable those skilled in the art to fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. Throughout this specification, some identical symbols denote elements having the same or similar structure, function, or principle, which can be deduced by those skilled in the art from the teachings of this specification. For the sake of brevity, elements with the same symbols will not be repeated.

[0022] Implementation method 1:

[0023] This embodiment provides a light-emitting diode, the specific structure of which is as follows: Figure 4The structure includes a substrate 101, an N-type GaN layer 201, a quantum well layer 301, a P-type GaN layer 401, and a metal reflective layer 501 sequentially stacked on the substrate. The thickness of the P-type GaN layer 401 is 2-4 μm, and the thickness of the N-type GaN layer 201 is 1-2 μm. The metal reflective layer 501 has a first groove exposing the N-type GaN layer 201 and a second groove exposing the P-type GaN layer 401. A DBR layer 601 is disposed on the metal reflective layer 501, covering the surface of the metal reflective layer 501 and the N-type GaN layer 201. The surface of the P-type GAN layer 201, the sidewalls of the quantum well layer 301, the surface of the P-type GAN layer 401, and the sidewalls of the first and second grooves are included. The metal reflective layer 501 is completely enclosed by the DBR layer 601 and is not electrically connected to the light-emitting diode. A first insulating layer 801, a second insulating layer 802, and a third insulating layer 803 are sequentially disposed on the DBR layer 601. A first electrode 701 and a second electrode 702 are provided between the second insulating layer 802 and the third insulating layer 803, and on the second insulating layer 802. The first electrode 701 is located in the first groove. The second electrode 702 is located in the second groove and electrically connected to the N-type GAN layer 201; the third insulating layer 803 has a first through hole and a second through hole, the third electrode 703 is located in the first through hole and electrically connected to the first electrode 701, and the fourth electrode 704 is located in the second through hole and electrically connected to the second electrode 702; on the N-type GAN layer 201, on both sides of its sidewalls, there are ISO platforms 901 formed by ISO etching, which imprint the pattern 102 on the substrate 101. The surface is completely covered and has a flat surface; let L be the distance from the surface of ISO platform 901 to substrate 101, and h be the height of pattern 102 on substrate 101, then L > h; let Δh be the distance from the surface of ISO platform 901 to pattern 102 on substrate 101, and Δh = Lh < 1.0 μm; let a be the coverage area of ​​DBR layer 601 on ISO platform 901, b be the coverage area of ​​first insulating layer 801 on ISO platform 901, and c be the coverage area of ​​third insulating layer 803 on ISO platform 901, then a <b<c;

[0024] Optionally, the substrate is preferably a sapphire substrate. The pattern 102 on the substrate 101 is a pattern formed on the sapphire substrate body with the same material and an integral structure, which is commonly referred to as a PSS substrate. Generally, the PSS pattern is formed by coating photoresist on the sapphire substrate, and after exposure and development, dry or wet etching is used. After removing the remaining photoresist, the patterned substrate, i.e., the PSS substrate, is obtained.

[0025] Optionally, the pattern 102 on the substrate 101 can be a conical structure, or a frustum, cylinder, pyramid, or other similar structure. It should be noted that... Figure 4The pattern on the substrate is for illustrative purposes only. The actual shape may vary depending on the substrate material and the etching process conditions of dry etching, such as the volume ratio and flow ratio of etching gases, as well as the etching time and etching power. It can also be set during fabrication according to actual needs (such as the luminous efficiency of the device) or the bottom width, diameter, height and spacing of the structure can be adjusted as needed. No restrictions are imposed here.

[0026] Optionally, the metal reflective layer 501 is a highly reflective metal layer containing Ag or Al. The metal reflective layer 501 has a reflectivity of >85% at all angles in the visible light range. It can preferentially reflect large-angle light, avoid the weak reflection of DBR at large angles and reduce the absorption of large-angle light, thereby improving the light output efficiency.

[0027] Optionally, the third insulating layer 803 is a single-layer or multi-layer composite structure containing an ALD layer. That is, the third insulating layer 803 can be made of ALD (Al2O3) or a variety of insulating materials including ALD during fabrication, which can encapsulate the chip to enhance its lateral insulation capability. At the ISO platform, the insulating layer can be exposed by dry etching or wet etching, or the insulating layer at the ISO platform can be left unprocessed.

[0028] The specific fabrication method of the light-emitting diode in this embodiment is as follows:

[0029] Photoresist is coated on a sapphire substrate, and after exposure and development, a PSS pattern is formed by dry or wet etching. After removing the remaining photoresist, a patterned substrate is obtained.

[0030] GaN-based semiconductor layers, including N-type GaN layers, quantum well layers, P-type GaN layers, and metal conductive layers, are grown on patterned substrates using metal-organic chemical deposition (MOCVD).

[0031] The epitaxial layer is etched to form a mesa platform and a first groove and a second groove;

[0032] The DBR layer, the first insulating layer, the second insulating layer, the first motor, the second electrode, and the third insulating layer are deposited sequentially.

[0033] The third insulating layer is etched to form the first and second through holes;

[0034] Deposit the third and fourth electrodes;

[0035] ISO etching is performed on the cleavage path to form an ISO plateau. After the chip undergoes the cleavage process, the chip is separated at the ISO plateau.

[0036] Implementation Method 2:

[0037] This embodiment is largely the same as embodiment 1, except that, as Figure 5 As shown, in this embodiment, the DBR layer 601 is located between the metal reflective layer 501 and the N-type GAN layer 201. The DBR layer 601 covers the surface of the N-type GAN layer 201, the sidewall of the quantum well layer 301, the surface of the P-type GAN layer 401, and the sidewalls of the first and second grooves. The metal reflective layer 501 is completely wrapped by the first insulating layer 801 and is not electrically connected to the light-emitting diode.

[0038] Apart from the above, this implementation method is exactly the same as implementation method 1, and will not be described again here.

[0039] Performance Analysis:

[0040] Performance analysis and comparison were performed on three chips: Implementation Method 1, no ISO etching, and excessive ISO etching.

[0041] Implementation method 1 reduces the time by more than 40% compared to the ISO over-etching single process step; Implementation method 1 reduces the cost by more than 30% compared to the ISO over-etching single process; Implementation method 1 increases the total chip cost by less than 1% compared to no ISO etching.

[0042] Implementation Method 1: The AOI appearance yields without ISO etching and with excessive ISO etching are shown in Table 1.

[0043]

[0044] The above embodiments are only for illustrating the technical concept and features of this utility model, and are intended to enable those skilled in the art to understand the content of this utility model and implement it accordingly. They should not be construed as limiting the scope of protection of this utility model. All equivalent transformations or modifications made in accordance with the spirit and essence of this utility model should be included within the scope of protection of this utility model.

Claims

1. A light-emitting diode, characterized in that, include: The system comprises a substrate, an N-type GAN layer, a quantum well layer, a P-type GAN layer, and a metal reflective layer sequentially stacked on the substrate. The metal reflective layer has a first groove extending to the middle of the N-type GAN layer and a second groove extending to the P-type GAN layer. A first electrode is located in the first groove and electrically connected to the N-type GAN layer, and a second electrode is located in the second groove and electrically connected to the P-type GAN layer. A first insulating layer is provided on the metal reflective layer and on the sidewalls of the first and second grooves. A second insulating layer is provided on the first insulating layer. The N-type GAN layer has an etched ISO platform, the distance from the surface of the ISO platform to the substrate is L, and the height of the pattern on the substrate is h, where L > h.

2. The light-emitting diode according to claim 1, characterized in that: It also includes a DBR layer, which is disposed between the metal reflective layer and the first insulating layer. The DBR layer exposes the N-type GAN layer through the first groove and exposes the P-type GAN layer through the second groove. Alternatively, it may also include a DBR layer disposed between the metal reflective layer and the N-type GAN layer, wherein the DBR layer exposes the N-type GAN layer through the first groove and exposes the P-type GAN layer through the second groove.

3. The light-emitting diode according to claim 1, characterized in that: The distance Δh = Lh < 1.0 μm from the surface of the ISO platform to the pattern on the substrate.

4. The light-emitting diode according to claim 2, characterized in that: A third insulating layer is disposed on the second insulating layer, the third insulating layer having a first through hole exposing the first electrode and a second through hole exposing the second electrode; the third electrode is electrically connected to the first electrode through the first through hole, and the fourth electrode is electrically connected to the second electrode through the second through hole.

5. The light-emitting diode according to claim 4, characterized in that: Let a be the coverage area of ​​the DBR layer on the ISO platform, b be the coverage area of ​​the first insulating layer on the ISO platform, and c be the coverage area of ​​the third insulating layer on the ISO platform. Then a <b<c。 6. The light-emitting diode according to claim 1, characterized in that: The third insulating layer is a single-layer or multi-layer composite structure containing an ALD layer.

7. The light-emitting diode according to claim 1, characterized in that: The thickness of the P-type GAN layer is 2-4 μm; the thickness of the N-type GAN layer is 1-2 μm.

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