Single-phase full-bridge three-level PWM (Pulse Width Modulation) generation device capable of bidirectionally flowing energy

Abstract

The utility model aims to provide the single-phase full-bridge three-level PWM generating device which can effectively reduce PWM channel resource consumption of the MCU and is safe and reliable. The circuit comprises a first logic chip (U1) and a second logic chip (U2). Pins 1, 2, 4, 5, 9, 10, 12 and 13 of the first logic chip are connected with input PWM signals, pins 3 and 11 of the first logic chip are connected with the second logic chip and serve as outputs at the same time, and pins 6 and 8 of the first logic chip are connected with pins 5 and 9 of the second logic chip; pins 1, 2, 12 and 13 of the second logic chip are connected with input PWM signals, pins 4 and 10 of the second logic chip are connected with pins 11 and 3 of the first logic chip and serve as output pins at the same time, and pins 3, 6, 8 and 11 of the second logic chip serve as output pins. The power electronic PWM signal modulation circuit can be applied to the technical field of power electronic PWM signal modulation.

Description

TECHNICAL FIELD

[0001] The utility model relates to power electronic PWM signal modulation technical field especially relates to a kind of energy two-way flow's single-phase full-bridge three-level PWM generation device. BACKGROUND

[0002] The generation method of the single-phase full-bridge three-level PWM signal of current routine, generally by external FPGA or CPLD generation, this mode is needed for the PWM signal of single-phase full-bridge three-level, it also needs to build the peripheral circuit and control program of FPGA or CPLD, this way leads to system cost and complexity will substantially increase. UTILITY MODEL CONTENTS

[0003] The utility model solves the technical problem that the prior art is overcome, provide a kind of energy two-way flow's single-phase full-bridge three-level PWM generation device that can effectively reduce the PWM channel resource consumption of MCU and safe and reliable.

[0004] The technical scheme adopted by the utility model is a kind of energy two-way flow's single-phase full-bridge three-level PWM generation device, the device is built on single-phase full-bridge three-level ANPC topology, the device includes first logic chip and second logic chip, the first logic chip and the second logic chip are commonly composed of PWM signal modulation conversion circuit;

[0005] The 1,2,4,5,9,10,12,13 pins of the first logic chip are connected with input PWM signal, the 3,11 pins of the first logic chip are connected with second logic chip and simultaneously as output, the 6,8 pins of the first logic chip are connected with the 5,9 pins of second logic chip, the 7,14 pins of the first logic chip are power supply pins;

[0006] The 1,2,12,13 pins of the second logic chip are connected with input PWM signal, the 4,10 pins of the second logic chip are connected with the 11,3 pins of first logic chip and simultaneously as output pin, the 3,6,8,11 pins of the second logic chip are as output pin, the 7,14 pins of the second logic chip are power supply pins.

[0007] The single-phase full-bridge three-level ANPC topology comprises a first capacitor, a second capacitor and a third capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a ninth switch tube, a tenth switch tube, an eleventh switch tube, a twelfth switch tube and an inductor, the first capacitor and the second capacitor are connected in series and between a positive electrode and a negative electrode, the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are connected in series and between the positive electrode and the negative electrode, the seventh switch tube, the eighth switch tube, the ninth switch tube and the tenth switch tube are connected in series and between the positive electrode and the negative electrode, the fifth switch tube and the sixth switch tube are connected in series, the drain electrode of the fifth switch tube is connected to the connection point of the first switch tube and the second switch tube, the source electrode of the sixth switch tube is connected to the connection point of the third switch tube and the fourth switch tube, the eleventh switch tube and the twelfth switch tube are connected in series, the drain electrode of the eleventh switch tube is connected to the connection point of the seventh switch tube and the eighth switch tube, and the source electrode of the twelfth switch tube is connected to the connection point of the ninth switch tube and the tenth switch tube, the third capacitor and the inductor are connected in series and the two ends are respectively connected to the series connection point of the fifth switch tube and the sixth switch tube and the series connection point of the eleventh switch tube and the twelfth switch tube.

[0008] The output signals S1A, S4A of the first logic chip and the output signals S1A, S2A, S3A, S4A, S5A, S6A of the second logic chip control the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube and the sixth switch tube, and simultaneously control the tenth switch tube, the ninth switch tube, the eighth switch tube, the seventh switch tube, the twelfth switch tube and the eleventh switch tube.

[0009] The first logic chip and the second logic chip jointly constitute a PWM signal modulation conversion circuit, 4-way PWM signals are converted into 12-way PWM signals, the consumption of PWM channel resources of the MCU is reduced, the problem of the shortage of PWM channel resources is effectively solved, the device requires fewer circuit elements and uses conventional logic devices, the system cost and complexity are reduced, electromagnetic interference is relatively less, noise pollution is also reduced, and the safety is higher. BRIEF DESCRIPTION OF DRAWINGS

[0010] Fig. 1 is a simple structure diagram of the single-phase full-bridge three-level ANPC topology;

[0011] Fig. 2 is a simple circuit principle diagram of the first logic chip;

[0012] Fig. 3 This is a simplified circuit schematic of the second logic chip;

[0013] Fig. 4 This is a waveform diagram of the modulation signal and timing corresponding to each of the aforementioned switching transistors. Detailed Implementation

[0014] like Figs. 1-4 As shown, this invention is built on a single-phase full-bridge three-level ANPC topology. The device includes a first logic chip U1 and a second logic chip U2, which together form a PWM signal modulation and conversion circuit. In this embodiment, the first logic chip U1 is selected from a TI (74LVC08) chip. The second logic chip U2 is selected from a TI (74LVC32) chip.

[0015] Pins 1, 2, 4, 5, 9, 10, 12, and 13 of the first logic chip U1 are connected to the input PWM signal. Pins 3 and 11 of the first logic chip U1 are connected to the second logic chip U2 and also serve as outputs. Pins 6 and 8 of the first logic chip U1 are connected to pins 5 and 9 of the second logic chip U2. Pins 7 and 14 of the first logic chip U1 are power supply pins.

[0016] Pins 1, 2, 12, and 13 of the second logic chip U2 are connected to the input PWM signal. Pins 4 and 10 of the second logic chip U2 are connected to pins 11 and 3 of the first logic chip U1 and also serve as output pins. Pins 3, 6, 8, and 11 of the second logic chip U2 serve as output pins. Pins 7 and 14 of the second logic chip U2 are power supply pins.

[0017] The single-phase full-bridge three-level ANPC topology comprises a first capacitor C1, a second capacitor C2, and a third capacitor C3, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5, a sixth switch tube Q6, a seventh switch tube Q7, an eighth switch tube Q8, a ninth switch tube Q9, a tenth switch tube Q10, an eleventh switch tube Q11, a twelfth switch tube Q12, and an inductor L. The first capacitor C1 and the second capacitor C2 are used as voltage dividing capacitors, and the third capacitor C3 functions with the inductor L to form an LC filter circuit. The first capacitor C1 and the second capacitor C2 are connected in series between the positive electrode V+ and the negative electrode V-, the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, and the fourth switch tube Q4 are connected in series between the positive electrode V+ and the negative electrode V-, the seventh switch tube Q7, the eighth switch tube Q8, the ninth switch tube Q9, and the tenth switch tube Q10 are connected in series between the positive electrode V+ and the negative electrode V-, the fifth switch tube Q5 and the sixth switch tube Q6 are connected in series, the drain electrode of the fifth switch tube Q5 is connected to the connection point of the first switch tube Q1 and the second switch tube Q2, the source electrode of the sixth switch tube Q6 is connected to the connection point of the third switch tube Q3 and the fourth switch tube Q4, the eleventh switch tube Q11 and the twelfth switch tube Q12 are connected in series, the drain electrode of the eleventh switch tube Q11 is connected to the connection point of the seventh switch tube Q7 and the eighth switch tube Q8, the source electrode of the twelfth switch tube Q12 is connected to the connection point of the ninth switch tube Q9 and the tenth switch tube Q10, and the third capacitor C3 and the inductor L are connected in series, with the two ends of the series connection being connected to the series connection point of the fifth switch tube Q5 and the sixth switch tube Q6 and the series connection point of the eleventh switch tube Q11 and the twelfth switch tube Q12, respectively.

[0018] The output signals S1A, S4A of the first logic chip U1 and the output signals S1A, S2A, S3A, S4A, S5A, S6A of the second logic chip U2 control the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the fourth switch tube Q4, the fifth switch tube Q5, and the sixth switch tube Q6, and simultaneously control the tenth switch tube Q10, the ninth switch tube Q9, the eighth switch tube Q8, the seventh switch tube Q7, the twelfth switch tube Q12, and the eleventh switch tube Q11.

[0019] The circuit composed of the first switch tube Q1, the second switch tube Q2, the fifth switch tube Q5, the ninth switch tube Q9, the tenth switch tube Q10 and the twelfth switch tube Q12 is in the active state in the positive half cycle, and the circuit composed of the third switch tube Q3, the fourth switch tube Q4, the sixth switch tube Q6, the seventh switch tube Q7, the eighth switch tube Q8 and the eleventh switch tube Q11 is in the active state in the negative half cycle. The fifth switch tube Q5 and the sixth switch tube Q6 and the eleventh switch tube Q11 and the twelfth switch tube Q12 are slow switches, and the inductor L is connected to the first switch tube Q1, the second switch tube Q2, the ninth switch tube Q9 and the tenth switch tube Q10 or the third switch tube Q3, the fourth switch tube Q4, the seventh switch tube Q7 and the eighth switch tube Q8 in the positive half cycle and the negative half cycle respectively. Each high-frequency switch tube operates as a synchronous buck converter in the corresponding half cycle. In the working condition in the positive half cycle, the fifth switch tube Q5 and the twelfth switch tube Q12 are kept in the open state in the whole half cycle. When the first switch tube Q1 and the fourth switch tube Q4 are opened, the circuit is in the active mode, and the current from V+ to the inductor L is established, and since the first switch tube Q1, the fifth switch tube Q5, the fourth switch tube Q4 and the twelfth switch tube Q12 are all connected, the switching node of the inductor L is connected to V+. At this time, the sixth switch tube Q6, the fourth switch tube Q4, the seventh switch tube Q7 and the eleventh switch tube Q11 must bear the full bus voltage together. In order to avoid uneven distribution of the bus voltage among these devices (due to device parasitic unevenness), the third switch tube Q3 and the eighth switch tube Q8 are also kept open, so that the center node is connected to the neutral point, and the voltage is evenly distributed between the sixth switch tube Q6 and the fourth switch tube Q4, and the voltage is evenly distributed between the seventh switch tube Q7 and the eleventh switch tube Q11, and when the first switch tube Q1, the third switch tube Q3, the eighth switch tube Q8 and the tenth switch tube Q10 are simultaneously closed in the dead time of this state, the current of the inductor L can only flow through the body diode (kept open) of the second switch tube Q2, the fifth switch tube Q5, the ninth switch tube Q9 and the twelfth switch tube Q12. In the freewheeling mode, the second switch tube Q2 and the ninth switch tube Q9 act as synchronous diodes, and the switching node of the inductor L is connected to the neutral point. There is only half of the bus voltage between the sixth switch tube Q6 and the fourth switch tube Q4, and there is only half of the bus voltage between the seventh switch tube Q7 and the eleventh switch tube Q11, so the third switch tube Q3 and the eighth switch tube Q8 do not need to be kept on to achieve voltage balance.

[0020] In addition, the operation in the negative half cycle is similar to the operation in the positive half cycle. The sixth switch Q6 and the eleventh switch Q11 remain on for the entire duration of the negative half cycle. The inductor L is connected to V- through the fourth switch Q4, the sixth switch Q6, the seventh switch Q7, the eleventh switch Q11 in the mode of operation, similar to the operation in the positive half cycle. The second switch Q2 and the ninth switch Q9 also remain on in this mode of operation to balance the voltage stress between the first switch Q1 and the fifth switch Q5, and between the tenth switch Q10 and the twelfth switch Q12. In the freewheeling mode, the inductor L current is maintained through the third switch Q3, the sixth switch Q6, the eighth switch Q8, the eleventh switch Q11 to connect the inductor L switching node to the neutral point.

[0021] The utility model discloses a design is reasonable, and the unique structure reduces the PWM channel resource consumption of MCU, effectively solve the problem of the PWM channel resource shortage, and the utility model discloses a device required circuit element is less, and uses conventional logic device, and electromagnetic interference is relatively less, reduces the noise pollution, has higher security.

[0022] Finally, it needs to be emphasized that the above-mentioned is only the preferred embodiment of the utility model, and does not limit the utility model, for the person skilled in the art, the utility model can have various changes and changes, any modification, equivalent replacement, improvement etc. that is done within the spirit and principle of the utility model should be included in the protection scope of the utility model.

Claims

1. A single-phase full-bridge three-level PWM generation device capable of bidirectional energy flow, which is built on a single-phase full-bridge three-level ANPC topology, characterized in that, The device comprises a first logic chip (U1) and a second logic chip (U2), the first logic chip (U1) and the second logic chip (U2) jointly constitute a PWM signal modulation conversion circuit; The 1, 2, 4, 5, 9, 10, 12, 13 pins of the first logic chip (U1) are connected with an input PWM signal, the 3, 11 pins of the first logic chip (U1) are connected with the second logic chip (U2) and simultaneously serve as outputs, the 6, 8 pins of the first logic chip (U1) are connected with the 5, 9 pins of the second logic chip (U2), and the 7, 14 pins of the first logic chip (U1) are power supply pins; The 1, 2, 12, 13 pins of the second logic chip (U2) are connected with an input PWM signal, the 4, 10 pins of the second logic chip (U2) are connected with the 11, 3 pins of the first logic chip (U1) and simultaneously serve as output pins, the 3, 6, 8, 11 pins of the second logic chip (U2) serve as output pins, and the 7, 14 pins of the second logic chip (U2) are power supply pins.

2. The single-phase full-bridge three-level PWM generation device of claim 1, wherein: The single-phase full-bridge three-level ANPC topology comprises a first capacitor (C1), a second capacitor (C2), and a third capacitor (C3), a first switch tube (Q1), a second switch tube (Q2), a third switch tube (Q3), a fourth switch tube (Q4), a fifth switch tube (Q5), a sixth switch tube (Q6), a seventh switch tube (Q7), an eighth switch tube (Q8), a ninth switch tube (Q9), a tenth switch tube (Q10), an eleventh switch tube (Q11), a twelfth switch tube (Q12), and an inductor (L), the first capacitor (C1) and the second capacitor (C2) are connected in series between the positive electrode (V+) and the negative electrode (V-), the first switch tube (Q1), the second switch tube (Q2), the third switch tube (Q3), and the fourth switch tube (Q4) are connected in series between the positive electrode (V+) and the negative electrode (V-), the seventh switch tube (Q7), the eighth switch tube (Q8), the ninth switch tube (Q9), and the tenth switch tube (Q10) are connected in series between the positive electrode (V+) and the negative electrode (V-), the fifth switch tube (Q5) and the sixth switch tube (Q6) are connected in series, the drain electrode of the fifth switch tube (Q5) is connected to the connection point of the first switch tube (Q1) and the second switch tube (Q2), the source electrode of the sixth switch tube (Q6) is connected to the connection point of the third switch tube (Q3) and the fourth switch tube (Q4), the eleventh switch tube (Q11) and the twelfth switch tube (Q12) are connected in series, the drain electrode of the eleventh switch tube (Q11) is connected to the connection point of the seventh switch tube (Q7) and the eighth switch tube (Q8), the source electrode of the twelfth switch tube (Q12) is connected to the connection point of the ninth switch tube (Q9) and the tenth switch tube (Q10), the third capacitor (C3) and the inductor (L) are connected in series, and the series connection point of the fifth switch tube (Q5) and the sixth switch tube (Q6) and the series connection point of the eleventh switch tube (Q11) and the twelfth switch tube (Q12) are respectively connected to the positive electrode (V+) and the negative electrode (V-); The output signals S1A, S4A of the first logic chip (U1) and the output signals S1A, S2A, S3A, S4A, S5A, S6A of the second logic chip (U2) control the first switch tube (Q1), the second switch tube (Q2), the third switch tube (Q3), the fourth switch tube (Q4), the fifth switch tube (Q5), and the sixth switch tube (Q6), and simultaneously control the tenth switch tube (Q10), the ninth switch tube (Q9), the eighth switch tube (Q8), the seventh switch tube (Q7), the twelfth switch tube (Q12), and the eleventh switch tube (Q11).

Images