High-voltage MOS array module and test circuit thereof

Abstract

The utility model discloses a high-voltage MOS array module and a test circuit thereof, and belongs to the technical field of hybrid integrated circuit testing. The high-voltage MOS array module comprises two or more than two high-voltage MOS array unit modules and corresponding load modules, each high-voltage MOS device control circuit is in one-to-one correspondence with the damping protection circuit, and each high-voltage MOS device control circuit with the damping protection circuit is independent. The test circuit comprises a high-voltage PMOS array module source-drain reverse bias test circuit, a high-voltage PMOS array module gate-source reverse bias test circuit and a high-voltage PMOS array module power aging test circuit. The problem that an existing MOS tube reliability test system is not suitable for a multi-channel high-voltage MOS array reliability test is solved, and the defect of power aging of high-voltage driving module products is overcome. The switch driving module is widely applied to the technical field of high-voltage signal controlled switch driving modules.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of mixed integrated circuit test, further relates to the high pressure MOS driver test technical field, specifically, relates to a kind of high pressure MOS array module and its test circuit. BACKGROUND

[0002] High pressure MOS driver is used for low-loss high-power switching device, with high power density, high reliability, conversion efficiency etc.Characteristics.Especially MOS tube array chip has the characteristics of high-density integration, high performance and low loss, is widely used in various electronic equipment.MOS tube as a kind of field effect transistor based on metal oxide semiconductor material, by applying voltage on gate, the current flow between drain and source can be controlled, with highly controllable.In MOS tube array chip, each MOS tube can work independently, by controlling gate voltage, different functions can be realized.The existing MOS tube reliability test system can only be used for single-channel MOS tube test, and is not compatible with multi-channel MOS tube array chip test.In view of this, the utility model is proposed. SUMMARY

[0003] The technical problem to be solved by the utility model is: solve the problem that the existing MOS tube reliability test system is not suitable for multi-channel high pressure MOS array reliability test, realize the deficiency of high voltage drive class module product power aging.

[0004] Therefore, the utility model provides a kind of high pressure MOS array module, as shown in Figures 1-4 Including two or more high pressure MOS array unit module and corresponding load module.

[0005] The high pressure MOS array unit module includes high pressure MOS device control circuit, damping protection circuit, and the damping protection circuit is reversely connected in parallel with the positive power supply and the output end (i.e. source end and drain end) of the high pressure MOS device control circuit, the output end of each unit module is connected with one end of load module, and the other end of load module is connected with negative power supply end (or ground end).

[0006] The high pressure MOS device control circuit and the damping protection circuit of each channel correspond one by one, and the high pressure MOS device control circuit of each channel with damping protection circuit is independent.

[0007] The reliability test circuit of a kind of high pressure MOS array module, as shown in Figures 5-7

[0008] Source-drain reverse bias test circuit: gate level is connected with source short circuit, and the corresponding port of source-drain reverse bias test voltage is connected between source end and drain end, and source-drain reverse bias test voltage is applied.

[0009] ​Gate-source reverse bias test circuit: the drain and the source are short-circuited, and a gate-source reverse bias test voltage is applied between the source end and the gate end.

[0010] Power aging test circuit: the output end of the unit module is connected with one end of the load module, the other end of the load module is connected with the negative power supply end (or the ground end), the output voltage end of the bias voltage circuit is connected with the gate end, a bias voltage is applied, and a power aging working voltage is applied between the positive power supply end and the negative power supply end (or the ground end).

[0011] The reliability test scheme has the beneficial effects that:

[0012] The three aging circuits: the gate-source aging circuit, the source-drain aging circuit and the array high-temperature power aging circuit. In addition to the source-drain and gate-drain of the MOS device in the high-voltage MOS device control circuit, the damping protection circuit as protection is also tested, and the reliability screening rate of the high-voltage MOS array module is effectively improved.

[0013] In the high-temperature power aging, the saturation voltage drop of the MOS device in the high-voltage MOS device control circuit can be calculated by adjusting the power supply voltage value and monitoring the voltage across the load module, and according to the thermal resistance formula, the chip can be effectively ensured to work in a safe junction temperature condition, and the product reliability is effectively improved.

[0014] The high-voltage MOS array module has the characteristics of high power density, high reliability, high conversion efficiency and the like. Each path mainly utilizes the adjustment of the gate-source voltage to control the conduction and turn-off of the channel between the source and the drain, and a damping protection circuit is added to prevent transient overvoltage pulses in the circuit. It has strong load capacity and can directly drive the load to work. The product adopts a metal ceramic patch airtight packaging, has the characteristics of small size, light weight, wide application, high integration, convenient use and the like in similar products, and can directly drive the load to work and has strong load capacity.

[0015] The module has low coupling, so that even if individual branches are abnormal, it will not affect the normal operation of the whole module, and has higher stability.

[0016] The utility model mainly uses in low loss high power switch technical field, makes voltage control high voltage driver in various electronic circuits, is used to high voltage signal control's switch drive module. It is widely used in the field of aviation, aerospace and the like. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is high-voltage MOS array unit module structure schematic diagram.

[0018] Figure 2The high-voltage MOS array module is connected with a load module.

[0019] Figure 3 The high-voltage PMOS array unit circuit is connected with a load circuit.

[0020] Figure 4 The six-channel high-voltage PMOS array module is connected with a load circuit.

[0021] Figure 5 The six-channel high-voltage PMOS array module is connected with a load circuit.

[0022] Figure 6 The six-channel high-voltage PMOS array module is connected with a load circuit.

[0023] Figure 7 The six-channel high-voltage PMOS array module is connected with a load circuit. DETAILED DESCRIPTION

[0024] As shown in Figures 1-7 , the high-voltage MOS array module and the test circuit thereof are taken as an example of a six-channel high-voltage PMOS driving module, and the specific implementation is as follows:

[0025] The high-voltage MOS device control circuit is a high-voltage PMOS device chip (referred to as a PMOS chip).

[0026] The damping protection circuit is a damping diode chip (referred to as a TVS chip).

[0027] The load module is a resistor.

[0028] The working principle of the high-voltage MOS array module is as follows:

[0029] (1) When the gate and source voltages |U GS | of the PMOS are greater than the threshold voltage |U GS（th） |, the PMOS is turned on, an I D current is generated and flows from the S pole to the D pole, the circuit does work, and the voltage across the TVS device is pulled down by the PMOS on-voltage drop and is in a reverse-biased cutoff state.

[0030] (2) When the gate and source voltages |U GS | of the PMOS are less than the threshold voltage |U GS（th） |, the PMOS is turned off, no ID current is generated, and an external voltage is applied across the PMOS device and the TVS device and the circuit, and the voltage across the PMOS device and the TVS device is V CC, PMOS device and TVS device are in reverse-biased off state, at this time the circuit does not work. When there is a transient overvoltage pulse in the power supply circuit, the TVS device is preferentially broken down to discharge, and since the breakdown voltage of the source-drain of the PMOS device is higher than the breakdown voltage of the TVS, the PMOS device is still in the off state at this time, and the PMOS device is protected from damage.

[0031] The six-channel high-voltage PMOS drive module is a hybrid drive module suitable for up to 350V, adopts a metal ceramic hermetic package, integrates six independent PMOS gate drivers, and further internally embeds six TVS protection devices, mainly solves the use environment of a high-voltage PMOS, and is a switching drive module for high-voltage signal control. The module has the characteristics of small size and light weight, and is arrayed into six channels. The module has low coupling, and even if an individual branch is abnormal, it will not affect the normal operation of the entire module, and the product has higher stability.

[0032] Each channel mainly uses the adjustment of the gate-source voltage to control the conduction and turn-off of the channel between the source and the drain, and can directly drive the load to work, and has strong load capacity, and is mainly used as a voltage control high-voltage driver in various electronic circuits.

[0033] In particular:

[0034] If only for the purpose of achieving embedding protection of the voltage between the source and the drain of the PMOS device, a zener diode can also achieve the same effect as the TVS device, the difference is that the TVS device has a large heat capacity design, and the transient peak absorption capacity of the TVS device is much larger than that of the zener diode, usually more than 10 times that of the zener diode. If it can be confirmed that there is no possibility of generating a high-energy peak pulse in the circuit during design, a zener diode can be used, which can also reduce the package size compared with a TVS device.

[0035] The quantitative analysis of the PMOS control circuit is as follows:

[0036] When the gate and source voltage |U GS | of the PMOS is greater than the threshold voltage |U GS（th） |, the PMOS is turned on. Assuming that the threshold voltage |U GSth |=4V, and when |U GS | (I=1A)=10V, the on-resistance R DS（ON） of the PMOS device is 8.5Ω, then when the gate and source voltage |U GS |≥10V, the channel resistance R DS between the source and the drain of the device is ≤8.5Ω, so at this time the PMOS is equivalent to a closed switch, the PMOS is turned on, and I DThe current, the circuit does work, and the voltage across the TVS device is pulled down to the reverse-biased off state.

[0037] When the gate-source voltage |U GS |≤ threshold voltage |U GSth |=4V, the channel resistance R DS of the PMOS device between the source and drain is much greater than 8.5Ω, and even R DS tends to infinity, so at this time the PMOS device is equivalent to a switch that is turned off, the PMOS is off, and there is no I D current generated. When the VCC voltage is applied across the PMOS device and the TVS device and the circuit is closed, the PMOS device and the TVS device are both in the off state, and at this time the circuit does not do work.

[0038] TVS device protection circuit analysis as follows:

[0039] When there is no high-energy transient overvoltage surge in the circuit, the TVS device is in the reverse-biased off high-resistance state; when an abnormal overvoltage appears in the circuit, the TVS device quickly changes from the high-resistance state to the low-resistance state, and discharges the transient overcurrent caused by the abnormal overvoltage to the ground, while embedding the abnormal overvoltage as the TVS device embedding voltage value Vc, thereby protecting the PMOS device from breakdown damage caused by the abnormal overvoltage between the source and the drain.

[0040] TVS device power consumption: at the drain of the circuit schematic, a load RL is connected, as shown in Figure 3 .

[0041] Suppose Vcc=300V, in the normal working of the circuit, the maximum working current in the circuit is IDmax=2mA, and the voltage drop between the source and the drain of the PMOS device is VDS=200V, then the load RL resistance is calculated as:

[0042] .

[0043] .

[0044] Suppose that at this time the circuit has a transient high voltage Vcc=1500V, the breakdown voltage V BR of the TVS device is 400V, and the duration of the transient high voltage is 1ms. According to the TVS device that breaks down before the PMOS device, the I D current in the circuit at this time is:

[0045] .

[0046] The dissipated power Ptot generated across the TVS device is:

[0047] .

[0048] The energy Qsingle (TVS) generated by the TVS device is approximately:

[0049] .

[0050] Therefore, in the case of a transient high voltage of 1500V and a duration of 1ms, the energy generated by the TVS is approximately Qsingle (TVS) = 0.5 * 1500V * 1ms = 750J, and the total energy of the six-channel TVS device Qtotal (TVS) is approximately:

[0051] .

[0052] For the reliability test circuit:

[0053] Based on the characteristics of the 6-group high-voltage MOS array circuit with a damping diode, the main core of the product reliability test circuit can be divided into four aspects:

[0054] (1) High-temperature reverse bias test of TVS device: The TVS device in the product is subjected to high-temperature reverse bias test under specified test conditions and test temperature, to evaluate the time stability of the leakage current under reverse bias conditions.

[0055] (2) TVS device pulse power test: The TVS device in the product is subjected to power pulse test under specified test conditions and test temperature, to evaluate the pulse peak current and pulse peak power that the product can withstand.

[0056] (3) High-temperature reverse bias test of PMOS device gate-source: The PMOS gate-source in the product is subjected to high-temperature reverse bias test at a temperature of 125°C and a gate-source voltage of 80% of the maximum rated voltage, for at least 48 hours.

[0057] (4) High-temperature power aging circuit of high-voltage MOS array module: The product is subjected to a certain power under high temperature (T=125°C), to evaluate the reliability of the product.

[0058] The specific test method of the reliability test circuit of the high-voltage MOS array is as follows:

[0059] TVS device high-temperature reverse bias test method: Set the environmental temperature T=125°C, short the gate-source of the PMOS device, and apply an aging voltage of V CC =V BR= 375V, test time t = 240h. In order to prevent the abnormal overcurrent in the circuit from damaging the device, a resistance with a resistance of 10k and a power of 1 / 16W and a resistance with a resistance of 20k and a power of 1w are connected in series at the voltage input end (i.e. the source input end). The purpose of such design is to limit the maximum current allowed in the circuit to 10mA. Moreover, if the current in the circuit exceeds 10mA, the power of the resistance with a resistance of 10k is P = (10mA*10mA)2*10k = 1W > 1 / 16W, so the 10k resistance will be burned due to excessive power, thereby forming a circuit protection circuit. As shown in Figure 5 .

[0060] The PMOS device gate-source high temperature reverse bias test method is: the ambient temperature T = 125℃ is set, the drain-source of the PMOS device is short-circuited, and the aging voltage V GS = maximum rated voltage V GS ×80% = 20V*0.8 = 16V, and the test time t = 240h. In order to prevent the abnormal overcurrent in the circuit from damaging the device, a resistance with a resistance of 16k and a power of 1W is connected in series at the voltage input end (i.e. the gate input end) to limit the maximum current allowed in the circuit to 1mA. The circuit is shown in Figure 6 .

[0061] The high temperature power aging test method of the high voltage MOS array module is: the source input end power voltage V CC = 10V of six channels in the given product, the drain output end is connected to the load R L = 68Ω, the working current I = 100mA of each channel, and the saturation voltage drop V SD between the source and the drain of the module is 2V. Then the dissipation power P tot（单） between the source and the drain of the module of each channel is 2x0.1 = 0.2w, so the total current I 总 of six channels is 0.6A, and the total dissipation power P tot (total) = 0.2*6 = 1.2W. The specific high temperature power aging circuit diagram is shown in Figure 7 . The gate end of each channel is connected to the voltage output end of the bias circuit composed of a zener diode and a resistance, the cathode end of the zener diode is connected to the power voltage end, the anode end of the zener diode is connected to the gate of the MOS device and one end of the resistance, and the other end of the resistance is connected to the ground end.

[0062] The beneficial effects of the reliability test scheme are:

[0063] According to the requirement of burn-in design circuit, three burn-in circuits are designed for the product: gate-source burn-in circuit, source-drain burn-in circuit and array high temperature power burn-in circuit. Such design can not only examine the source-drain and gate-drain of PMOS, but also examine the TVS chip as protection, effectively improving the screening rate.

[0064] In the high temperature power burn-in, the PMOS source-drain saturation voltage drop can be calculated by adjusting the power supply voltage value and monitoring the voltage across the load resistor, and according to the thermal resistance formula, the chip can be effectively ensured to work under the junction temperature condition, and the product reliability can be effectively improved.

[0065] Finally, it should be noted that the above examples are merely examples for the sake of clarity, and the utility model includes but is not limited to the above examples, and all the embodiments need not be exhausted here. For ordinary skilled in the art, other different forms of changes or changes can be made on the basis of the above description. Any implementation scheme meeting the requirements of the utility model belongs to the protection scope of the utility model.

Claims

1. A high-voltage MOS array module test circuit, characterized in that: The high-voltage MOS array module includes two or more high-voltage MOS array unit modules and corresponding load modules; The high-voltage MOS array unit module includes a high-voltage MOS device control circuit and a damping protection circuit. The damping protection circuit is connected in reverse parallel to the positive power supply and output terminal of the high voltage MOS device control circuit. The output terminal of each unit module is connected to one end of the load module, and the other end of the load module is connected to the negative power supply terminal or ground terminal. Each high-voltage MOS device control circuit and damping protection circuit correspond one-to-one, and each high-voltage MOS device control circuit with damping protection circuit is independent.

2. The high-voltage MOS array module test circuit as described in claim 1, characterized in that: For the source-drain reverse bias test circuit, the gate and source are short-circuited, and the corresponding port of the source-drain reverse bias test voltage is connected between the source and drain terminals.

3. The high-voltage MOS array module test circuit as described in claim 1, characterized in that: For the gate-source reverse bias test circuit, the drain and source are short-circuited together, and the corresponding port of the gate-source reverse bias test voltage is connected between the source terminal and the gate terminal.

4. The high-voltage MOS array module test circuit as described in claim 1, characterized in that: For the power aging test circuit: the output terminal of the unit module is connected to one end of the load module, the other end of the load module is connected to the negative power supply terminal or ground terminal, the output voltage terminal of the bias voltage circuit is connected to the gate terminal, and the corresponding port of the power aging working voltage is connected between the positive power supply terminal and the negative power supply terminal or ground terminal.

5. The high-voltage MOS array module test circuit as described in claim 1, characterized in that: The control circuit for the high-voltage MOS device is a high-voltage PMOS device. The damping protection circuit is a TVS device; The load module is a resistor.

6. The high-voltage MOS array module test circuit as described in claim 5, characterized in that: Short-circuit the gate and source of the PMOS device, and connect the aging voltage V across the TVS device. CC Two resistors are connected in series at the voltage input terminal.

7. The high-voltage MOS array module test circuit as described in claim 6, characterized in that: The aging voltage V CC The voltage is 300V. The two resistors are a 10kΩ resistor with a power of 1 / 16W and a 20kΩ resistor with a power of 1W.

8. The high-voltage MOS array module test circuit as described in claim 5, characterized in that: Short-circuit the drain and source terminals of the PMOS device, and connect the aging voltage V across the gate and source terminals of the PMOS. GS A resistor is connected in series at the voltage input terminal.

9. The high-voltage MOS array module test circuit as described in claim 8, characterized in that: The aging voltage V GS 16V ， The resistor has a resistance of 16kΩ and a power rating of 1W.

10. The high-voltage MOS array module test circuit as described in claim 5, characterized in that: The gate of each channel is connected to the voltage output of the bias circuit composed of a Zener diode and a resistor. The cathode of the Zener diode is connected to the power supply voltage terminal, the anode of the Zener diode is connected to the gate of the MOS device, one end of the resistor is connected, and the other end of the resistor is connected to ground.

Images