Novel LRM backboard high-speed serial bus test module

Abstract

The utility model discloses a novel LRM backboard high-speed serial bus test module, which comprises a GTX serial data processing circuit taking an FPGA as a core, a 12C isolation buffer interface circuit, a control circuit, an SFP 1 + interface circuit, an SFP 2 + interface circuit and an LRM high-speed connector circuit, and is characterized in that the GTX serial data processing circuit is correspondingly connected with the SFP 1 + interface circuit and the SFP 2 + interface circuit respectively; the SFP < 1 + > interface circuit and the SFP < 2 + > interface circuit are respectively connected with an external computer through an LAN1 port and an LAN2 port, and the GTX serial data processing circuit is connected with the LRM high-speed connector circuit through a 10GBASEKR1 interface and a 10GBASEKR2 interface. The test module can meet the test requirements of the high-speed serial bus of the LRM backboard, and the purpose of verifying whether the signal integrity of the high-speed serial bus of the backboard meets the requirements or not is achieved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of vehicle-mounted field replaceable unit LRM backboard high -speed serial bus signal integrity test, especially relates to a novel LRM backboard high -speed serial bus test module. BACKGROUND

[0002] At present, the vehicle-mounted field replaceable unit (LRM) backboard high -speed serial bus signal rate is high, and performance test verification is inconvenient, and the use of special test instrument test custom cost is high, the degree of integration is not high, can only carry out ping package and fill package design, cannot realize the test of eye diagram, error rate, does not adopt modularization, standardization design, can not be flexibly configured and expanded according to different needs of different modules. CONTENT OF UTILITY MODEL

[0003] In order to overcome the technical defects that the existing vehicle-mounted field replaceable unit LRM backboard cannot realize the test of eye diagram and error rate and does not adopt modularization and standardization design, the utility model provides a novel LRM backboard high -speed serial bus test module, mainly used for the eye diagram, error rate, transmission bandwidth and communication protocol test of LRM backboard 10Gbase-KR bus interface.

[0004] The utility model provides a novel LRM backboard high -speed serial bus test module, including the GTX serial data processing circuit with FPGA as the core, 12C isolation buffer interface circuit, the control circuit with MCU as the core, SFP1+ interface circuit, SFP2+ interface circuit and LRM high -speed connector circuit, GTX serial data processing circuit is connected with SFP1+ interface circuit, SFP2+ interface circuit respectively correspondingly, SFP1+ interface circuit, SFP2+ interface circuit is connected with the computer of outside respectively through LAN1 and LAN2, GTX serial data processing circuit is connected with LRM high -speed connector circuit through 10G_BASE_KR1 interface and 10G_BASE_KR2 interface, LRM high -speed connector circuit is connected with the LRM backboard of detection, and control circuit is connected with LRM backboard through 12C isolation buffer interface circuit and LRM high -speed connector circuit in proper order.

[0005] The processing flow of the novel LRM backboard high-speed serial bus test module for LRM backboard transmission bandwidth test data is as follows: in the sending direction, the network packet sent by the computer is input to the SPF1+ interface circuit through the LAN1 port, and after photoelectric conversion, the output is 10G high-speed serial data, the 10G-GXT1 network packet is subjected to data processing by the GTX serial data processing circuit with FPGA as the core, and the output 10G-Base-KR signal is connected to the LRM backboard through the LRM high-speed connector circuit.

[0006] The processing flow of the novel LRM backboard high-speed serial bus test module for backboard communication protocol test data is as follows: in the sending direction, the control circuit with MCU as the core is used for simulating the IPMB protocol, and the test module state query result is sent to the LRM backboard through the I2C isolation buffer interface circuit and the LRM high-speed connector circuit.

[0007] The processing flow of the novel LRM backboard high-speed serial bus test module for backboard eye diagram and bit error rate test data is as follows: in the sending direction, the GTX serial data processing circuit with FPGA as the core is connected to the computer for online configuration parameter, and the pseudo-random binary sequence (PRBS) is sent, and the measured pseudo-random binary sequence is sent to the LRM high-speed connector circuit through the 10G_BASE_KR interface and input to the LRM backboard.

[0008] Therefore, the novel LRM backboard high-speed serial bus test module can realize the test of the eye diagram, the error rate, the transmission bandwidth and the communication protocol of the 10Gbase-KR bus interface between each slot of the LRM backboard, and can verify whether the produced backboard meets the design requirements,

[0009] Preferably, in the GTX serial data processing circuit, the FPGA is a core of data processing, and internally integrated with an IBERT core; the GTX serial data processing circuit further comprises a first GTX transceiver, a second GTX transceiver, a third GTX transceiver, a fourth GTX transceiver, a first switch selection module and a second switch selection module; the GTX serial data processing circuit is connected with a computer through a JTAG interface, to complete parameter setting, evaluation and monitoring of the first GTX transceiver, the second GTX transceiver, the third GTX transceiver and the fourth GTX transceiver on line; the first GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR1 interface; the second GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR2 interface; the third GTX transceiver is connected with the SFP1+ interface circuit through a 10G-GTX1 interface; the fourth GTX transceiver is connected with the SFP2+ interface circuit through a 10G-GTX2 interface; the first switch selection module is connected between the first GTX transceiver and the third GTX transceiver; the second switch selection module is connected between the second GTX transceiver and the fourth GTX transceiver; the first switch selection module and the second switch selection module are connected with the IBERT core respectively; the FPGA is further connected with a clock module; a 156.25MHz clock generated by the clock module is input to the FPGA as a reference; the first switch selection module and the second switch selection module select according to a test item, and signals of the first GTX transceiver and the second GTX transceiver are connected to the third GTX transceiver and the fourth GTX transceiver respectively for transmission bandwidth test; the signals of the first GTX transceiver and the second GTX transceiver are connected to the IBERT core for eye diagram and error rate test.

[0010] Preferably, the control circuit with the MCU as a core is used for completing simulation of the IPMB bus transmission protocol; the MCU is connected with a crystal oscillator and a reset circuit; the crystal oscillator provides a 25M clock signal for the MCU; the reset circuit is used for resetting the MCU when the module is initialized; the MCU is connected with the 12C isolation buffer interface circuit through a 12C1 interface and a 12C2 interface respectively.

[0011] Compared with the prior art, the technical scheme of the utility model has the following technical effects: the utility model adopts the highly integrated, standardized design idea, completes digital, analog, power supply, optical fiber and various communication functions, can carry out signal integrity test, communication protocol test and the like according to the various functional performance test requirements of different LRM modules; the test module can meet the test requirements of the LRM backboard high-speed serial bus, achieves the purpose of verifying whether the backboard high-speed serial bus signal integrity meets the requirements, is applicable to the test of different vehicle-mounted LRM backboards, and has very wide application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0012] The drawings incorporated into the specification and constituting a part of the specification show embodiments consistent with the utility model and, together with the specification, serve to explain the principle of the utility model.

[0013] In order to more clearly illustrate the technical scheme in the embodiments of the utility model or the prior art, the drawings needed to be used in the embodiment or the prior art description will be briefly introduced as follows, and obviously, other drawings can be obtained by the drawings for the ordinary skilled in the art without creative labor.

[0014] Figure 1 It is the whole module connection principle schematic view of a novel LRM backboard high-speed serial bus test module in some embodiments of the utility model;

[0015] Figure 2 It is the module connection principle schematic view of the GTX serial data processing circuit in some embodiments of the utility model;

[0016] Figure 3 It is the module connection principle schematic view of the control circuit in some embodiments of the utility model;

[0017] Figure 4 It is the module connection principle schematic view of the LRM high-speed connector circuit in some embodiments of the utility model;

[0018] Figure 5 It is the composition schematic view of the LRM backboard in some embodiments of the utility model. DETAILED DESCRIPTION

[0019] In order to more clearly illustrate the above-mentioned purpose, features and advantages of the utility model, the scheme of the utility model will be further described as follows.It should be explained that the embodiments of the utility model and the features in the embodiments can be combined mutually without conflict.

[0020] In the description, it needs to be explained that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance. It needs to be explained that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0021] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein; Obviously, the examples in the specification are only a part of the embodiments of the present application, not all the embodiments.

[0022] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0023] In one embodiment, as shown in Figure 1 A novel LRM backboard high-speed serial bus test module, comprising a GTX serial data processing circuit with FPGA as the core, a 12C isolation buffer interface circuit, a control circuit with MCU as the core, an SFP1+ interface circuit, an SFP2+ interface circuit and an LRM high-speed connector circuit, the GTX serial data processing circuit is connected with the SFP1+ interface circuit and the SFP2+ interface circuit respectively, the SFP1+ interface circuit and the SFP2+ interface circuit are connected with the external computer through LAN1 and LAN2 respectively, the GTX serial data processing circuit is connected with the LRM high-speed connector circuit through 10G_BASE_KR1 and 10G_BASE_KR2, the LRM high-speed connector circuit is connected with the LRM backboard to be detected, and the control circuit is connected with the LRM backboard through the 12C isolation buffer interface circuit and the LRM high-speed connector circuit.

[0024] The processing flow of the novel LRM backboard high-speed serial bus test module for LRM backboard transmission bandwidth test data is as follows: in the sending direction, the network packet sent by the computer is input to the SPF1+ interface circuit through the LAN1 port, and after photoelectric conversion, the output is 10G high-speed serial data, the 10G-GXT1 network packet is subjected to data processing by the GTX serial data processing circuit with FPGA as the core, and the output 10G-Base-KR signal is connected to the LRM backboard through the LRM high-speed connector circuit.

[0025] The processing flow of the novel LRM backboard high-speed serial bus test module for backboard communication protocol test data is as follows: in the sending direction, the control circuit with MCU as the core is used for simulating the IPMB protocol, and the test module state query result is sent to the LRM backboard through the I2C isolation buffer interface circuit and the LRM high-speed connector circuit.

[0026] The processing flow of the novel LRM backboard high-speed serial bus test module for backboard eye diagram and bit error rate test data is as follows: in the sending direction, the GTX serial data processing circuit with FPGA as the core is connected to the computer for online configuration parameter, and the pseudo-random binary sequence (PRBS) is sent, and the measured pseudo-random binary sequence is sent to the LRM high-speed connector circuit through the 10G_BASE_KR interface and input to the LRM backboard.

[0027] Therefore, the novel LRM backboard high-speed serial bus test module can realize the test of the eye diagram, the error rate, the transmission bandwidth and the communication protocol of the 10Gbase-KR bus interface between each slot of the LRM backboard, can verify whether the produced backboard meets the design requirements, and on the basis of the above embodiment, in a preferred embodiment, in the GTX serial data processing circuit, the FPGA is the core of data processing, and an IBERT core is integrated in the FPGA, the GTX serial data processing circuit further includes a first GTX transceiver, a second GTX transceiver, a third GTX transceiver, a fourth GTX transceiver, a first switch selection module and a second switch selection module, the GTX serial data processing circuit is connected with a computer through a JTAG interface, and is used for completing parameter setting, evaluation and monitoring of the first GTX transceiver, the second GTX transceiver, the third GTX transceiver and the fourth GTX transceiver on line; the first GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR1 interface, the second GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR2 interface, the third GTX transceiver is connected with an SFP1+ interface circuit through a 10G-GTX1 interface, and the fourth GTX transceiver is connected with an SFP2+ interface circuit through a 10G-GTX2 interface; the first switch selection module is connected between the first GTX transceiver and the third GTX transceiver, the second switch selection module is connected between the second GTX transceiver and the fourth GTX transceiver, and the first switch selection module and the second switch selection module are connected with the IBERT core respectively; the FPGA is further connected with a clock module, a 156.25MHz clock generated by the clock module is input to the FPGA as a reference, the first switch selection module and the second switch selection module select according to a test item, and signals of the first GTX transceiver and the second GTX transceiver are connected to the third GTX transceiver and the fourth GTX transceiver respectively to test the transmission bandwidth; the signals of the first GTX transceiver and the second GTX transceiver are connected to the IBERT core to test the eye diagram and the error rate. Specifically, the FPGA is a Zynq7000 series of Xilinx Corporation.

[0028] On the basis of the above embodiment, in a preferred embodiment, the control circuit with the MCU as the core is used for completing simulation of the IPMB bus transmission protocol, the MCU is connected with a crystal oscillator and a reset circuit, the crystal oscillator provides a 25M clock signal for the MCU, and the reset circuit is used for resetting the MCU when the module is initialized; the MCU is connected with the 12C isolation buffer interface circuit through a 12C1 interface and a 12C2 interface respectively. Specifically, the model of the MCU is GD32F107.

[0029] In a specific embodiment, the high-speed LRM connector interface circuit mainly exchanges data with other modules on the backplane through the 10G_BASE_KR bus interface of the high-speed LRM connector, and performs management communication through the I2C management bus interface of the high-speed LRM connector.

[0030] The LRM high-speed connector circuit adopts a modular combination structure, and can simultaneously integrate and transmit two sets of management I2C interfaces and two sets of service 10G_BASE_KR interfaces. The transmission rate of the differential contact of the LRM high-speed connector circuit selected this time is 13 Gbps, the characteristic impedance is 100 ohms, the voltage resistance is 300 V, the high-speed serial signal received by the LRM backplane is input to the differential contact pin of the LRM high-speed connector circuit, and the high-speed serial data wiring technology is used in PCB design. The high-speed serial signal is all inner-layer wiring, and the impedance of the differential signal is designed to be 100 ohms; the high-speed differential signal line is ensured to be equal width and equal spacing to achieve a specific differential impedance value distribution, and the differential signal line should be symmetrical as much as possible. According to the data manual of the LRM high-speed connector circuit, the differential pair signals inside are not equal in length, and the maximum delay of one differential pair can reach dozens of PS during high-speed differential signal transmission. Pin_delay compensation is set during PCB design to compensate the time of the differential signals in the group and ensure the timing consistency of the signals in the group.

[0031] After the above wiring, the received monitoring status signal is input into the MCU-based control circuit through the I2C1 interface and the I2C1 interface for subsequent processing. The ground pin is connected to the GND signal.

[0032] The composition schematic diagram of the LRM backplane is shown in Figure 5 The software of the operation computer completes the ping packet and transmission rate verification test of the gigabit Ethernet bus interface between each slot of the LRM backplane, and also completes the eye diagram and error code test of the 10G high-speed serial bus between any slots of the LRM backplane. The test results are shown in Figure 3 、 4 At a rate of 10 Gbit / s, 5,000 packets of Ping are transmitted, each packet has 1,500 bytes and no packet is lost; the average transmission rate is 9.49 Gb / s; the test data is 2E12, and the error rate is 0. The test results show that the test module can meet the test requirements of the high-speed serial bus of the LRM backplane, and the purpose of verifying whether the high-speed serial bus signal of the backplane meets the requirements is achieved. It is suitable for testing different vehicle-mounted LRM backplanes and has very wide application scenarios.

[0033] The above merely describes specific implementation manners of the present application, and enables those skilled in the art to understand or implement the present application. Although the foregoing embodiments are described in detail, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments, and should be covered in the protection scope of the claims.

Claims

1. A novel LRM backplane high speed serial bus test module characterized by, The GTX serial data processing circuit with FPGA as the core, the 12C isolation buffer interface circuit, the control circuit with MCU as the core, the SFP1+ interface circuit, the SFP2+ interface circuit and the LRM high-speed connector circuit are connected correspondingly, the SFP1+ interface circuit and the SFP2+ interface circuit are connected with the external computer through LAN1 and LAN2 respectively, the GTX serial data processing circuit is connected with the LRM high-speed connector circuit through 10G_BASE_KR1 and 10G_BASE_KR2, the LRM high-speed connector circuit is connected with the LRM backboard to be detected, and the control circuit is connected with the LRM backboard through the 12C isolation buffer interface circuit and the LRM high-speed connector circuit.

2. A novel LRM backplane high speed serial bus test module according to claim 1, characterized in that, In the GTX serial data processing circuit, the FPGA is the core of data processing, and has an IBERT core integrated therein, the GTX serial data processing circuit further comprises a first GTX transceiver, a second GTX transceiver, a third GTX transceiver, a fourth GTX transceiver, a first switch selection module and a second switch selection module, the GTX serial data processing circuit is connected with the computer through a JTAG interface, to complete the parameter setting of the first GTX transceiver, the second GTX transceiver, the third GTX transceiver and the fourth GTX transceiver, and to evaluate and monitor the first GTX transceiver, the second GTX transceiver, the third GTX transceiver and the fourth GTX transceiver; the first GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR1 interface, the second GTX transceiver is connected with the LRM high-speed connector circuit through a 10G_BASE_KR2 interface, the third GTX transceiver is connected with the SFP1+ interface circuit through a 10G-GTX1 interface, and the fourth GTX transceiver is connected with the SFP2+ interface circuit through a 10G-GTX2 interface; the first switch selection module is connected between the first GTX transceiver and the third GTX transceiver, the second switch selection module is connected between the second GTX transceiver and the fourth GTX transceiver, and the first switch selection module and the second switch selection module are connected with the IBERT core respectively; the FPGA is further connected with a clock module, a 156.25MHz clock generated by the clock module is input to the FPGA as a reference, the first switch selection module and the second switch selection module select the signals of the first GTX transceiver and the second GTX transceiver to be connected to the third GTX transceiver and the fourth GTX transceiver respectively for transmission bandwidth test, and the signals of the first GTX transceiver and the second GTX transceiver are connected to the IBERT core for eye diagram and error rate test.

3. A novel LRM backplane high speed serial bus test module according to claim 1, characterized in that, The control circuit with the MCU as the core is used for completing simulation of the IPMB bus transmission protocol, the MCU is connected with a crystal oscillator and a reset circuit, the crystal oscillator provides a 25M clock signal for the MCU, and the reset circuit is used for resetting the MCU when initializing the module; the MCU is connected with the 12C isolation buffer interface circuit through a 12C1 interface and a 12C2 interface respectively.

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