Interconnection structure

Abstract

An interconnect structure includes a first conductive feature in a first dielectric layer, a conductive capping layer over the first conductive feature, a second dielectric layer over an etch stop layer, and a second conductive feature extending through the second dielectric layer. The second conductive feature includes a barrier layer on a sidewall of the second dielectric layer, a liner on the barrier layer and in physical contact with the conductive capping layer, a seed layer on the liner, and a conductive fill layer on the seed layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an interconnect structure. BACKGROUND

[0002] The integrated circuit (IC) industry has experienced rapid growth. The technology advances in IC materials and design have produced generations of ICs, each having smaller and more complex circuitry than the previous generation. In the pursuit of smaller ICs, greater integration, higher performance, and lower costs, there has been a continual trend toward reducing the size of the individual elements (e.g., transistors, resistors, capacitors, inductors, etc.) that make up the integrated circuitry. In addition, there has been a trend toward reducing the size of the overall IC while increasing the density of the elements that it contains. Such shrinking of the size of ICs allows for more complex circuits to be constructed on a single IC.

[0003] This shrinking has also increased the complexity of processing and manufacturing ICs, and to take advantage of these advances, similar developments in IC processing and manufacturing are needed. For example, as multilayer interconnect (MLI) features become more closely spaced with ever-shrinking IC feature sizes, the interconnect performance of the MLI features exhibits increased contact resistance, which presents performance, yield, and cost challenges. It has been observed that the higher contact resistance exhibited by interconnects in advanced IC technology nodes can significantly delay (and in some cases, prevent) signals from being routed efficiently to and from IC devices such as transistors, negating any improvements in performance of such IC devices in advanced technology nodes. Thus, while existing interconnects are generally adequate for their intended purpose, they are not entirely satisfactory in all respects. SUMMARY

[0004] In one illustrative aspect, the present disclosure is directed to an interconnect structure. The interconnect structure includes a first conductive feature, a second dielectric layer, a second conductive feature, and an auxiliary liner. The first conductive feature is located in a first dielectric layer, where the first conductive feature includes a seed layer, a first metal fill layer located above the seed layer, and a conductive cap layer located above the first metal fill layer. The second dielectric layer is located above the first dielectric layer, and the second conductive feature extends through the second dielectric layer, where the second conductive feature includes a barrier layer and a second metal fill layer located above the barrier layer. The auxiliary liner is located between the conductive cap layer and the barrier layer, where the auxiliary liner includes cobalt.

[0005] In another illustrative aspect, the disclosure relates to an interconnect structure. The interconnect structure includes a first conductive feature, a second dielectric layer, and a second conductive feature. The first conductive feature is located in a first dielectric layer. The second dielectric layer is located over the first dielectric layer. The second conductive feature extends through the second dielectric layer, wherein the second conductive feature includes a seed layer and a metal fill layer located over the seed layer. The seed layer is a metal alloy layer containing a primary metal element and an additive metal element.

[0006] In another illustrative aspect, the disclosure relates to an interconnect structure. The interconnect structure includes a first conductive feature, a second dielectric layer, and a second conductive feature. The first conductive feature is located in a first dielectric layer. The second dielectric layer is located over the first dielectric layer. The second conductive feature extends through the second dielectric layer, wherein the second conductive feature includes a seed layer and a metal fill layer located over the seed layer. The seed layer is a metal alloy layer containing a primary metal element and an additive metal element. BRIEF DESCRIPTION OF DRAWINGS

[0007] The disclosure can best be understood by reading the following detailed description in conjunction with the accompanying drawings in the specification. It should be emphasized, however, that various features are not to scale in the drawings and are given for purposes of illustration only. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A cross-sectional view of layers involved in an interconnect structure of a semiconductor device according to some embodiments of the disclosure is illustrated;

[0009] Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 and Figure 14 A cross-sectional view of an interconnect structure at an intermediate stage of forming metal lines and vias according to some embodiments of the disclosure is illustrated;

[0010] Figure 15 A process flow for forming metal lines and vias in an interconnect structure according to some embodiments of the disclosure is illustrated.

[0011] SYMBOL DESCRIPTION

[0012] 100: semiconductor device

[0013] 102: semiconductor substrate

[0014] ​​​​​​​​​​​104: circuit device

[0015] 106, 120: dielectric layer

[0016] 108: conductive feature

[0017] 110, 142: barrier layer

[0018] 112, 144: liner

[0019] 114, 154: seed layer

[0020] 116: metal fill layer

[0021] 117, 121, 167: cap layer

[0022] 118, 168: etch stop layer

[0023] 122, 132: hard mask

[0024] 124: via opening

[0025] 126: trench

[0026] 128, 134: opening

[0027] 130: BARC layer

[0028] 140: inhibitor film

[0029] 142', 144': discrete island regions

[0030] 150: post-deposition treatment

[0031] 152: gap

[0032] 156: conductive material

[0033] 164: via

[0034] 166: metal line

[0035] 200: process flow

[0036] 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224: process

[0037] T1, T2, T3, T4,..., Ttop: thickness DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of elements and configurations are described below to provide a thorough description of various embodiments. Of course, these are merely examples, and are in no way limiting. For instance, in the following description, forming a first feature over or on a second feature can include embodiments where the first and second features are formed in direct contact, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. Moreover, this disclosure can repeat reference numerals and / or letters in the various examples and / or drawings. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0039] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Still further, unless otherwise noted, when a range of numbers is provided, the term "about" is intended to encompass numbers within + / - 10% of the stated range. For example, the term "about 5 nm" encompasses a range of sizes from 4.5 nm to 5.5 nm.

[0040] IC fabrication process flows are generally divided into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). FEOL generally encompasses processes related to making IC devices such as transistors. For example, FEOL processes can include forming isolation features, gate structures, and source and drain features (often referred to as source / drain features). MEOL generally encompasses processes related to making contacts of conductive features (or conductive regions) of IC devices, such as contacts of gate structures and / or source / drain features. BEOL generally encompasses processes related to making multilayer interconnect (MLI) features that interconnect IC features made by FEOL and MEOL (referred to herein as FEOL and MEOL features or structures, respectively) to enable operation of the IC device.

[0041] As IC technology moves toward smaller technology nodes, MEOL and BEOL processes are experiencing significant challenges. For example, advanced IC technology nodes require tighter MLI features, which requires significantly reducing the critical dimensions of the interconnects of the MLI features (e.g., the width and / or height of the interconnects' vias and / or wires). Reduced critical dimensions have resulted in significantly increased interconnect resistance, which can reduce IC device performance (e.g., by increasing resistance-capacitance (RC) delay).

[0042] Embodiments of interconnect structures that provide low-resistance via and metal line structures (collectively, contact structures) are disclosed. The contact structures typically include a diffusion barrier layer. The diffusion barrier layer has the function of preventing the diffusion of metallic elements in the contact structures (such as copper) into the dielectric layers that surround the contact structures. The diffusion barrier layer typically has a high resistivity, which increases the contact resistance between the contact structures and underlying interconnect features. In some embodiments of the present disclosure, a low-resistance contact structure includes a barrier layer that is selectively formed on the sidewalls of the contact structure, rather than on the underlying interconnect features. By not having the barrier layer directly contact the underlying interconnect features, the contact resistance can be reduced, and thus the overall resistance of the contact structure.

[0043] Figure 1 A schematic cross-sectional view illustrating a plurality of layers involved in a semiconductor device 100 is shown. It should be noted that, Figure 1illustrated to show various levels of interconnect structures and circuit device regions (e.g., transistors), and can not reflect an actual cross-sectional view of the semiconductor device 100. The interconnect structures include a contact level, an OD (where the term "OD" means "active region") level; via levels: Via_0 level, Via_1 level, Via_2 level, and Via_3 level; and metal levels: M1 level, M2 level, M3 level, M4 level,..., Mtop level. Each of the illustrated levels includes one or more dielectric layers and conductive features formed therein. Conductive features at the same level can have top surfaces that are substantially planar with each other, bottom surfaces that are substantially planar with each other, and can be formed at the same time. The contact level can include gate contacts (also known as contact plugs) for connecting gate electrodes of transistors to an overlying level, such as the Via_0 level, and source / drain contacts (labeled as "contacts") for connecting source / drain regions of transistors to an overlying level. The thicknesses of metal lines at the metal levels (M1 level, M2 level, M3 level, M4 level,..., Mtop level) are denoted as T1, T2, T3, T4,..., Ttop, respectively. It should also be noted that metal lines at higher levels generally have greater thicknesses than metal lines at lower levels (i.e., T1 < T2 < T3 < T4 <... < Ttop). In addition, metal lines at higher levels generally have greater pitches (e.g., center-to-center distances or edge-to-edge distances between adjacent metal lines) than metal lines at lower levels.

[0044] Figures 2 to 14 A cross-sectional view illustrating an intermediate stage of forming a contact structure in the semiconductor device 100 according to some embodiments of the present disclosure is shown. In particular, for simplicity, Figures 2 to 14 A cross-sectional view illustrating an intermediate stage of forming two consecutive metal level of an interconnect structure of the semiconductor device 100 and a corresponding via level therebetween (e.g., M x level, Via_x level, and M x+1 level, where x denotes an integer) according to some embodiments is shown. The corresponding processes are also schematically reflected in the process flow 200 as shown in Figure 15 Additional processes can be provided before, during, and after the process flow 200, and for additional embodiments of the process flow 200, some of the processes described can be moved, replaced, or omitted. Additional features can be added to the interconnect structure depicted in Figures 2 to 14 and in other embodiments of the interconnect structure depicted in Figures 2 to 14 some of the features described below can be replaced, modified, or omitted.

[0045] Figure 2A cross-sectional view of a semiconductor device 100 is illustrated. According to some embodiments of the present disclosure, the semiconductor device 100 is a device wafer that includes active devices such as transistors and / or diodes and can include passive devices such as capacitors, inductors, resistors, or the like. According to alternative embodiments of the present disclosure, the semiconductor device 100 is an interposer wafer that can or can not include active devices and / or passive devices. According to yet alternative embodiments of the present disclosure, the semiconductor device 100 is a package substrate strip that can include a package substrate with a core therein or a coreless package substrate. In the following discussion, a device wafer is used as an example of the semiconductor device 100. The teachings of the present disclosure can also be applicable to interposer wafers, package substrates, packages, and the like.

[0046] According to some embodiments of the present disclosure, the semiconductor device 100 includes a semiconductor substrate 102 and features formed at a top surface of the semiconductor substrate 102. The semiconductor substrate 102 can comprise crystalline silicon, crystalline germanium, silicon-germanium, a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. The semiconductor substrate 102 can also be a bulk silicon substrate or a Silicon-On-Insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown in Figure 2 but shown in Figure 1 ) can be formed in the semiconductor substrate 102 to isolate active regions in the semiconductor substrate 102. Although not shown, vias can be formed to extend into the semiconductor substrate 102, where the vias are used to electrically couple features on opposite sides of the semiconductor device 100 to each other.

[0047] According to some embodiments of the present disclosure, circuit devices 104 are formed on the top surface of the semiconductor substrate 102. Examples of the circuit devices 104 include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, or the like. Details of the circuit devices 104 are not illustrated herein.

[0048] Figure 2Further described is dielectric layer 106. Dielectric layer 106 can be an Inter-Layer Dielectric (ILD) layer or an Inter-Metal Dielectric (IMD) layer. According to some embodiments of the present disclosure, dielectric layer 106 is an ILD layer in which a contact plug is formed. Dielectric layer 106 can be formed from Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-Doped Phospho Silicate Glass (BPSG), Fluorine-Doped Silicate Glass (FSG), a silicon oxide layer (formed using Tetra Ethyl Ortho Silicate (TEOS)), or the like. Dielectric layer 106 can be formed using spin coating, Atomic Layer deposition (ALD), Flowable Chemical Vapor Deposition (FCVD), Chemical Vapor Deposition (CVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Low-Pressure Chemical Vapor Deposition (LPCVD), or the like. According to some embodiments of the present disclosure, dielectric layer 106 is an IMD layer in which metal lines and / or vias are formed. Dielectric layer 106 can be formed from carbon-containing low-k dielectric material, Hydrogen Silses Quioxane (HSQ), Methyl Silses Quioxane (MSQ), or the like. According to some embodiments of the present disclosure, forming dielectric layer 106 includes depositing a dielectric material containing a pore-forming agent, and then performing a curing process to drive off the pore-forming agent, and thus the remaining dielectric layer 106 is porous.

[0049] Conductive features 108 are formed in dielectric layer 106. Conductive features 108 can be metal lines, conductive vias, contact plugs, or the like. According to some embodiments, conductive features 108 include a barrier layer 110, a liner 112, a seed layer 114, a metal fill layer 116 over seed layer 114, and a cap layer 117 over metal fill layer 116. Barrier layer 110 can be formed of a conductive material such as Ta, TaN, TaC, Ti, TiN, TiC, and other suitable materials that can block diffusion of metal elements, and can be deposited using ALD, CVD, ELD, or PVD, and barrier layer 110 can be formed to a thickness of between about 0.5 nm to about 5 nm. Barrier layer 110 can also be referred to as a diffusion barrier layer. According to some embodiments of the present disclosure, forming conductive features 108 can also employ a method as discussed later such that a bottom portion of barrier layer 110 is not formed.

[0050] Liner 112 is deposited on barrier layer 110. In some implementations, liner 112 can be deposited using ALD, CVD, ELD, or PVD, and can be formed to a thickness of between about 0.5 nm to 3 nm. Liner 112 can be formed of a suitable metal, metal nitride, or metal carbide such as Co, CoN, and RuN. In one example, liner 112 is made of Co. Liner 112 serves to increase adhesion between seed layer 114 and barrier layer 110. Liner 112 can also be referred to as an adhesion layer.

[0051] Seed layer 114 is formed on liner 112. In some implementations, seed layer 114 is a metal alloy layer containing at least a main metal element (e.g., copper (Cu)) and an additive metal element (e.g., manganese (Mn)). In one example, seed layer 114 is a copper manganese (CuMn) layer. In other embodiments, Ti, Al, Nb, Cr, V, Y, Tc, Re, or the like can be used as an alternative additive metal for forming seed layer 114. In some embodiments, the concentration (atomic percentage) of the additive metal element in the copper alloy layer can range from about 0.5% to about 5%. As explained in further detail below, in some embodiments, the concentration of the additive metal element can vary among contact structures at different levels. In one example, the copper alloy layer is a CuMn layer, and contact structures at higher levels have a higher concentration of manganese than contact structures at lower levels. Seed layer 114 can be deposited by using ALD, CVD, ELD, PVD, or other suitable deposition techniques.

[0052] The metal fill layer 116 can be formed of copper, copper alloy, aluminum, or the like. The barrier layer 110 has a function of preventing materials in the metal fill layer 116, such as copper, from diffusing into the dielectric layer 106. In some embodiments, the metal fill layer 116 can be deposited using PVD, CVD, ALD, electroplating, ELD, or other suitable deposition processes, or a combination thereof. After the metal fill layer 116 is deposited, a planarization process, such as a chemical mechanical planarization (CMP) process or a mechanical polishing process, can be performed to remove excess portions of the conductive material of the metal fill layer 116.

[0053] A capping layer 117 is deposited on the metal fill layer 116. The respective process is illustrated as process 202 in the process flow 200 shown in FIG. 2. In some embodiments, the CMP process performed prior to removing the excess portions of the conductive material of the metal fill layer 116 also slightly recesses the top surfaces of the metal fill layer 116 and the seed layer 114. The capping layer 117 is deposited on the recessed top surfaces of the metal fill layer 116 and the seed layer 114. The liner 112 can surround the capping layer 117 and separate the capping layer 117 from the barrier layer 110. To facilitate some embodiments, the top surfaces of the barrier layer 110, the liner 112, and the capping layer 117 can be substantially coplanar. In some other embodiments, the CMP process also recesses the liner 112 such that the capping layer 117 covers the top surfaces of the liner 112, the seed layer 114, and the metal fill layer 116. Thus, the capping layer 117 can physically contact the barrier layer 110. Figure 15 The capping layer 117 is formed of a conductive material, which can include, but is not limited to, a metal, a metal nitride, or a metal carbide. In some implementations, the capping layer 117 can be formed of Co, CoN, RuN, or a combination thereof. To facilitate some embodiments, the capping layer 117 and the liner 112 have the same material composition. For example, both the capping layer 117 and the liner 112 can be formed of Co. As explained in further detail below, an auxiliary liner having substantially the same material composition as the liner 112 will be deposited on the capping layer 117 at the bottom of the via opening. Making the capping layer 117 also of the same material composition allows the conductive materials from the capping layer 117 and the auxiliary liner to be combined into a thicker conductive layer, which helps to further reduce the contact resistance. In some other embodiments, the capping layer 117 and the liner 112 can include different material compositions. For example, the liner 112 can be formed of Co, while the capping layer 117 can be formed of CoN. In the depicted embodiment, the capping layer 117 is thinner than the liner 112. Alternatively, the capping layer 117 can have the same thickness as the liner 112 or can be thicker than the liner 112.

[0054]

[0055] ​Just like Figure 2 As shown, an etch stop layer 118 is formed over the dielectric layer 106 and the conductive feature 108. The etch stop layer 118 is formed of a material with high etch selectivity relative to the overlying dielectric layer 120, and therefore the etch stop layer 118 can be used to terminate the etching of the dielectric layer 120. According to some embodiments of this disclosure, the etch stop layer 118 is formed of a dielectric material, which may include, but is not limited to, aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or the like. In various embodiments, the etch stop layer 118 may have a greater thickness than the liner 112.

[0056] Dielectric layer 120 is formed above etch stop layer 118. Individual processes are described as follows: Figure 15 Process 204 in the process flow 200 shown. According to some embodiments, dielectric layer 120 is an IMD layer or an ILD layer. Dielectric layer 120 may include dielectric materials such as oxides, nitrides, carbon-containing dielectric materials, or the like. For example, dielectric layer 120 may be formed of PSG, BSG, BPSG, FSG, TEOS oxide, HSQ, MSQ, or the like. Dielectric layer 120 may also be a low-k dielectric layer having a low dielectric constant value of less than about 3.5 or less than about 3.0.

[0057] A capping layer 121 is formed over the dielectric layer 120. According to some embodiments of this disclosure, the capping layer 121 is formed of a dielectric material, which may include, but is not limited to, aluminum oxide, aluminum nitride, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, or the like. A hard mask 122 is formed over the capping layer 121. The hard mask 122 is formed by patterning the hard mask layer to form openings 128 therein, wherein the openings 128 define a pattern of trenches to be filled to form metal lines. According to some embodiments of this disclosure, the hard mask 122 is a metallic hard mask formed of titanium nitride, boron nitride, or the like.

[0058] Figures 3 to 12 This describes a process for forming metal wires and through-holes according to some embodiments. It should be understood that, as... Figures 3 to 12 The examples shown illustrate a dual-damascene process. According to alternative embodiments, a single-damascene process is also contemplated, in which metal wires, through-holes, contact plugs, or the like are formed.

[0059] like Figure 3 and Figure 4 As shown, the through-hole opening 124 and the trench 126 are formed by etching. The individual processes are described as follows: Figure 15Process 206 in the process flow 200 shown in FIG. 2. The via openings 124 and the trenches 126 can be formed using, for example, lithography techniques. In an example of the formation process of the via openings 124 and the trenches 126, a bottom anti-reflective coating (BARC) layer 130 is formed on the patterned hardmask 122, and a patterned hardmask 132 is formed on the BARC layer 130. In one example, the BARC layer 130 includes an organic BARC material formed by a spin-on technique. The hardmask 132 is formed by patterning the hardmask layer to form openings 134 therein, where the openings 134 define the pattern of the via openings 124 to be filled to form vias. Through the openings 134, the BARC layer 130 is etched to form the via openings 124. As the via openings 124 extend downward in the etching process, the capping layer 121 and the dielectric layer 120 are then etched.

[0060] According to some embodiments of the present disclosure, a process gas including fluorine and carbon is used for the etching of the dielectric layer 120, where the fluorine is used for etching while the carbon has the effect of protecting the sidewalls of the resulting openings. With a proper ratio of fluorine and carbon, the via openings 124 can have a desirable profile. For example, the process gas used for etching includes fluorine- and carbon-containing gases such as C4F8, CH2F2, and / or CF4, and a carrier gas such as N2. In an example of the etching process, the flow rate of C4F8 is in a range between about 0 seem and about 50 seem, the flow rate of CF4 is in a range between about 0 seem and about 300 seem (with at least one of C4F8 having a non-zero flow rate), and the flow rate of N2 is in a range between about 0 seem and about 200 seem. According to an alternative embodiment, the process gas used for etching includes CH2F2 and a carrier gas such as N2. In an example of the etching process, the flow rate of CH2F2 is in a range between about 10 seem and about 200 seem, and the flow rate of N2 is in a range between about 50 seem and about 100 seem.

[0061] During the etching process, the semiconductor device 100 can be maintained at a temperature in a range between about 30 °C and about 60 °C. In the etching process, a plasma can be generated from the etching gas. The Radio Frequency (RF) power of the power source used for etching can be lower than about 700 Watts, and the pressure of the process gas is in a range between about 15 mTorr and about 30 mTorr.

[0062] The etching for forming the via openings 124 can be performed using a time- dependent pattern. As a result of the etching, the via openings 124 are formed to extend to an intermediate level between the top surface and the bottom surface of the dielectric layer 120. Next, the BARC layer 130 and the patterned hard mask 132 are removed, followed by further etching of the dielectric layer 120 using the patterned hard mask 122 as an etching mask. In the etching process, which is a non-isotropic etching process, the via openings 124 extend downward until the etch stop layer 118 is exposed. At the same time, the openings 124 extend downward, and the trenches 126 are formed to extend into the dielectric layer 120. The etch stop layer 118 is then etched with a suitable etchant, and the capping layer 117 is exposed at the bottom of the via openings 124. The resulting structure is illustrated in Figure 3 In the resulting structure, the via openings 124 are located below and connected to the trenches 126.

[0063] According to an alternative embodiment, the via openings 124 and the trenches 126 are formed in separate lithography processes. For example, in a first lithography process, the via openings 124 are formed to extend downward to the etch stop layer 118. In a second lithography process, the trenches 126 are formed. The order for forming the via openings 124 and the trenches 126 can also be reversed.

[0064] Next, referring to Figure 5 , a wet cleaning process is performed to clean residues from the via openings 124 and the trenches 126. The wet cleaning solution can include a suppressant for protecting the exposed portion of the capping layer 117, such as Co, from being undesirably etched when the capping layer 117 is exposed to the via openings 124, which results in the formation of the suppressant film 140. The respective process is illustrated as process 208 in the process flow 200 shown in Figure 15 The suppressant film 140 is thin and can have a thickness Tl in a range between about 1 nm to about 2 nm, although the thickness Tl can be greater or less. The thickness Tl is related to the type of suppressant. The suppressant film 140 can be a single layer of suppressant, such as a single layer of benzotriazole (BTA).

[0065] According to some embodiments, the suppressant includes benzotriazole (BTA). An example of the chemical structure of BTA includes a benzene ring and three hydrogen atoms attached to the benzene ring, which can be represented by the chemical formula C6H5N3.

[0066] According to other embodiments, the inhibitor is selected from other chemical species. These candidate inhibitor materials are hydrophobic and preferably contain non-polar groups. The hydrophobic nature and non-polar groups make the candidate inhibitor materials difficult to adsorb the precursor gases in subsequent deposition processes. The candidate inhibitor materials also have good chelation stability during wet clean and during subsequent deposition of barrier layers. In addition, the candidate inhibitor materials are removable during subsequent plasma unsealing processes, as will be discussed. For example, bis-triazolyl indole amine can also be used as an inhibitor. The benzo ring in bis-triazolyl indole amine also results in hydrophobic and steric hindrance properties.

[0067] As a result of adding the inhibitor to the wet clean solution, the inhibitor has a residue left on the exposed surface of the capping layer 117, resulting in the formation of an inhibitor film 140. For example, when the capping layer 117 includes Co, the Co atoms at the surface of the inhibitor film 140 bond to the nitrogen atoms in the BTA. The benzo ring of the BTA faces outward. Since the benzo ring cannot bond to other atoms, such as the Ta atoms and nitrogen atoms in the subsequently formed barrier layer, steric hindrance results.

[0068] Initially, the inhibitor film 140 can cover a major portion, but not all, of the exposed surface of the capping layer 117. To further increase the coverage, one way is to extend the time of the wet clean process. However, it is recognized that the extension of the wet clean time is limited by other factors. For example, extending the wet clean time too much can result in the corrosion of the capping layer 117. According to some embodiments of the present disclosure, the wet clean time is in the range of between about 50 seconds to about 100 seconds.

[0069] Reference is made to Figure 6 According to some embodiments of the present disclosure, to increase the coverage of the inhibitor film 140 without causing the aforementioned problems, an additional inhibitor film formation process is performed. The respective processes are illustrated as Figure 15Process 210 in process flow 200 shown in FIG. 2. In an example of the process, the semiconductor device 100 is removed from the wet clean solution and immersed in an inhibitor forming solution. Since the process is used to further grow the inhibitor film 140, rather than to etch the capping layer 117, the chemistry used for the wet clean is not included in the inhibitor forming solution. For example, the amine and H2O2may not be included. However, certain other chemicals such as ethylene glycol, dimethyl sulfide, etc. can be added to the inhibitor forming solution. An inhibitor such as BTA is added to the inhibitor forming solution, which can be the same or different from the inhibitor used in the wet clean solution. The semiconductor device 100 is then immersed in the inhibitor forming solution to further grow the inhibitor film 140 and increase the coverage of the inhibitor film 140. According to some embodiments of the disclosure, the immersion time is in the range of between about 30 seconds to about 60 seconds. After the immersion, the inhibitor film 140 can achieve 100% coverage as the thickness increases from T1to T2(T2>T1). In some embodiments, T2is at least 50% greater than T1. When the BTA used in the inhibitor forming solution is different from the BTA used in the wet clean solution, the further grown inhibitor film 140 can have a first layer of the first BTA with a thickness of T1and a second layer of the second BTA with a thickness of T2-T1. In various embodiments, the thickened inhibitor film 140 is still thinner than any of the barrier layer 110, the liner 112, or the etch stop layer 118. As will be discussed below, the inhibitor film 140 leaves room for a thin auxiliary liner to be formed therein, and the relatively small thickness of the inhibitor film 140 ensures that the auxiliary liner also has a small thickness, which makes the resulting structure similar to a bottom barrier layer without a via structure.

[0070] There can or can not be an inhibitor film 140 grown on the patterned hard mask 122. Also, when an inhibitor film 140 is grown on the patterned hard mask 122, its thickness is less than the thickness T2, and / or the coverage of the portion of the inhibitor film 140 on the patterned hard mask 122 is less than 100%, e.g., less than about 50%.

[0071] Next, referring to Figure 7 a conductive barrier layer 142 is deposited to line the via openings 124 and the trenches 126, e.g., using atomic layer deposition (ALD). The respective processes are illustrated as Figure 15Process 212 in process flow 200 shown in FIG. 2. Barrier layer 142 can be formed of a conductive material such as Ta, TaN, TaC, Ti, TiN, TiC, and other suitable materials, and has the function of preventing copper in a subsequently deposited copper-containing material from diffusing into dielectric layer 120. According to some embodiments of the present disclosure, barrier layer 142 comprises TaN formed using ALD. A corresponding ALD cycle includes introducing a Ta-containing process gas such as pentakis(dimethylamido) tantalum (C 10 H 30 N5Ta) into a respective ALD chamber, purging the Ta-containing process gas, introducing a nitrogen-containing process gas such as ammonia into the C4F8process chamber, and purging the nitrogen-containing process gas.

[0072] Inhibitor film 140 blocks or retards the growth of barrier layer 142 at the bottom of via opening 124. This is due to the steric hindrance of inhibitor film 140, and this steric hindrance is at least partially due to its heterocyclic structure. For example, on inhibitor film 140, there is a very small likelihood of a TaN molecule (assuming barrier layer 142 comprises TaN) growing on it during an ALD cycle, whereas on dielectric layer 120, a complete TaN layer grows during each ALD cycle. Thus, after one ALD cycle, a very small portion of the exposed surface of inhibitor film 140 has TaN grown on it, which acts as a seed for subsequent growth. Once TaN is grown, it will grow at the same rate as on dielectric layer 120. After each cycle, a very small additional area of inhibitor film 140 is covered by newly grown TaN. Thus, a large portion of inhibitor film 140 does not have TaN grown on it until after multiple ALD cycles. This effect is referred to as growth retardation (or incubation retardation) on inhibitor film 140, whereas there is no growth retardation on the sidewalls of dielectric layer 120, since inhibitor film 140 is not formed on dielectric layer 120.

[0073] Due to the growth retardation and random seeding of barrier layer 142 on inhibitor film 140, there can be substantially no barrier layer 142 grown on inhibitor film 140 after the formation of barrier layer 142 is complete. In other words, barrier layer 142 can not extend onto inhibitor film 140. A small amount of barrier layer 142 grown on inhibitor film 140 is possible, with a coverage less than 100% and greater than 0. According to some embodiments, barrier layer 142 forms discrete islands 142' on the surface of inhibitor film 140, with a random and irregular pattern, and a coverage less than about 20% of the exposed surface of inhibitor film 140.

[0074] Referring to Figure 8 For example, liner 144 is deposited on barrier layer 142 using ALD, and liner 144 lines via opening 124 and trench 126. The respective processes are described asFigure 15 Process 214 in process flow 200 shown. Liner 144 may be formed of a suitable metal, metal nitride, or metal carbide (such as Co, CoN, and RuN). For the purposes of some embodiments, lining 144 and lining 112 have the same material composition. For example, both lining 144 and lining 112 may be formed of Co. After forming lining 144, the thickness T3 of lining 144 may range from approximately to approximately

[0075] The inhibitor film 140 blocks or delays the growth of the liner 144 at the bottom of the via opening 124. This is due to the steric hindrance of the inhibitor film 140, which is at least partly due to its heterocyclic structure. For example, the likelihood of Co-containing material growing on the inhibitor film 140 during an ALD cycle (assuming the liner 144 includes Co) is extremely small, whereas a complete Co-containing material layer grows on the barrier layer 142 in each ALD cycle. Therefore, after one ALD cycle, a very small portion of the exposed surface of the inhibitor film 140 has Co-containing material grown on it, which acts as a seed for subsequent growth. Once the Co-containing material is grown, it will grow at the same rate as on the barrier layer 142. After each cycle, a very small additional region of the inhibitor film 140 is covered by newly grown Co-containing material. Therefore, most of the inhibitor film 140 does not have Co-containing material grown on it until after multiple ALD cycles. This effect is referred to as growth delay (or culture delay) on the inhibitor membrane 140, while there is no growth delay on the sidewall of the barrier layer 142, because the inhibitor membrane 140 is not formed on the barrier layer 142.

[0076] Due to growth delay and random seeding of the liner 144 on the inhibitor film 140, the liner 144 may substantially not exist on the inhibitor film 140 after its formation is complete. In other words, the liner 144 may not extend onto the inhibitor film 140. It is possible for a small amount of the liner 144 to grow on the inhibitor film 140, with a coverage area less than 100% and greater than 0. According to some embodiments, the liner 144 forms discrete island regions 144' on the surface of the inhibitor film 140, the discrete island regions 144' having a random and irregular pattern, and covering an area less than about 20% of the exposed surface of the inhibitor film 140. Also... Figure 8 As depicted, some discrete island regions 144' of the Co-containing material can overlap on the discrete island regions 142' of TaN from the barrier layer 142.

[0077] refer to Figure 9 Post-deposition treatment 150 is performed to remove the inhibitor film 140. Individual processes are described as follows: Figure 15Process 216 in process flow 200 shown in FIG. 2. Post-deposition treatment 150 can be performed via a plasma treatment. The process gas can include hydrogen (H2) and a carrier gas such as argon. During the plasma treatment, the temperature of semiconductor device 100 can be greater than about 200°C, for example in a range between about 200°C and about 300°C. The treatment duration can be in a range between about 30 seconds and about 60 seconds. The plasma treatment is also referred to as a plasma unpinning treatment. As a result of the post-deposition treatment, inhibitor film 140 is removed along with discrete island regions 142' and 144'. In post-deposition treatment 150, inhibitor film 140 is broken down into gases that are removed. With inhibitor film 48 removed, a gap 152 is formed between cap layer 117 and the end portions of barrier layer 142 and liner 144. The bottom portion of the sidewall of dielectric layer 120 is exposed by gap 152. An advantageous feature of performing a post-deposition treatment after depositing barrier layer 142 is that a high resistance barrier layer 142 will not be present at the bottom of via opening 124.

[0078] Reference is made to Figure 10 such as using ALD to conformally deposit an auxiliary liner 144' over liner 144, and auxiliary liner 144' lines via opening 124 and trench 126. The respective processes are described as Figure 15 Process 218 in process flow 200 shown in FIG. 2. Auxiliary liner 144' also fills gap 152. Auxiliary liner 144' covers the portion of the top surface of cap layer 117 that was exposed in via opening 124, and covers the portion of the sidewall of dielectric layer 120 that was exposed in gap 152. Auxiliary liner 144' can be formed of a suitable metal, metal nitride or metal carbide such as Co, CoN and RuN. To facilitate some embodiments, auxiliary liner 144' and liner 144 have the same material composition. For example, both auxiliary liner 144' and liner 144 can be formed of Co. The thickness of auxiliary liner 144' can be less than the thickness T3 of liner 144. In embodiments where auxiliary liner 144' and liner 144 are formed of the same conductive material, auxiliary liner 144' merges with liner 144, and equivalently, liner 144 is thickened to a thickness T4 that is greater than the initial thickness T3. In some embodiments, thickness T4 is greater than initial thickness T3 by about 30% to 80%. The thickened liner 144 helps reduce contact resistance. Further, in embodiments where auxiliary liner 144', liner 144 and cap layer 117 are made of the same material composition such as Co, the same material composition merges into a thicker conductive layer between the top surface of conductive feature 108 and the bottom of via opening 124, which helps further reduce contact resistance. By filling gap 152, liner 144 also separates barrier layer 142 from cap layer 117.

[0079] Reference is made to Figure 11A seed layer 154 is formed on the liner 144. The respective processes are illustrated as processes 220 in the process flow 200 shown in FIG. 2. Figure 15 In some embodiments, the seed layer 154 is a metal alloy layer containing at least a base metal element (e.g., copper (Cu)) and an additive metal element (e.g., manganese (Mn)). In one example, the seed layer 154 is a copper manganese (CuMn) layer. In other embodiments, Ti, Al, Nb, Cr, V, Y, Tc, Re, or the like can be used as an alternative additive metal for forming the seed layer 154. The additive metal element helps improve the device electromigration performance. In some embodiments, the concentration (atomic percent) of the additive metal element in the copper alloy layer can range from about 0.5% to about 5%. The concentration of the additive metal element in the contact structures at the lower metal layer level can be less than the concentration of the additive metal element in the contact structures at the higher metal layer level. In one example, the copper alloy used for the seed layer 154 and the seed layer 114 is CuMn, and the concentration of manganese in the lower seed layer 114 is less than the concentration of manganese in the upper seed layer 154, e.g., 1% less. This is because, although a higher concentration of the additive metal element further helps improve the electromigration performance, the contact resistance also increases due to the relatively lower resistance of the additive metal element. For conductive features formed in the lower metal layer level, the generally smaller metal line width and metal line spacing have already increased the metal resistance at the lower metal layer level, and thus a lower concentration of the additive metal element mitigates further increasing the metal resistance. For conductive features formed in the higher metal layer level, the generally larger metal line width and metal line spacing accommodate a larger concentration of the additive metal element without as much concern of degrading the metal resistance. The seed layer 154 can be deposited by using ALD, CVD, ELD, PVD, or other suitable deposition techniques.

[0080] Referring to Figure 12 A conductive material 156 is deposited to fill the via openings 124 and the trenches 126. The respective processes are illustrated as processes 222 in the process flow 200 shown in FIG. 2. Figure 15 The processes shown in Figure 11 and Figure 12 may be performed in-situ in the same vacuum environment without vacuum interruption. Figures 7 to 10 A portion or all of the deposition processes in Figure 11 and Figure 12The process shown is performed in situ in the same vacuum environment without vacuum interruption. According to some embodiments, the seed layer 154 comprises blanket deposition using physical vapor deposition (PVD) and filling the remaining portions of the via openings 124 and trenches 126 using, for example, electroplating. Planarization processes such as chemical mechanical planarization (CMP) or mechanical polishing can be performed to remove excess portions of the conductive material 156, thus forming the vias 164 and metal lines 166, as... Figure 13 As shown in the image.

[0081] Due to the selective formation of the barrier layer 142, the barrier layer 142 includes a portion that contacts the dielectric layer 120 to perform a diffusion-blocking function, and does not have a portion that separates the bottom portion of the liner 144 (auxiliary liner 144') located at the bottom of the via 164 from the capping layer 117. Since the resistivity of the barrier layer 142 is significantly higher than that of the conductive material 156 (e.g., two to four orders of magnitude higher), not forming the barrier layer 142 at the interface with the underlying contact structure significantly reduces the contact resistance of the via 164.

[0082] Figure 14 The formation of capping layer 167 and etch stop layer 168 is also explained. Capping layer 167 is deposited on conductive material 156. Individual processes are described as follows: Figure 15 Process 224 in the process flow 200 shown. In some embodiments, the CMP process performed before removing excess portions of the conductive material 156 also slightly recesses the top surfaces of the conductive material 156 and the seed layer 154. A capping layer 167 is deposited on the recessed top surfaces of the conductive material 156 and the seed layer 154. A liner 144 may surround the capping layer 167 and separate the capping layer 167 from the barrier layer 142. To facilitate some embodiments, the top surfaces of the barrier layer 142, the liner 144, and the capping layer 167 may be substantially coplanar. In some other embodiments, the CMP process also recesses the liner 144 such that the capping layer 167 covers the top surfaces of the liner 144, the seed layer 154, and the conductive material 156. Thus, the capping layer 167 may physically contact the barrier layer 142.

[0083] According to some embodiments of the present disclosure, the capping layer 167 is formed of a conductive material, which can include but is not limited to a metal, a metal nitride, or a metal carbide. In some implementations, the capping layer 167 can be formed of Co, CoN, RuN, or a combination thereof. To facilitate some embodiments, the capping layer 167 and the liner 144 have the same material composition. For example, both the capping layer 167 and the liner 144 can be formed of Co. The etch stop layer 168 covers and contacts the dielectric layer 120 and the metal line 166. The etch stop layer 168 is formed of a material having a high etch selectivity with respect to an overlying dielectric layer (not shown) to be formed later.

[0084] Referring back to Figure 1 As discussed above, according to some embodiments of the present disclosure, metal lines at higher metal layer levels (and the respective vias directly underneath the metal lines) can have a higher concentration of the additive metal element (e.g., manganese). For example, the manganese concentration at the Mtop level can be about 3% to about 5% higher than the manganese concentration at the Ml level, and is graded for the metal layer levels in between. In some other embodiments, according to some embodiments of the present disclosure, metal lines at metal layer levels having a larger metal line pitch can have a higher concentration of the additive metal element (e.g., manganese). For example, if the M2 level and the M3 level have the same metal line pitch (which is larger than the metal line pitch at the Ml level and smaller than the metal line pitch at the M4 level), the manganese concentration at the M2 level and the M3 level can be substantially the same, which is larger than the manganese concentration at the Ml level and smaller than the manganese concentration at the M4 level.

[0085] Embodiments of the present disclosure have some advantageous features. By forming the conductive barrier layer after forming the inhibitor film, since the growth of the inhibitor film is selective on different materials, the resulting conductive barrier layer is selectively formed on the sidewalls of the low-k dielectric layer for the diffusion barrier function, but not formed on the underlying conductive regions to cause an increase in the resistance of the via contact.

[0086] In one illustrative aspect, the disclosure features a method of manufacturing a semiconductor device. The method includes forming a conductive cap layer over a conductive feature; forming a dielectric layer over the conductive cap layer; forming an opening in the dielectric layer to expose a top surface of the conductive cap layer; forming an inhibitor film at the top surface of the conductive cap layer; depositing a barrier layer on sidewalls of the opening; removing the inhibitor film to expose the top surface of the conductive cap layer; depositing an auxiliary liner on the barrier layer and the top surface of the conductive cap layer; and depositing a conductive material on the auxiliary liner and filling the opening. In some embodiments, the inhibitor film includes benzotriazole (BTA). In some embodiments, during deposition of the barrier layer, the inhibitor film retards growth of the barrier layer on the inhibitor film. In some embodiments, during deposition of the barrier layer, the barrier layer forms isolated islands on the inhibitor film. In some embodiments, the conductive cap layer includes Co. In some embodiments, the conductive cap layer and the auxiliary liner include the same material composition. In some embodiments, the method also includes, after deposition of the barrier layer and before removal of the inhibitor film, depositing a liner on the barrier layer, the liner being stacked between the barrier layer and the auxiliary liner. In some embodiments, the auxiliary liner and the liner include the same material composition. In some embodiments, during deposition of the liner, the inhibitor film retards growth of the liner on the inhibitor film. In some embodiments, the method also includes, after deposition of the auxiliary liner and before deposition of the conductive material, depositing a first seed layer. The first seed layer includes an additive metal element having a first concentration, the conductive feature includes a second seed layer, the second seed layer includes the additive metal element having a second concentration, and the first concentration is greater than the second concentration. In some embodiments, forming the inhibitor film includes forming an initial inhibitor layer in a first solution, the initial inhibitor layer partially covering the top surface of the conductive cap layer; and expanding and thickening the initial inhibitor layer to form the inhibitor film in a second solution different from the first solution, the inhibitor film completely covering the top surface of the conductive cap layer.

[0087] In another illustrative aspect, the disclosure features a method of forming a semiconductor structure. The method includes forming a first dielectric layer; forming a first opening in the first dielectric layer; depositing a first seed layer in the first opening, the first seed layer including a main metal element and an additive metal element; depositing a first conductive material to fill the first opening; forming a second dielectric layer over the first dielectric layer; forming a second opening in the second dielectric layer; depositing a second seed layer in the second opening, the second seed layer including the main metal element and the additive metal element; and depositing a second conductive material to fill the second opening. The additive metal element has a first concentration in the first seed layer and a second concentration in the second seed layer, and the second concentration is greater than the first concentration. In some embodiments, the main metal element is copper, and the additive metal element is manganese. In some embodiments, each of the first concentration and the second concentration ranges from about 0.5% to about 5%. In some embodiments, the method also includes, after depositing the first conductive material and before forming the second dielectric layer, depositing a conductive cap layer on the first conductive material. After depositing the second conductive material, the conductive cap layer is vertically between the first conductive material and the second seed layer. In some embodiments, the method also includes, after forming the second opening, depositing an inhibitor film on a bottom of the second opening; depositing a barrier layer on sidewalls of the second opening, but not on the inhibitor film; and, before depositing the second conductive material, removing the inhibitor film from the second opening. In some embodiments, removing the inhibitor film exposes sidewalls of the second dielectric layer in the second opening.

[0088] In yet another illustrative aspect, the disclosure features an interconnect structure. The interconnect structure includes a first conductive feature in a first dielectric layer, a conductive cap layer over the first conductive feature, a second dielectric layer over an etch stop layer, and a second conductive feature extending through the second dielectric layer. The second conductive feature includes a barrier layer on sidewalls of the second dielectric layer, a liner on the barrier layer and in physical contact with the conductive cap layer, a seed layer on the liner, and a conductive fill layer on the seed layer. In some embodiments, the liner separates the barrier layer from the conductive cap layer. In some embodiments, the seed layer is a first seed layer including a first concentration of an additive metal element, the first conductive feature includes a second seed layer including a second concentration of the additive metal element, and the first concentration is higher than the second concentration.

[0089] In yet another illustrative aspect, the disclosure features an interconnect structure. The interconnect structure includes a first conductive feature, a second dielectric layer, a second conductive feature, and an auxiliary liner. The first conductive feature is located in a first dielectric layer, where the first conductive feature includes a seed layer, a first metal fill layer located above the seed layer, and a conductive cap layer located above the first metal fill layer. The second dielectric layer is located above the first dielectric layer. The second conductive feature extends through the second dielectric layer, where the second conductive feature includes a barrier layer and a second metal fill layer located above the barrier layer. The auxiliary liner is located between the conductive cap layer and the barrier layer, where the auxiliary liner includes cobalt. In some embodiments, the conductive cap layer and the auxiliary liner comprise a same material composition. In some embodiments, the seed layer is a metal alloy layer including a primary metal element and an additive metal element. In some embodiments, the seed layer is a copper-manganese layer. In some embodiments, the additive metal element of the seed layer is titanium, aluminum, niobium, chromium, vanadium, yttrium, technetium, or rhenium. In some embodiments, the atomic percentage of the additive metal element in the primary metal element ranges from 0.5% to 5%.

[0090] In yet another illustrative aspect, the disclosure features an interconnect structure. The interconnect structure includes a first conductive feature, a second dielectric layer, and a second conductive feature. The first conductive feature is located in a first dielectric layer. The second dielectric layer is located above the first dielectric layer. The second conductive feature extends through the second dielectric layer, where the second conductive feature includes a seed layer and a metal fill layer located above the seed layer. The seed layer is a metal alloy layer including a primary metal element and an additive metal element.

[0091] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the various aspects of the disclosure. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that changes can be made in the present disclosure without departing from the spirit and scope of the same.

Claims

1. An interconnect structure, characterized by, Comprising: a first conductive feature in a first dielectric layer, wherein the first conductive feature comprises: a seed layer; a first metal fill layer over the seed layer; and a conductive cap layer over the first metal fill layer; a second dielectric layer over the first dielectric layer; a second conductive feature extending through the second dielectric layer, wherein the second conductive feature comprises a barrier layer and a second metal fill layer over the barrier layer; and a supplemental liner between the conductive cap layer and the barrier layer, wherein the supplemental liner comprises cobalt.

2. The interconnect structure of claim 1, wherein, wherein the conductive cap layer covers a top surface of the seed layer and a top surface of the first metal fill layer.

3. The interconnect structure of claim 1, wherein, Further comprising: a liner on a sidewall of the barrier layer.

4. The interconnect structure of claim 3, wherein, wherein the seed layer is a copper-manganese layer.

5. The interconnect structure of claim 3, wherein, Further comprising: an etch stop layer over the first dielectric layer and the first conductive feature, wherein the etch stop layer has a greater thickness than the supplemental liner.

6. The interconnect structure of claim 3, wherein, wherein a thickness of the supplemental liner is less than a thickness of the liner.

7. An interconnect structure, characterized by Comprising: a first conductive feature in a first dielectric layer, wherein the first conductive feature comprises a conductive cap layer; a second dielectric layer over the first dielectric layer; and a second conductive feature extending through the second dielectric layer, wherein the second conductive feature comprises: a seed layer; a barrier layer over the seed layer and a metal fill layer over the barrier layer; and a supplemental liner between the conductive cap layer and the barrier layer.

8. An interconnect structure, characterized by Comprising: a first conductive feature in a first dielectric layer; a conductive cap layer over the first conductive feature; a second dielectric layer over the etch stop layer; and a second conductive feature extending through the second dielectric layer, wherein the second conductive feature includes: a barrier layer on sidewalls of the second dielectric layer, a supplemental liner on the barrier layer and in physical contact with the conductive cap layer, wherein the supplemental liner is between the conductive cap layer and the barrier layer, a seed layer on the liner, and a conductive fill layer on the seed layer.

9. The interconnect structure of claim 8, wherein, wherein the supplemental liner separates the barrier layer from the conductive cap layer.

10. The interconnect structure of claim 8, wherein, wherein the supplemental liner contacts a bottom surface of the barrier layer.

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