Interconnection structure

Abstract

Embodiments of the present disclosure provide an interconnect structure including a molybdenum via through a dielectric layer and a molybdenum cap over the molybdenum via, where the molybdenum cap has a thickness of at least 2 nanometers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to interconnect structures. BACKGROUND

[0002] Integrated circuits are formed on semiconductor wafers. A photolithography patterning process uses ultraviolet light to transfer a desired mask pattern to photoresist on a semiconductor wafer. An etching process can then be used to transfer the pattern to a layer underneath the photoresist. This process is repeated multiple times using different patterns to build different layers on the wafer substrate and to fabricate functional devices. Thin film resistors can be fabricated as part of such integrated circuits. SUMMARY

[0003] According to some embodiments of the disclosure, an interconnect structure includes a molybdenum via through a dielectric layer and a molybdenum cap on the molybdenum via, wherein the molybdenum cap has a thickness of at least 2 nanometers.

[0004] According to some embodiments of the disclosure, an interconnect structure includes one or more bottom vias in a first dielectric layer, a via in a second dielectric layer above the first dielectric layer and contacting the bottom vias, a molybdenum cap on the via and having a thickness of 2 nanometers to 40 nanometers, and a top via in a third dielectric layer above the second dielectric layer and electrically connected to the molybdenum cap.

[0005] According to some embodiments of the disclosure, an interconnect structure includes a molybdenum via through a dielectric layer and a molybdenum cap on an upper surface of the dielectric layer, wherein the molybdenum cap contacts the molybdenum via and has a dome. The interconnect structure further includes a top via on the molybdenum cap, wherein the top via contacts the dome of the molybdenum cap. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can best be understood with reference to the following detailed description when read with the accompanying drawings in which, according to common method in the industry, the various features are not drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] FIG. 1A is a cross-sectional view of a first exemplary embodiment of an interconnect structure according to some embodiments;

[0008] FIG. 1B is a cross-sectional view of an interconnect structure of FIG. 1A , in which additional details of various components are illustrated;

[0009] FIG. 1C is a cross-sectional view of an interconnect structure of FIG. 1A , in which additional details of various components are illustrated;

[0010] FIG. 2is a flowchart of a method of forming a resistor structure according to some embodiments; FIG. 3 to FIG. 11 The plurality of steps of the method are shown in;

[0011] FIG. 3 is a cross-sectional view after patterning the first dielectric layer to form a bottom via;

[0012] FIG. 4 is a cross-sectional view after patterning the dielectric layer to form at least one via opening;

[0013] FIG. 5 is a cross-sectional view after filling the via opening with a conductive material;

[0014] FIG. 6 is a cross-sectional view after planarizing the conductive material;

[0015] FIG. 7 is a cross-sectional view after adding an etch stop layer, another dielectric layer, and a hardmask layer;

[0016] FIG. 8 is a cross-sectional view after patterning to expose the via through gaps in the hardmask layer;

[0017] FIG. 9 is a cross-sectional view after selectively depositing a molybdenum cap on the via;

[0018] FIG. 10 is a cross-sectional view after depositing a barrier diffusion liner;

[0019] FIG. 11 is a cross-sectional view after depositing a conductive material on the molybdenum cap.

[0020]

Symbolic Representation

[0021] 100: semiconductor package

[0022] 102: semiconductor die

[0023] 104: substrate

[0024] 106: layer

[0025] 108: interconnect structure

[0026] 110: first dielectric layer

[0027] 112: lower surface

[0028] 114: upper surface

[0029] 115: depth

[0030] 120: first etch stop layer

[0031] 121: thickness

[0032] 124: second dielectric layer

[0033] 125: thickness

[0034] 126: lower surface

[0035] 127: upper surface

[0036] 128: second etch stop layer

[0037] 129: thickness

[0038] 130: third dielectric layer

[0039] 131: thickness

[0040] 132: gap

[0041] 133: width

[0042] 135: width

[0043] 140: hard mask layer

[0044] 142: window

[0045] 143: width

[0046] 144: window

[0047] 145: width

[0048] 150: bottom via

[0049] 153: lower width

[0050] 155: upper width

[0051] 160: via

[0052] 161: thickness

[0053] 163: width

[0054] 164: via opening

[0055] 166: cap

[0056] 167: thickness

[0057] 169: width

[0058] 170: via

[0059] 171: thickness

[0060] 173: width

[0061] 174: via opening

[0062] 176: cap

[0063] 177: thickness

[0064] 179: width

[0065] 180: diffusion barrier layer

[0066] 181: width

[0067] 190: top via opening 191: thickness

[0068] 192: top via

[0069] 193: width

[0070] 194: top via

[0071] 195: width

[0072] 196: conductive material

[0073] 200: method

[0074] 205, 210, 215, 218, 220, 225, 230, 235, 240, 245, 250, 255, 260, 265, 270, 275, 280: step DETAILED DESCRIPTION

[0075] To implement different features of the subject matter recited, the following disclosure provides numerous different embodiments or examples. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature can include embodiments in which the first feature and second feature are formed directly contacting one another, and can also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and second feature can not directly contact one another. Additionally, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0076] In addition, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, can be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0077] Numerical values in the specification and claims of this disclosure should be understood to include any and all equivalents, whether expressed as a number or not. All ranges disclosed herein are inclusive of the endpoints and the endpoints are combinable with the ranges between them. All ranges disclosed herein are inclusive of the endpoints and the endpoints are combinable with the ranges between them.

[0078] The term "about" can be used to include any numerical value, either absolute or relative, that when used in connection with a value, indicates that the value, arbitrarily, excludes minor variations of the value. When used in connection with a range, the term "about" can indicate that both endpoints are approximations, e.g., "about 2 to about 4" also discloses the range "2 to 4." The term "about" can mean plus or minus 10% of the indicated value.

[0079] Some embodiments of the disclosure are directed to structures composed of different layers. When the terms "on" or "over" or "above" are used in reference to two different layers (including a substrate), they are used only to indicate that one layer is on or over the other layer. These terms do not require that the two layers be in direct contact with each other, and other layers can be positioned between the two layers. For example, all layers of a structure can be considered to be "on" a substrate, even if the layers are not all in direct contact with the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other without any layers between the two.

[0080] The terms "semiconductor die," "wafer," or "micro-wafer" can be used interchangeably in some embodiments of the disclosure to refer to a combination of a substrate and multiple layers on the substrate that form one or more integrated circuits.

[0081] The term "semiconductor package" is used in some embodiments of the disclosure to refer to a combination of a semiconductor die and an interconnect layer. Examples of interconnect layers can include a redistribution layer (RDL) or an interposer with under bumping, C4 bumps, or pillars. Thus, a semiconductor package can have an interconnect layer on only one side or on both sides. It is noted that the term "package" is used in the art to refer to many different structures and does not have a single, fixed definition.

[0082] Some embodiments of the present disclosure are directed to methods of reducing the overall interconnect resistance of an interconnect structure in an interconnect layer that allows a semiconductor die to communicate with one or more other semiconductor packages. Resistance increases as device size decreases due to increased electron scattering. One solution to reduce resistance includes increasing the contact area of a via in the interconnect structure without changing the critical dimension (CD) of the via. However, applying a cap on the via also affects the gapfill window used in the subsequent step of applying interconnect metal on the cap due to the material forming the cap also being deposited on the mask and reducing the width of the window. Since the interconnect metal is typically applied using a conformal deposition process, the interconnect metal around the cap naturally forms undesirable voids when it fuses together. Generally, smaller critical dimensions result in a higher risk of void formation. In the methods of some embodiments of the present disclosure, the material used to form the molybdenum cap on the molybdenum via does not deposit on the mask, resulting in no reduction in the width of the gapfill window. Thus, the contact area of the via can be maximized to reduce resistance without increasing the risk of void formation.

[0083] According to some embodiments, FIG. 1A is an X-axis cross-sectional view of a first exemplary embodiment of an interconnect structure. The interconnect structure is part of an overall semiconductor package and is disclosed herein as being fabricated during a middle-end-of-line (MEOL) process, which is when local electrical connections are made between transistors of a semiconductor die. However, the process steps described herein can also be applied to fabricate an interconnect structure during a back-end-of-line (BEOL) process, in which multiple semiconductor dies are interconnected to form a desired electronic circuit.

[0084] In an initial process, a semiconductor package 100 includes a semiconductor die 102 on which an interconnect structure is to be built. The die includes a substrate 104 and multiple layers of integrated circuitry formed on the substrate 104, which are shown as one layer 106 in the figures.

[0085] In particular embodiments, the substrate is a wafer formed of a semiconductor material. Such a semiconductor material can include silicon, for example in the form of crystalline silicon. In alternative embodiments, the substrate can be formed of other elemental semiconductors, for example germanium, or can include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbon, gallium arsenide phosphide, or indium gallium arsenide phosphide. In particular embodiments, the wafer substrate is silicon.

[0086] Different patterns of conductive materials and electrically insulating materials establish integrated circuits to form useful components. Suitable examples of integrated circuit components can include, for example but not limited to, active components (such as transistors), passive components (such as capacitors, inductors, resistors, and the like), or combinations of the above. These components can be formed of conductive materials such as metals like copper, aluminum, gold, tungsten, iron, ruthenium, iridium, and alloys of the above. Suitable examples of electrically insulating materials (i.e., dielectric materials) can include oxides such as silicon dioxide (SiO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium dioxide (ZrO2), or hafnium dioxide (HfO2); nitrides such as silicon carbonitride (SiCN), silicon nitride (SiN), hafnium oxynitride (HfO x N y ), zirconium oxynitride (ZrO x N y ), or silicon oxynitride (SiO x N y ), where 0 < x ≤ 1, 0 < y ≤ 1; silicates such as hafnium silicate (HfSi x O y ), or zirconium silicate (ZrSi x O y ), where x 0 < x ≤ 1, 0 < y ≤ 1; polysilicon, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), high-stress undoped silicate glass (HSUSG), borosilicate glass (BSG), high-k dielectric materials, or low-k dielectric materials.

[0087] Subsequently, the interconnect structure 108 includes a first dielectric layer 110 and a second dielectric layer 124, where a first etch stop layer 120 separates the two dielectric layers. The two dielectric layers can be independently regarded as an intermetal dielectric (IMD) or an interlayer dielectric (ILD). The first dielectric layer 110 can also be regarded as a pre-metal dielectric (PMD). These two dielectric layers can be located at any level of the interconnect layer above the semiconductor die

[0087] 102. The first dielectric layer includes a lower surface 112 and an upper surface 114, where the lower surface 112 is closer to the semiconductor die <00002 29>102 than the upper surface 114.

[0088] Bottom vias 150 extend through the first dielectric layer 110 between the lower surface 112 and the upper surface 114. As depicted in the figures, there can be four such bottom vias 150. Notably, each bottom via can be in the form of a trench extending along the Y-axis and thus not visible in the orientation of the figures.

[0089] A second dielectric layer 124 is above the first dielectric layer 110 and also includes a lower surface 126 and an upper surface 127. Vias 160, vias 170 (indicated in dashed lines) also extend through the second dielectric layer 124 and the first etch stop layer 120 to contact the bottom vias 150. Narrow vias 160 and wide vias 170 are depicted in the figures. The narrow vias 160 contact only one bottom via 150, while the wide vias 170 contact two or more bottom vias 150. Each via also includes a cap 166, 176 placed over the upper surface 127 of the second dielectric layer 124.

[0090] A second etch stop layer 128 is above the second dielectric layer 124, and a third dielectric layer 130 is above the second etch stop layer 128. A gap 132 is in the third dielectric layer 130 and the second etch stop layer 128 above the vias 160, 170 and the caps 166, 176 of the vias. A diffusion barrier layer 180 is present to separate the third dielectric layer 130 from the caps 166, 176. Top vias 192, 194 are in the gap 132 above the vias 160, 170. The vias 160, 170 electrically connect one or more bottom vias 150 to the top vias 192, 194. Notably, each top via can be in the form of a trench extending along the Y-axis and thus not visible in the orientation of the figures.

[0091] FIG. 1B And FIG. 1C Additional details are provided regarding the dimensions of the various components of the interconnect structure.

[0092] Referring first to FIG. 1B In some embodiments, the first dielectric layer 110 has a thickness or depth 115 of about 5 nanometers (nm) to about 50 nanometers. Thus, each bottom via 150 can also have a height or thickness of about 5 nanometers to about 50 nanometers. As indicated in the figures, each bottom via 150 has a lower width 153 at the lower surface 112 and an upper width 155 at the upper surface 114. In particular embodiments, the upper width 155 is greater than the lower width 153. In particular embodiments, the upper width 155 is about 5 nanometers to about 30 nanometers. In particular embodiments, the lower width 153 is about 4 nanometers to about 10 nanometers. In more particular embodiments, the difference between the upper width and the lower width is about 1 nanometer to about 26 nanometers. Other values and ranges for each of these measurements are also within the scope of the present disclosure.

[0093] In some embodiments, the first etch stop layer 120 has a thickness 121 of about 3 nanometers to about 30 nanometers. In some embodiments, the second dielectric layer 124 has a thickness 125 of about 2 nanometers to about 40 nanometers. Other values and ranges for each of these measurements are within the scope of the present disclosure.

[0094] The vias 160, 170 extend through the first etch stop layer 120 and the second dielectric layer 124. In some embodiments, each via 160, 170 has a height or thickness 161, 171 of about 5 nanometers to about 40 nanometers. Each via 160, 170 also has a width 163, 173, where the width 163, 173 is generally uniform throughout the thickness of the second dielectric layer 124. Generally, the via width can be about 4 nanometers to about 200 nanometers. For example, the width 163 of a narrow via 160 can be about 4 nanometers to about 20 nanometers. As another example, the width 173 of a wide via 170 can be about 25 nanometers to about 200 nanometers. As illustrated in the figures, a wide via 170 contacts two or more bottom vias 150. In some embodiments, the width 163 of a narrow via 160 is less than the upper width 155 of a bottom via 150, but this is not required. Embodiments also include a width 163 of a narrow via 160 that is equal to or greater than the upper width 155 of a bottom via 150. Other values and ranges for each of these measurements are within the scope of the present disclosure.

[0095] In some embodiments, the second etch stop layer 128 has a thickness 129 of about 3 nanometers to about 30 nanometers. In some embodiments, the third dielectric layer 130 has a thickness 131 of about 2 nanometers to about 40 nanometers. Other values and ranges for each of these measurements are within the scope of the present disclosure.

[0096] Referring now to the top vias 192, 194, these top vias are formed within the gaps 132 in the third dielectric layer 130 and the second etch stop layer 128. Generally, the width of the gap can be about 10 nanometers to about 1000 nanometers. For example, the width 133 of a gap 132 exposing a narrow via 160 can be about 10 nanometers to about 30 nanometers. As another example, the width 135 of a gap 132 exposing a wide via 170 can be about 30 nanometers to about 1000 nanometers. Other values and ranges for each of these measurements are within the scope of the present disclosure.

[0097] Referring now to a higher magnification view of a portion of the structure FIG. 1CEach of the caps 166, 176 has a height or thickness 167, 177. In certain embodiments, the cap thickness 167, 177 is at least 2 nanometers. In more certain embodiments, the cap thickness can be from 2 nanometers to about 40 nanometers, from about 5 nanometers to about 40 nanometers, or from about 10 nanometers to about 40 nanometers. Each of the caps 166, 176 also has a width 169, 179, where the width measurement is taken at the base of the cap where it contacts the via. In general, the cap width can be from about 4 nanometers to about 1000 nanometers. For example, the width 169 of the narrow cap 166 can be from about 4 nanometers to about 30 nanometers. As another example, the width 179 of the wide cap 176 can be from about 30 nanometers to about 1000 nanometers. Other values and ranges for each of these measurements are within the scope of the disclosure.

[0098] The cap width 169, 179 is generally greater than the via 160, 170 width 163, 173, but need not be. In certain embodiments, the difference between the cap width 169, 179 and the via width 163, 173 is from about 5 nanometers to about 800 nanometers, or from about 5 nanometers to about 25 nanometers. Other values and ranges for each of these measurements are within the scope of the disclosure.

[0099] The diffusion barrier layer 180 is on the sidewalls of each of the gaps 132. In certain embodiments, the diffusion barrier layer 180 has a width 181 of from about 0.5 nanometers to about 4 nanometers. Other values and ranges are also possible within the scope of the disclosure.

[0100] The top vias 192, 194 extend through the second etch stop layer 128 and the third dielectric layer 130. In some embodiments, each of the top vias 192, 194 has a height or thickness 191 of from about 5 nanometers to about 40 nanometers. The width 193, 195 of the top vias 192, 194 corresponds to the width of the gap minus the width of the diffusion barrier layer and any additional layers that can be added on top of the cap 166, 176. Other values and ranges for each of these measurements are within the scope of the disclosure.

[0101] According to some embodiments of the disclosure, FIG. 2 A flow diagram of a method 200 of forming an interconnect structure is illustrated. Some of the steps of the method are also illustrated in FIG. 3 to FIG. 11 The figures provide different views to better understand. While the method steps are discussed below to form an interconnect structure with two vias 160, 170, the discussion can be interpreted broadly to apply to forming only one via or to forming multiple vias at the same time. The method steps can be used during a middle-of-line process or a back-end-of-line process.

[0102] It is noted that certain known steps are not explicitly described in the following discussion. For example, a pattern / structure can be formed in a given layer by applying a photoresist layer, patterning the photoresist layer, developing the photoresist layer, and then etching.

[0103] Generally, applying a photoresist layer can be performed by, for example, spin coating or spraying, roller coating, dip coating, or extrusion coating. Generally, in spin coating, the substrate is placed on a spin platform, which can include a vacuum chuck that holds the substrate in the platform. Then, a photoresist composition is applied to the center of the substrate. The spin platform is then increased in speed to spread the photoresist uniformly from the center of the substrate to the edge of the substrate. The speed of the platform is then fixed, which can control the thickness of the final photoresist layer.

[0104] Next, the photoresist composition is baked or cured to remove solvents and harden the photoresist layer. In some particular embodiments, the baking temperature is about 90 °C to about 110 °C. The baking can be performed using a hot plate, an oven, or similar equipment. Thus, a photoresist layer is formed on the substrate.

[0105] Next, the photoresist layer is exposed to radiation to pattern the photoresist layer. The radiation can be any wavelength of light that carries the desired mask pattern. In particular embodiments, extreme ultraviolet (EUV) light having a wavelength of about 13.5 nm is used for patterning, thus allowing for smaller feature sizes. This results in a portion of the photoresist layer being exposed to the radiation, and a portion of the photoresist not being exposed to the radiation. Such exposure results in a portion of the photoresist becoming soluble in a developer, and other portions of the photoresist remaining insoluble in the developer.

[0106] An additional photoresist baking step (post exposure bake (PEB)) can occur after exposure to the radiation. For example, post exposure bake can help to release acid leaving groups (ALGs) or other molecules important in chemical amplification photoresists.

[0107] The photoresist layer can then be developed using a developer. The developer can be an aqueous or organic solution. During the development step, soluble portions of the photoresist layer are dissolved and washed away, thus leaving behind a photoresist pattern. One example of a common developer is an aqueous solution of tetramethylammonium hydroxide (TMAH). Other developers can include 2-heptanone, n-butyl acetate, isoamyl acetate, cyclohexanone, 5-methyl-2-hexanone, methyl-2-hydroxyisobutyrate, ethyl lactate, or propyleneglycol monomethyl ether acetate, n-pentyl acetate, n-butyl propionate, n-hexyl acetate, n-butyl butyrate, isobutyl butyrate, 2,5-dimethyl-4-hexanone, 2,6-dimethyl-4-heptanone, propyl isobutyrate, or isobutyl propionate. In general, any suitable developer can be used. At times, a post- development bake or hard bake can be performed after development to stabilize the photoresist pattern, thus optimizing performance in subsequent steps.

[0108] In succession, portions of the underlying layer that are now exposed by the patterned photoresist layer. The etching step transfers the photoresist pattern to the underlying layer that is patterned. After use of the patterned photoresist layer, the patterned photoresist layer can be removed, for example using solvents such as N-methyl-pyrrolidone (NMP), alkaline media, or other strippers at elevated temperature, or by dry etching using an oxygen plasma.

[0109] Generally, any etching step herein can be performed using wet etching, dry etching, plasma etching processes such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or a combination thereof as appropriate. The etching can be anisotropic. Depending on the material, the etchant can include carbon tetrafluoride (CF4), hexafluoroethane (C2F6), octafluoropropane (C3F8), difluoromethane (CH2F2), fluoromethane (CH3F), trifluoromethane (CHF3), carbon fluoride, nitrogen (N2), hydrogen (H2), oxygen (O2), argon (Ar), xenon (Xe), xenon difluoride (XeF2), helium (He), carbon monoxide (CO), carbon dioxide (CO2), fluorine (F2), chlorine (Cl2), hydrogen bromide (HBr), hydrofluoric acid (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), boron trichloride (BC13), ammonia (NH3), bromine (Br2), nitrogen trifluoride (NF3), the like, or a combination thereof in various proportions. For example, silicon dioxide can be wet etched using hydrofluoric acid and ammonium fluoride. Alternatively, silicon dioxide can be dry etched using a mixture of CHF3, O2, CF4, and / or H2.

[0110] Planarization can be performed to obtain a planar surface. Planarization can be performed, for example, using a chemical mechanical polishing (CMP) process. Generally, chemical mechanical polishing is performed using a rotating platform with an attached polishing pad. The substrate is attached to a rotating carrier. A slurry or solution containing a plurality of chemicals and abrasives is spread on the polishing pad or wafer substrate. During polishing, both the polishing pad and the carrier are rotated, causing mechanical and chemical effects on the surface of the wafer substrate and / or top layers on the wafer substrate, removing undesired material and creating a highly planar surface. A post-CMP cleaning step is then performed using a rotating scrubber brush and cleaning fluid to clean one or both sides of the wafer substrate.

[0111] Finally, cleaning steps such as wet cleaning can be performed between process steps. The cleaning fluid depends on the etch recipe and exposed layers. Cleaning fluid examples can include deionized water, dilute hydrofluoric acid, and other known solutions.

[0112] The methods and systems of some embodiments of the present disclosure include a number of different dielectric layers. These dielectric layers can generally be formed from any suitable dielectric material combination, but the properties of any particular layer can be further defined. Dielectric material examples can include silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), hafnium oxide (HfOx ) Zirconium dioxide (ZrO2), aluminum oxide (Al2O3), aluminum nitride (AlN), silicon carbonitride (SiC x N y ) silicon oxycarbide (SiC x O y ) silicon oxynitride (SiO x N y ) hafnium oxynitride (HfO x N y ) zirconium oxynitride (ZrO x N y ) hafnium silicate (ZrSi x O y ) zirconium silicate (ZrSi x O y ) or silicon carbon oxynitride (SiC x O y N z ) or hexagonal boron nitride (hBN), where 0 < x, y, z ≤ 1 and x + y + z = 1. Other dielectric materials may include tantalum oxide (Ta2O5), nitrides such as silicon nitride, polysilicon, phosphosilicate glass, fluorosilicate glass, undoped silicate glass, high-stress undoped silicate glass, and borosilicate glass. Low dielectric constant dielectric materials typically have a dielectric constant equal to or lower than silicon dioxide (i.e., equal to or lower than 3.9). High dielectric constant dielectric materials typically have a dielectric constant of 7 or higher, or a dielectric constant of 10 or higher.

[0113] Subsequently, in FIG. 2 step 20 of FIG. 3 and shown in x , a first dielectric layer 110 is formed over the substrate 104. (The semiconductor die 102 is omitted in subsequent figures for ease of illustration.) The first dielectric layer 110 is formed of a dielectric material and is typically made of, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (AlO x ), aluminum nitride (AlN), hafnium oxide (HfO x N y ), silicon carbonitride (SiC x O yThe first dielectric layer 110 is formed of a material different from the material of the substrate 100. Forming the first dielectric layer 110 can be by physical vapor deposition (PVD), chemical vapor deposition (CVD), or other suitable process. For example, a silicon-containing gas source can be reacted as a silicon precursor with an oxygen-containing gas source. Examples of such silicon precursors include, but are not limited to, tetraethyl orthosilicate (TEOS), trimethylsilane, tetramethylsilane, and hexachlorodisilane (HCDS). Ozone (O3) can be used to provide the oxygen atoms for the reaction. At temperatures of about 300 °C to about 500 °C or higher, these gases can react to deposit silicon dioxide. The first dielectric layer 110 is then planarized to obtain a planar surface.

[0114] A photoresist layer is then applied and patterned. In FIG. 2 step 210, etching is then performed to form at least one bottom via opening. Typically, multiple such bottom via openings are formed in this etching step. In FIG. 2 step 215, a conductive material is deposited in the bottom via opening to form a bottom via 150. Such deposition can be performed before or after the removal of the patterned photoresist layer. Examples of suitable conductive materials can include molybdenum, tungsten, copper, cobalt, ruthenium, or titanium nitride (TiN). In particular embodiments, the conductive material is molybdenum (Mo) or tungsten (W), and in more particular embodiments, tungsten. The deposition is performed by physical vapor deposition, chemical vapor deposition, sputtering, or other suitable process. Optionally, planarization can be performed again after the deposition to remove excess conductive material, as represented in optional step 218. The resulting structure is shown in FIG. 3 .

[0115] Next, in FIG. 2 step 220 and as illustrated in FIG. 4 , a first etch stop layer 120 is formed over the first dielectric layer 110. The first etch stop layer 120 is formed of a material different from the material of the first dielectric layer 110, and can be formed of, for example, a dielectric material or a metal oxide. In particular embodiments, the first etch stop layer 120 is formed of silicon nitride. Forming the first etch stop layer 120 can be by physical vapor deposition, chemical vapor deposition, atomic layer deposition (ALD), or other suitable process.

[0116] In FIG. 2In step 225, a second dielectric layer 124 is formed over the first etch stop layer 120. The second dielectric layer 124 and the first dielectric layer 110 are typically formed of the same material. Again, physical vapor deposition or chemical vapor deposition is typically used to form the second dielectric layer 124. A photoresist layer is then applied and patterned. FIG. 2 In step 230, the second dielectric layer 124 and the first etch stop layer 120 are etched to form via openings 164 and 174. Each via opening contacts one or more bottom vias 150. The patterned photoresist layer is then removed.

[0117] The resulting structure is shown in FIG. 4 In the accompanying drawing, two different through-hole openings (narrow through-hole opening 164 and wide through-hole opening 174) are illustrated. Narrow through-hole opening 164 contacts only one bottom through-hole 150, while wide through-hole opening 174 contacts two or more bottom through-holes 150.

[0118] Next, in FIG. 2 In step 235 and shown in FIG. 5 In this embodiment, through-hole openings 164 and 174 are filled with conductive material to form through-holes 160 and 170, respectively. In a particular embodiment, the conductive material is molybdenum (Mo).

[0119] exist FIG. 5 In the diagram, through holes 160 and 170 have uneven, rough surfaces. For example... FIG. 2 As indicated by step 240, planarization can be performed again after deposition to remove excess conductive material. The resulting structure is shown in... FIG. 6 middle.

[0120] exist FIG. 2 In the following steps 245, and as FIG. 7 As illustrated, a second etch stop layer 128 is formed on the second dielectric layer 124. The second etch stop layer 128 is formed of a material different from that of the second dielectric layer 124. The second etch stop layer 128 is also typically formed of a material different from that of the first etch stop layer 120. Again, the second etch stop layer 128 can be formed of, for example, a dielectric material or a metal oxide. The second etch stop layer 128 can be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable processes.

[0121] Next, in FIG. 2 In step 250, a third dielectric layer 130 is formed over the second etch stop layer 128. The third dielectric layer 130 can be formed by physical vapor deposition, chemical vapor deposition, or other suitable processes. In a particular embodiment, the third dielectric layer is formed of a low dielectric constant dielectric material.

[0122] Next, inFIG. 2 In step 255, a hard mask layer 140 is formed over the third dielectric layer 130. In particular embodiments, the hard mask layer 140 is formed of tungsten-doped carbide (WdC). Forming the hard mask layer 140 can be by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable process. The resulting structure is illustrated in FIG. 7

[0123] A photoresist layer is then applied and patterned. Next, in step 260 and as illustrated in FIG. 2 FIG. 8 the hard mask layer 140, the third dielectric layer 130, and the second etch stop layer 128 are etched to form top via openings 190. Each top via opening exposes a via 160, a via 170 through the second dielectric layer 124. The patterned photoresist layer is then removed. The hard mask layer 140 can be considered to have windows 142, 144 that expose the vias 160, 170. The windows have a width 143, a width 145.

[0124] Next, in step 265 and as illustrated in FIG. 2 FIG. 9 molybdenum is selectively deposited to form molybdenum caps 166, 176 over each via 160, 170. Notably, molybdenum is not deposited over the hard mask layer 140 or the sides of the hard mask layer 140 in the windows 142, 144. Thus, the width 143, 145 of the windows is not reduced. The interface between the via and the cap is ideally homogeneous, i.e., the via and the cap are formed of the same material.

[0125] In particular embodiments, the selective deposition is performed by chemical vapor deposition. In chemical vapor deposition, a volatile precursor reacts and / or decomposes to produce the desired deposition. In some implementations of the present disclosure, a mixture of a carrier gas and a molybdenum precursor is used. The carrier gas can be, for example, hydrogen (H2). Examples of molybdenum precursors include MoCl5, MoO3, Mo(CO)6, MoO2Cl2, and ammonium heptamolybdate. In particular embodiments, the molybdenum precursor used is MoCl5. In some particular embodiments, the deposition time is about 180 seconds to about 240 seconds.

[0126] ​​​In a further specific embodiment, the atomic or molar ratio between the carrier gas and the molybdenum precursor is about 200:1 or lower (e.g., 1500:1 can be considered an even lower ratio). For clarity, the carrier gas always has a larger molar amount than the molybdenum precursor in the gas mixture. When the ratio is higher than about 2000:1, molybdenum will also deposit on the hard masking layer, thereby reducing the widths 143 and 145 of windows 142 and 144 in the hard masking layer 140 and increasing the risk of void formation. In a more specific embodiment, the molar ratio is about 1900:1 or lower, or about 1500:1 or lower. In this regard, (without being theoretically limited) it is generally believed that at higher molybdenum precursor concentrations, the absorption rate of Mo absorbed on the WdC hard masking layer will decrease, preventing nucleation and Mo deposition on the hard masking layer. Simultaneously, the increased molybdenum concentration will increase the cap growth rate above the vias.

[0127] It is worth noting that the cap illustrated in the attached figure has a dome shape. This dome shape is created because the critical size of the top through-hole opening is larger than the critical size of the through-hole itself. Therefore, deposition occurs in all directions, rather than uniformly across the width of the top through-hole opening.

[0128] Continuing, in FIG. 2 In step 270 and as FIG. 10 As illustrated, a diffusion barrier layer 180 is deposited around each of the caps 166 and 176. The diffusion barrier layer 180 reduces or prevents the diffusion of top via material into the third dielectric layer 130. Suitable examples of diffusion barrier materials include titanium nitride (TiN), tantalum nitride (TaN), indium oxide (In₂O₃), tungsten nitride, tungsten silicide, cobalt, ruthenium, or tantalum. It is worth noting that some of these materials are actually ceramic, but because they possess the general functional property of chemically isolating two materials on opposite sides while still conducting electricity, those skilled in the art consider these materials to be "barrier metals." In a particular embodiment, the diffusion barrier material used is TaN. The diffusion barrier layer 180 can be formed using, for example, atomic layer deposition (ALD) processes. It is worth noting that the diffusion barrier layer 180 is formed on the material of the third dielectric layer 130 and is preferably not deposited on the caps 166 and 176 (but a small amount may fall on the edges of the caps). The diffusion barrier layer 180 may also be on the hard mask layer 140.

[0129] Subsequently, in FIG. 2 In step 275 and as FIG. 11As shown in FIG. 19, the top via opening (or gap) 190 is filled with a conductive material 196. The filling can be performed by physical vapor deposition, chemical vapor deposition, sputtering, or other suitable processes. Since the width of the windows 142, 144 of the hard mask layer 140 is not reduced, the risk of void formation is reduced or avoided. The conductive material can include copper, molybdenum, cobalt, ruthenium, or tungsten. In a particular embodiment, copper is used to fill the top via opening 190. As shown in FIG. 20, excess material can be deposited on the substrate and on the hard mask layer 140. FIG. 11

[0130] In step 280, the substrate is planarized. Referring to FIG. 21, the hard mask layer 140 and the excess diffusion barrier material and top via material deposited on the hard mask layer 140 are removed, thus forming the top via 192, the top via 194. The resulting structure is shown in FIG. 22. FIG. 2 FIG. 11 FIG. 1A

[0131] The methods and systems of some embodiments of the present disclosure have advantages. The via contact area can be increased, thus reducing the total interconnect resistance. The thickness of the metal cap can be increased from 2 nanometers to tens of nanometers, thus increasing the via contact area. The via contact area increase can be achieved without reducing the gap fill window used in the deposition step of forming the top via, thus reducing or avoiding void formation in the top via. In some particular embodiments, the total interconnect resistance can be reduced from 80 ohms to about 60 ohms (kelvin contact resistance of the via on the trench interconnect). The interconnect structure is also suitable for transistors of any pitch, and the interconnect structure is compatible with other interconnect layers and power rails formed on the backside of the wafer substrate.

[0132] ​​​​Additional process steps can be performed to obtain devices having semiconductor packages with interconnect structures. These semiconductor packages can be used in a variety of applications, such as Bipolar-CMOS-DMOS (BCD) circuits for driving discrete high voltage components; drivers for liquid crystal display (LCD), organic light-emitting diode (OLED), active-matrix organic light-emitting diode (AMOLED), or quantum dot light-emitting diode (QLED) display panels; image sensors that can be used in, for example, cell phones, facial recognition systems, or motion sensors for automotive, security, energy efficiency, etc.; power management devices that control power flow and direction; and / or image signal processors (ISPs).

[0133] Some aspects of the disclosure relate to methods of forming a molybdenum cap over a via. A patterned hardmask layer is exposed to a mixture including a carrier gas and a molybdenum precursor to deposit a molybdenum cap over the via. Molybdenum is not deposited over the hardmask layer such that a width of the window in the hardmask layer is not reduced in size.

[0134] In some embodiments, a molar ratio between the carrier gas and the molybdenum precursor is about 2000: 1 or less. In some embodiments, the carrier gas is hydrogen. In some embodiments, the molybdenum precursor is MoCl5. In some embodiments, the via has a width of about 4 nanometers to about 200 nanometers. In some embodiments, the molybdenum cap over the via has a thickness of at least 2 nanometers. In some embodiments, the molybdenum cap over the via has a width of about 4 nanometers to about 30 nanometers or about 4 nanometers to about 1000 nanometers. In some embodiments, the window has a width of about 10 nanometers to about 1000 nanometers. In some embodiments, the via contacts one or more bottom vias. In some embodiments, the method further includes depositing a diffusion barrier layer around the molybdenum cap. In some embodiments, the method further includes forming a top via over the molybdenum cap.

[0135] Embodiments herein also disclose a method of forming an interconnect structure on a substrate. A first dielectric layer is formed over the substrate. The first dielectric layer is etched to form at least one bottom via opening. A conductive material is deposited in the at least one bottom via opening. The substrate is then planarized to obtain at least one bottom via. A first etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over the first etch stop layer. The second dielectric layer and the first etch stop layer are etched to form at least one via opening reaching the at least one bottom via. A conductive material is deposited in the at least one via opening. The second dielectric layer is then planarized to obtain a via. A second etch stop layer is formed over the second dielectric layer. A third dielectric layer is formed over the second etch stop layer. A hard mask layer is formed over the third dielectric layer. The hard mask layer, the third dielectric layer, and the second etch stop layer are etched to form a top via opening exposing the via. Molybdenum is selectively deposited over the exposed via to form a cap. A diffusion barrier layer is deposited around the cap. A conductive material fills the top via opening. The third dielectric layer is then planarized to obtain a top via and form the interconnect structure.

[0136] In some embodiments, forming the cap is using a mixture of H2 and MoCl5, the molar ratio of H2 and MoCl5 (H2:MoCl5) is 1500: 1 or less.

[0137] Embodiments herein also disclose an interconnect structure, wherein the interconnect structure includes a via through a dielectric layer. A cap is over the via. The cap has a thickness of at least 2 nanometers.

[0138] In some embodiments, the molybdenum via has a width of about 4 nanometers to about 200 nanometers. In some embodiments, the molybdenum cap has a width of about 4 nanometers to about 1000 nanometers or about 4 nanometers to about 30 nanometers. In some embodiments, the molybdenum cap has a thickness of at least 2 nanometers to about 40 nanometers. In some embodiments, the dielectric layer includes silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, silicon carbon nitride, or silicon carbon oxide. In some embodiments, the interconnect structure further includes a diffusion barrier layer around the molybdenum cap. In some embodiments, the molybdenum via connects a bottom via and a top via.

[0139] Embodiments herein also disclose an interconnect structure, wherein the interconnect structure includes one or more bottom vias in a first dielectric layer, a via in a second dielectric layer over the first dielectric layer and contacting the bottom vias, a molybdenum cap over the via and having a thickness of 2 nanometers to 40 nanometers, and a top via in a third dielectric layer over the second dielectric layer and electrically connected to the molybdenum cap.

[0140] In some embodiments, the molybdenum cap has a width of 4 nanometers to 1000 nanometers or 4 nanometers to 30 nanometers. In some embodiments, the molybdenum cap has a width in a direction that is greater than a width of the via in the direction. In some embodiments, the interconnect structure further comprises a diffusion barrier layer between the molybdenum cap and the third dielectric layer and between the top via and the third dielectric layer.

[0141] Various embodiments herein also disclose an interconnect structure, wherein the interconnect structure comprises a molybdenum via through a dielectric layer, a molybdenum cap on an upper surface of the dielectric layer, wherein the molybdenum cap contacts the molybdenum via and has a dome. The interconnect structure further comprises a top via on the molybdenum cap, wherein the top via contacts the dome of the molybdenum cap.

[0142] Semiconductor packages containing the interconnect structures are also disclosed herein. Such packages typically also include an integrated circuit (IC). Devices including such semiconductor packages, such as display panel drivers, image sensors, cell phones, facial recognition systems, motion sensors, power management devices, and / or image signal processors, are also contemplated within the scope of the present disclosure.

[0143] The non-limiting working examples below further illustrate methods, systems, and apparatuses of some implementations of the present disclosure, which should be understood as merely illustrative and not intended to limit the disclosure to the materials, conditions, process parameters, and the like, recited herein.

[0144] Experimental implementations were performed using WdC hardmasks and deposition of molybdenum on vias formed of molybdenum. Chemical vapor deposition used a gas mixture of H2 / MoCl5. When the gas ratio of H2 / MoCl5 was 3859, the molybdenum layer formed on the WdC hardmask had a thickness of about 70 angstroms, thus reducing the window width above the via. When the gas ratio was 1900 and the deposition time was 210 seconds, no molybdenum layer was formed on the WdC hardmask.

[0145] The foregoing summary of some embodiments has been presented for the purposes of illustration and description. It is, of course, not intended to be an exhaustive list of aspects of the disclosure. It will be apparent to those of ordinary skill in the art that many changes, modifications, variations, substitutions, deletions, and / or additions can be made to the disclosure as described herein without departing from its spirit and scope.

Claims

1. An interconnect structure, characterized by, Comprising: a molybdenum via through a dielectric layer; and a molybdenum cap over the molybdenum via, wherein the molybdenum cap has a thickness of at least 2 nanometers.

2. The interconnect structure of claim 1, wherein, wherein the molybdenum via has a width of 4 nanometers to 200 nanometers.

3. The interconnect structure of claim 1, wherein, wherein the molybdenum cap has a thickness of at least 2 nanometers to 40 nanometers.

4. The interconnect structure of claim 1, wherein, further comprising a diffusion barrier layer around the molybdenum cap.

5. The interconnect structure of claim 1, wherein, wherein the molybdenum via connects a bottom via and a top via.

6. An interconnect structure, characterized by Comprising: one or more bottom vias in a first dielectric layer; a via in a second dielectric layer over the first dielectric layer, wherein the via contacts the one or more bottom vias; a molybdenum cap over the via, wherein the molybdenum cap has a thickness of 2 nanometers to 40 nanometers; and a top via in a third dielectric layer over the second dielectric layer, wherein the top via is electrically connected to the molybdenum cap.

7. The interconnect structure of claim 6, wherein, wherein the molybdenum cap has a width of 4 nanometers to 1000 nanometers or 4 nanometers to 30 nanometers in a direction.

8. The interconnect structure of claim 6, wherein, wherein a width of the molybdenum cap in a direction is greater than a width of the via in the direction.

9. The interconnect structure of claim 6, wherein, further comprising a diffusion barrier layer between the molybdenum cap and the third dielectric layer and between the top via and the third dielectric layer.

10. An interconnect structure, characterized by, Comprising: a molybdenum via through a dielectric layer; a molybdenum cap over an upper surface of the dielectric layer, wherein the molybdenum cap contacts the molybdenum via, and the molybdenum cap has a dome shape; and a top via over the molybdenum cap, wherein the top via contacts the dome shape of the molybdenum cap.

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