Half-bridge circuit and power module

Abstract

The utility model discloses a half-bridge circuit and a power module. The half-bridge circuit is integrated on the power module, the half-bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between the positive voltage direct current end and the alternating current end, and the second bridge arm is electrically connected between the negative voltage direct current end and the alternating current end; the first bridge arm comprises a first switch unit, the first end of the first switch unit is electrically connected with the positive voltage direct current end, and the second end is electrically connected with the alternating current end; the first end of the first inductor is electrically connected with the second end of the first switch unit; the first end of the first suppression unit is electrically connected with the second end of the first inductor, the second end of the first suppression unit is electrically connected with the control end of the first switch unit, and the first suppression unit is used for suppressing the negative voltage between the control end of the first switch unit and the second end of the first switch unit. According to the embodiment of the invention, the negative voltage Miller peak generated between the gate and the source can be suppressed.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of power semiconductor packaging, and particularly relates to a half-bridge circuit and a power module. BACKGROUND

[0002] When the power module is applied to a power electronic system, switching of a power semiconductor chip is generally accompanied, which causes a change in a current path in the power system, i.e., "commutation".

[0003] However, during the "commutation", the current path (such as a pin and a copper layer of an element in a PCB circuit, and a terminal and a bonding wire in a power module) also has rapidly changing voltage and current. The rapidly changing voltage and current are coupled with the parasitic capacitance / inductance of the current path and the device itself, causing current / voltage overshoot and oscillation. Voltage oscillation is easy to introduce a negative voltage noise to a source electrode of the semiconductor chip, thereby causing a negative voltage Miller spike between the gate and the source. CONTENT OF THE INVENTION

[0004] The application provides a half-bridge circuit and a power module, which can inhibit a negative voltage Miller spike generated between the gate and the source.

[0005] In a first aspect, the application provides a half-bridge circuit, which is integrated in a power module, and the half-bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between a positive voltage DC end and an AC end, and the second bridge arm is electrically connected between a negative voltage DC end and the AC end; the first bridge arm comprises: a first switching unit, a first end of the first switching unit is electrically connected to the positive voltage DC end, and a second end of the first switching unit is electrically connected to the AC end; a first inductor, a first end of the first inductor is electrically connected to the second end of the first switching unit; and a first suppression unit, a first end of the first suppression unit is electrically connected to a second end of the first inductor, and a second end of the first suppression unit is electrically connected to a control end of the first switching unit, and the first suppression unit is configured to suppress a negative voltage between the control end of the first switching unit and the second end of the first switching unit.

[0006] According to the embodiment of the first aspect of the application, the first switching unit comprises a first transistor, and the first suppression unit comprises: a first voltage-resistant diode, a cathode of the first voltage-resistant diode is electrically connected to the control end of the first switching unit; and a first transient voltage suppression diode, an anode of the first transient voltage suppression diode is electrically connected to an anode of the first voltage-resistant diode, and a cathode of the first transient voltage diode is electrically connected to the second end of the first inductor.

[0007] According to any one of the foregoing embodiments of the first aspect of the application, the second bridge arm comprises: a second switch unit, a first end of the second switch unit being electrically connected to the AC end, a second end of the second switch unit being electrically connected to the negative voltage DC end; a second inductor, a first end of the second inductor being electrically connected to the second end of the second switch unit and the negative voltage DC end; a second suppression unit, a first end of the second suppression unit being electrically connected to a second end of the second inductor, a second end of the second suppression unit being electrically connected to a control end of the second switch unit, the second suppression unit being configured to suppress a negative voltage between the control end of the second switch unit and the second end of the second switch unit.

[0008] According to any one of the foregoing embodiments of the first aspect of the application, the second switch unit comprises a second transistor, and the second suppression unit comprises: a second voltage-resistant diode, a cathode of the second voltage-resistant diode being electrically connected to the control end of the second switch unit; a second transient voltage suppression diode, an anode of the second transient voltage suppression diode being electrically connected to an anode of the second voltage-resistant diode, a cathode of the second transient voltage suppression diode being electrically connected to the second end of the second inductor.

[0009] According to any one of the foregoing embodiments of the first aspect of the application, the first switch unit comprises a first transistor, the second switch unit comprises a second transistor, the power module comprises a laminated substrate and a first metal layer; the first metal layer comprises a first metal region, a second metal region, a third metal region, a fourth metal region, a fifth metal region, a sixth metal region and a seventh metal region; the first metal region, the second metal region, the third metal region, the fourth metal region, the fifth metal region, the sixth metal region and the seventh metal region are arranged at intervals along a first direction of the power module; the first metal region is provided with a first die, the first die comprising a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode being electrically connected to the first metal region; the second metal region is provided with a second die, the second die comprising a first voltage-resistant diode, the cathode of the first voltage-resistant diode being electrically connected to the second metal region; the anode of the first transient voltage suppression diode is electrically connected to the anode of the first voltage-resistant diode; the third metal region is provided with at least one third die, the third die comprising the first transistor, the drain of the first transistor being electrically connected to the third metal region, the gate of the first transistor being electrically connected to the second metal region, the source of the first transistor being electrically connected to the first metal region, and the third metal region being electrically connected to a positive direct current terminal; the fourth metal region is provided with at least one fourth die, the fourth die comprising the second transistor, the drain of the second transistor being electrically connected to the fourth metal region, and the fourth metal region being electrically connected to an alternating current terminal; the fifth metal region is electrically connected to a negative direct current terminal, and the fifth metal region is electrically connected to the source of the second transistor; the sixth metal region is provided with a fifth die, the fifth die comprising a second voltage-resistant diode, the cathode of the second voltage-resistant diode being electrically connected to the sixth metal region, and the sixth metal region being electrically connected to the gate of the second transistor; the seventh metal region is provided with a sixth die, the sixth die comprising a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode being electrically connected to the seventh metal region, and the seventh metal region being electrically connected to the source of the second transistor.

[0010] According to any one of the foregoing embodiments of the first aspect of the application, the minimum distance between the first metal region and the second metal region along the first direction is less than the minimum distance between the second metal region and the third metal region along the first direction, and / or the minimum distance between the sixth metal region and the seventh metal region along the first direction is less than the minimum distance between the fifth metal region and the sixth metal region along the first direction.

[0011] According to any one of the foregoing embodiments of the first aspect of the application, the area of the third metal region is greater than the area of at least one of the first metal region, the second metal region, the sixth metal region and the seventh metal region; and the area of the fifth metal region is greater than the area of at least one of the first metal region, the second metal region, the sixth metal region and the seventh metal region.

[0012] According to any one of the foregoing embodiments of the first aspect of the application, the second metal region includes a first sub-metal region and at least one second sub-metal region, and the second die is arranged on the second sub-metal region; in the first direction, the first sub-metal region and the second sub-metal region are arranged between the first metal region and the third metal region, and the first gate resistor is arranged on the second sub-metal region, the first end of the first gate resistor is electrically connected to the second sub-metal region, the second end of the first gate resistor is electrically connected to the first sub-metal region, the cathode of the first voltage-resistant diode is electrically connected to the second sub-metal region, the anode of the first voltage-resistant diode is electrically connected to the anode of the first transient voltage suppression diode, and the second sub-metal region is electrically connected to the gate of the first transistor; the sixth metal region includes at least one third sub-metal region and a fourth sub-metal region, and the fifth die is arranged on the third sub-metal region; in the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, the second gate resistor is arranged on the third sub-metal region, the first end of the second gate resistor is electrically connected to the third sub-metal region, and the second end of the second gate resistor is electrically connected to the seventh metal region; the cathode of the second voltage-resistant diode is electrically connected to the third sub-metal region, the anode of the second voltage-resistant diode is electrically connected to the anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected to the gate of the second transistor.

[0013] According to any one of the foregoing embodiments of the first aspect of the application, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a laminated substrate and a first metal layer; the first metal layer includes an eighth metal region, a ninth metal region, a tenth metal region, an eleventh metal region, and a twelfth metal region; in the first direction of the power module, the eighth metal region, the ninth metal region, the tenth metal region, the eleventh metal region, and the twelfth metal region are arranged at intervals; the eighth metal region is provided with a seventh die, and the seventh die includes a first transient voltage suppression diode, and the cathode of the first transient voltage suppression diode is electrically connected to the eighth metal region; the ninth metal region is provided with at least one eighth die, and the eighth die includes the first transistor, the drain of the first transistor is electrically connected to the ninth metal region, the gate of the first transistor is electrically connected to the eighth metal region, and the ninth metal region is electrically connected to the positive direct-current terminal; the tenth metal region is provided with a ninth die and at least one tenth die, the ninth die includes a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode is electrically connected to the tenth metal region, the tenth die includes a second transistor, and the tenth metal region is electrically connected to the alternating-current terminal; the eleventh metal region is provided with an eleventh die, the eleventh die includes a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode is electrically connected to the eleventh metal region, and the eleventh metal region is electrically connected to the negative direct-current terminal; the twelfth metal region is provided with a twelfth die, the twelfth die includes a second voltage-resistant diode, the cathode of the second voltage-resistant diode is electrically connected to the twelfth metal region, and the anode of the second voltage-resistant diode is electrically connected to the anode of the second transient voltage suppression diode.

[0014] According to an embodiment of the first aspect of the application, the first switch unit comprises a first transistor, the second switch unit comprises a second transistor, the power module comprises a laminated substrate and a first metal layer; the first metal layer comprises a thirteenth metal region, a fourteenth metal region, a fifteenth metal region, a sixteenth metal region, a seventeenth metal region, an eighteenth metal region, a nineteenth metal region and a twentieth metal region; the thirteenth metal region is electrically connected with the AC end; the fourteenth metal region is provided with at least one thirteenth die, the thirteenth die comprising the first transistor, the source of the first transistor being electrically connected with the thirteenth metal region, the drain of the first transistor being electrically connected with the fourteenth metal region, and the fourteenth metal region being electrically connected with the positive DC end; the fifteenth metal region is provided with a fourteenth die, the fourteenth die comprising a first voltage-resistant diode, the cathode of the first voltage-resistant diode being electrically connected with the fifteenth metal region; the sixteenth metal region is provided with a fifteenth die, the fifteenth die comprising a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode being electrically connected with the sixteenth metal region, and the anode of the first transient voltage suppression diode being electrically connected with the anode of the fourteenth die; the seventeenth metal region is electrically connected with the negative DC end; the eighteenth metal region is provided with at least one sixteenth die, the sixteenth die comprising the second transistor, the source of the second transistor being electrically connected with the seventeenth metal region, and the drain of the second transistor being electrically connected with the eighteenth metal region; the nineteenth metal region is provided with a seventeenth die, the seventeenth die comprising a second voltage-resistant diode, the cathode of the second voltage-resistant diode being electrically connected with the nineteenth metal region; and the twentieth metal region is provided with an eighteenth die, the eighteenth die comprising a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode being electrically connected with the twentieth metal region, and the anode of the second transient voltage suppression diode being electrically connected with the anode of the second voltage-resistant diode.

[0015] In a second aspect, the embodiments of the application provide a power module, the power module comprising the half-bridge circuit according to the first aspect.

[0016] The half-bridge circuit and the power module provided by the embodiment of the present application, the half-bridge circuit is integrated in the power module, the half-bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between the positive voltage DC end and the AC end, and the second bridge arm is electrically connected between the negative voltage DC end and the AC end. The first bridge arm comprises: a first switch unit, a first end of the first switch unit is electrically connected with the positive voltage DC end, and a second end of the first switch unit is electrically connected with the AC end; a first inductor, a first end of the first inductor is electrically connected with the second end of the first switch unit; and a first suppression unit, a first end of the first suppression unit is electrically connected with a second end of the first inductor, and a second end of the first suppression unit is electrically connected with a control end of the first switch unit, and the first suppression unit is used for suppressing negative voltage between the control end of the first switch unit and the second end of the first switch unit. The half-bridge circuit is integrated in the power module, and with the switching process of the first switch unit, the current flow path in the power module changes, that is, the commutation. In this process, with the rapid turn-off of the second switch unit, the changing current causes the first inductor to generate an induced negative voltage drop, and in combination with the closed first switch unit, the two ends of the first switch unit in parallel with the first inductor bear an excessively high negative voltage. The present application introduces the first suppression unit at the control end and the second end of the first switch unit, and slows down the change of the current through the first suppression unit, so as to suppress the negative voltage between the control end and the second end of the first switch unit. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below, and other drawings can also be obtained by those of ordinary skill in the art without creative labor on the basis of these drawings.

[0018] Figure 1 is a circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0019] Figure 2 is another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0020] Figure 3 is still another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0021] Figure 4 is still another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0022] Figure 5 is still another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0023] Figure 6 is still another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application;

[0024] Figure 7 is a partial enlarged schematic view of the current flow direction when the half-bridge circuit forms the suppression effect, provided by an embodiment of the present application;

[0025] Figure 8 is a structural schematic view of a die, provided by an embodiment of the present application;

[0026] Figure 9 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application; Figure 6 is a longitudinal sectional schematic view of the buffer circuit part obtained by taking a section along the dashed line path;

[0027] Figure 10 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application;

[0028] Figure 11 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application;

[0029] Figure 12 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application;

[0030] Figure 13 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application; Figure 11 is a partial enlarged schematic view of the current flow direction when the half-bridge circuit forms the suppression effect, provided by an embodiment of the present application;

[0031] Figure 14 is a schematic view of another circuit connection of the half-bridge circuit, provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below in combination with the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0033] The acquisition, storage, use, processing, etc. of data in the technical solutions of the present application all comply with the relevant provisions of national laws and regulations.

[0034] It should be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0035] It should be understood that the term "and / or" as used herein merely describes associated objects, and can exist in three forms: A and / or B, A or B, and A and B. In addition, the character " / " is generally used to represent an "or" relationship between the front and rear associated objects.

[0036] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or that two components are electrically connected via one or more other components.

[0037] Various modifications and changes can be made to the present application in light of the above description of the application without departing from the spirit or scope of the application. Accordingly, the present application is intended to embrace all modifications and alterations of this application that fall within the scope of the claims (the technical solutions claimed in the application) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction, if possible.

[0038] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0039] Power semiconductor chips have been widely used in the fields of automotive motor drive and battery management, industrial frequency converters, photovoltaic inverters and other related fields due to their functions of control and energy conversion. A power module encapsulates multiple power semiconductor chips in the same module to form a required circuit topology. In addition to better heat dissipation and high reliability, higher integration reduces the space occupied by the power electronic system, and fewer connection lines reduce the complexity of the system. Therefore, power modules are often used in high-power power conversion and motor control. The power module packaging process generally includes chip grouping, chip mounting, wire bonding, sub-unit welding, shell assembly, terminal interconnection, and potting. After completing the circuit topology on the insulating substrate, the terminals are connected by wire bonding to realize the required functions of the circuit.

[0040] When the power module is applied in a power electronic system, it generally accompanies the switching process of the power semiconductor chip, which changes the current flow path in the power system, i.e., "commutation". During this process, the current path (such as the pins and copper layers of the components in the PCB circuit, the terminals and bonding wires in the power module) will also have rapidly changing voltage and current. The rapidly changing voltage and current are coupled with the parasitic capacitance and inductance of the current path and the device itself, causing current / voltage overshoot and oscillation.

[0041] To solve the above problems, the embodiments of the present application provide a half-bridge circuit and a power chip. First, the negative voltage Miller suppression circuit is introduced.

[0042] Figure 1 is a circuit connection schematic diagram of the half-bridge circuit provided by the embodiments of the present application, as shown in Figure 1 The half-bridge circuit 100 is integrated in a power module, and the half-bridge circuit 100 can include a first bridge arm 110 and a second bridge arm 120.

[0043] The first bridge arm 110 is electrically connected between the positive voltage DC+ and the AC terminal, and the second bridge arm 120 is electrically connected between the negative voltage DC- and the AC terminal; the first bridge arm 110 can include a first switching unit S1, a first inductor L2 and a first suppression unit 111.

[0044] The first end of the first switching unit S1 is electrically connected to the positive voltage DC+, and the second end of the first switching unit S1 is electrically connected to the AC terminal; the first end of the first inductor L2 is electrically connected to the second end of the first switching unit S1; the first end of the first suppression unit 111 is electrically connected to the second end of the first inductor L2, and the second end of the first suppression unit 111 is electrically connected to the control end of the first switching unit S1, and the first suppression unit 111 is used to suppress the negative voltage between the control end of the first switching unit S1 and the second end of the first switching unit S1.

[0045] It should be noted that the first inductor L2 is not a specific existing electrical element, and is specifically a parasitic inductance generated by the magnetic effect when the current flows in the metal region.

[0046] Figure 2 is another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the application, as shown in Figure 2 To functionally illustrate the half-bridge circuit in the application, a load inductor L1 is introduced, the load inductor L1 is in parallel with the first bridge arm 110 or in parallel with the second bridge arm 120, Figure 2 Taking the case that L1 is in parallel with 110.

[0047] In Figure 2 , if the first suppression unit 111 does not exist, when the first switching unit S1 remains off and S2 changes from on to off, due to the existence of the load inductor L1 and the inductance current does not change abruptly, the second end of L1, that is, the first end of the first inductor L2, maintains the original current flowing to the first switching unit S1, thereby causing the control end of S1 and the second end of S1 to generate a negative voltage drop, so that the control end of S1 bears an excessively high negative voltage, and the reliability is reduced.

[0048] In some embodiments, the first switching unit S1 can be a field effect transistor, the control end of the field effect transistor is electrically connected with the second end of the first suppression unit 111, the drain end of the field effect transistor is electrically connected with the positive direct current end DC+, and the source end of the field effect transistor is electrically connected with the first end of the first inductor L2, and this embodiment is also applicable to other power semiconductor chips.

[0049] The half-bridge circuit 100 is integrated in a power module, the first switching unit S1 remains off, and with the switching process of the second switching unit S1, the current flow path in the power module changes, that is, commutation. In this process, the first switching unit S1 remains off, and with the off of the second switching unit S2, the changing current causes the first inductor L2 to generate an induced negative voltage drop, and in combination with the off of the first switching unit S1, the two ends of the first switching unit S1 and the first inductor L2 bear an excessively high negative voltage. The application introduces the first suppression unit 111 at the control end and the second end of the first switching unit S1, and slows down the change of the current through the first suppression unit 111, thereby suppressing the negative voltage between the control end and the second end of the first switching unit S1.

[0050] Figure 3 is another circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the application, as shown in Figure 3 The first switching unit S1 can include a first transistor, and the first suppression unit 111 can include a first voltage-resistant diode D1 and a first transient voltage suppression diode D2.

[0051] The cathode of the first voltage-resistant diode D1 is electrically connected with the control end of the first switch unit S1; the anode of the first transient voltage suppression diode D2 is electrically connected with the anode of the first voltage-resistant diode D1, and the cathode of the first transient voltage diode is electrically connected with the second end of the first inductor L2.

[0052] The second bridge arm 120 can include: a second switch unit S2, a second inductor L3, and a second suppression unit 121. The first end of the second switch unit S2 is electrically connected with the alternating current end AC, and the second end of the second switch unit S2 is electrically connected with the negative voltage direct current end DC-. The first end of the second inductor L3 is electrically connected with the second end of the second switch unit S2 and the negative voltage direct current end DC-. The first end of the second suppression unit 121 is electrically connected with the second end of the second inductor L3, and the second end of the second suppression unit 121 is electrically connected with the control end of the second switch unit S2. The second suppression unit 121 is used to suppress the negative voltage between the control end of the second switch unit S2 and the second end of the second switch unit S2.

[0053] It should be noted that the second inductor L3 is not a specific existing electrical element, but a parasitic inductance generated by the magnetic effect when the current flows in the metal area. The generation principle is the same as that of the first inductor L2.

[0054] The second switch unit S2 includes a second transistor, and the second suppression unit 121 can include: a second voltage-resistant diode D3 and a second transient voltage suppression diode D4.

[0055] The cathode of the second voltage-resistant diode D3 is electrically connected with the control end of the second switch unit S2; the anode of the second transient voltage suppression diode D4 is electrically connected with the anode of the second voltage-resistant diode D3, and the cathode of the second transient voltage suppression diode D4 is electrically connected with the second end of the second inductor L3.

[0056] In some embodiments, the half-bridge circuit 100 further includes a bus capacitor C, the first end of the bus capacitor C is electrically connected with the positive voltage direct current end DC+, and the second end of the bus capacitor C is electrically connected with the negative voltage direct current end DC-. The bus capacitor C is used for energy storage in the half-bridge circuit 100 of the present application.

[0057] In some embodiments, the first transient voltage suppression diode D2 and the second transient voltage suppression diode D4 can be transient voltage suppression diodes (TVS).

[0058] When the first switch unit S1 is a field effect transistor, the first voltage-resistant diode D1 and the first transient voltage suppression diode D2 are electrically connected between the gate end and the source end of the field effect transistor, the voltage between the gate end and the source end of the bipolar transistor is clamped at the required negative voltage position by the TVS, thereby improving the reliability of the system.

[0059] The above is the connection mode of the half-bridge circuit.

[0060] The working principle of the negative voltage Miller spike suppression circuit is as follows: the half-bridge is in normal working condition, that is, Figure 2 Without the first suppression unit, the gate-source voltage of the first switch unit that is not turned on is generally generated by the driving circuit off (characteristic value 0~-5V) to completely turn off the chip. The change of the current path causes the parasitic inductance to generate an induced negative voltage drop V L , wherein V L is calculated as follows:

[0061]

[0062] , wherein I DS is the current of the half-bridge, and the sum of V L and V off is too high, which can reduce the reliability of the power semiconductor chip. The TVS tube of the half-bridge circuit has an avalanche breakdown voltage drop V Z and a forward conduction voltage drop V F (characteristic value 0.2~0.6V) of the voltage-resistant diode. When the negative voltage drop is higher than the sum of the avalanche breakdown voltage drop of the TVS tube and the forward conduction voltage drop of the voltage-resistant diode, that is,

[0063] |V off |+|V L |>V Z +V F (2)

[0064] The TVS tube is in an avalanche breakdown state, and the voltage-resistant diode is in a forward conduction state, so as to ensure that the gate voltage of the power semiconductor chip and the corresponding source voltage satisfy the corresponding relationship, that is,

[0065] V GS_OFF =-(V Z +V F ) (3)

[0066] , wherein the off voltage V GS_OFF between the gate and the source, and the voltage-resistant diode functions in the on state of the power semiconductor chip, and is in a reverse blocking state to ensure that the power semiconductor chip is effectively turned on. Therefore, the voltage values of the two diodes should satisfy:

[0067] V GS_R >V Z +V F >|V off | (4)

[0068] V R >V GS_ON (5)

[0069] wherein, V R is the maximum peak reverse voltage that the voltage-resistant diode can withstand continuously, obtained through a datasheet. V GS_R is the maximum negative voltage that the gate of the power semiconductor chip can withstand, obtained through a datasheet. V GS_ON is the gate-source voltage when the first switching unit is turned on. The voltage-resistant diode and the TVS tube are both inside the module, and are very close to the gate-source of the power semiconductor chip, so that the parasitic inductance introduced is smaller, and the negative voltage Miller peak can be better suppressed.

[0070] Exemplarily, when the second switching unit S2 is turned off, the first switching unit S1 generates an induced electromotive force due to the first inductor L2 (a kind of parasitic inductor), so that the gate-source voltage is -10V, and the negative voltage between the gate and the source is too large; the second transient voltage suppression diode D2 is introduced, and the breakdown voltage is 4.7V. The first voltage-resistant diode D1 is introduced, and appropriate parameters are selected so that the forward voltage of D1 is 0.6V. Then, the gate-source voltage of -10V is clamped at -5.3V due to the reverse breakdown of D2 and the forward conduction of D1.

[0071] Since the half-bridge circuit is applied in the power module, the voltage-resistant diode and the TVS tube are generally arranged on the PCB board outside the module. Since the two diodes are connected to the gate and the source of the switching unit respectively, the flexibility of the PCB board is affected; most of the power module DC+, DC-, and AC ports have a large spacing, so that the space occupied by the half-bridge circuit is further increased. For the half-bridge circuit itself, the voltage-resistant diode and the TVS tube flow through a relatively long lead, so that the delay is increased; the half-bridge circuit is connected in parallel to the gate and the source of the power semiconductor chip, and the long-distance lead or the metallization layer path of the module will generate parasitic inductance, so that the suppression effect is weakened.

[0072] For the half-bridge circuit applied in the power module, the problems of large space occupation and inability to be close to the power semiconductor chip are common, and the layout structure of the half-bridge circuit on the power module is provided.

[0073] Figure 4 is another kind of circuit connection schematic diagram of the half-bridge circuit provided by the embodiment of the present application, as shown in Figure 4 The half-bridge circuit is integrated in the power module, and the power module includes a laminated substrate and a first metal layer; the first metal layer includes a first metal region J1, a second metal region J2, a third metal region J3, a fourth metal region J4, a fifth metal region J5, a sixth metal region J6, and a seventh metal region J7; along a first direction of the power module, the first metal region J1, the second metal region J2, the third metal region J3, the fourth metal region J4, the fifth metal region J5, the sixth metal region J6, and the seventh metal region J7 are arranged at intervals. It should be noted that, Figure 4The application discloses a metal pattern design of a half-bridge circuit.

[0074] Figure 5 The application provides another circuit connection diagram of the half-bridge circuit, which is a layout structure of the half-bridge circuit in application.

[0075] The Miller clamp is arranged in the driving circuit, and the disadvantage is that the suppression effect is weakened due to the increase of the circuit parasitic inductance. The half-bridge circuit is integrated in the module, and the negative voltage Miller peak can be better suppressed.

[0076] In combination with Figure 4 , Figure 5 and Figure 6 , the first metal area J1 is provided with a first die, the first die comprises a first transient voltage suppression diode D2, the cathode of the first transient voltage suppression diode D2 is electrically connected with the first metal area J1; the second metal area J2 is provided with a second die, the second die comprises a first voltage-resistant diode D1, the cathode of the first voltage-resistant diode D1 is electrically connected with the second metal area J2; the anode of the first transient voltage suppression diode D2 is electrically connected with the anode of the first voltage-resistant diode D1; the third metal area J3 is provided with at least one third die, the third die comprises a first transistor S1, the drain of the first transistor S1 is electrically connected with the third metal area J3, the gate of the first transistor S1 is electrically connected with the second metal area J2, the source of the first transistor S1 is electrically connected with the first metal area J1, and the third metal area J3 is electrically connected with a positive voltage direct current end DC+; the fourth metal area J4 is provided with at least one fourth die, the fourth die comprises a second transistor S2, the drain of the second transistor S2 is electrically connected with the fourth metal area J4, and the fourth metal area J4 is electrically connected with an alternating current end AC; the fifth metal area J5 is electrically connected with a negative voltage direct current end DC-, and the fifth metal area J5 is electrically connected with the source of the second transistor S2; the sixth metal area J6 is provided with a fifth die, the fifth die comprises a second voltage-resistant diode D3, the cathode of the second voltage-resistant diode D3 is electrically connected with the sixth metal area J6, and the sixth metal area J6 is electrically connected with the gate of the second transistor S2; the seventh metal area J7 is provided with a sixth die, the sixth die comprises a second transient voltage suppression diode D4, the cathode of the second transient voltage suppression diode D4 is electrically connected with the seventh metal area J7, and the seventh metal area J7 is electrically connected with the source of the second transistor S2.

[0077] It should be noted that Figure 6 the connection diagram of the half-bridge circuit is designed for a power module metal area with a Kelvin source.

[0078] It should be noted that the above-mentioned electrical connection modes are all electrically connected through bonding wires, and the connected devices are all dies. Figure 8is a structural schematic diagram of a die provided by an embodiment of the present application. A diode die is used instead of a packaged diode device, and the power semiconductor chip, the voltage-resistant diode, and the TVS diode die structure are as shown in Figure 8 . Since the overall process includes processes such as patching, die bonding, and potting, the present application does not introduce additional packaging processes.

[0079] In addition, the electrical connection between the die and the metal region includes reflow soldering, conductive silver paste, and (silver, copper) sintering.

[0080] In Figure 6 , the black line is a bonding wire, and in actual applications, the bonding process includes coarse aluminum wire, aluminum ribbon bonding, and copper wire and copper ribbon bonding. The dashed line is the current direction when a negative voltage Miller peak is generated, and the enlarged view is shown in Figure 7 . Figure 7 is a partial enlarged schematic diagram of the current flow direction when the suppression effect is formed in the half-bridge circuit provided by an embodiment of the present application.

[0081] In some embodiments, the minimum distance between the first metal region J1 and the second metal region J2 in the first direction is less than the minimum distance between the second metal region J2 and the third metal region J3 in the first direction, and / or the minimum distance between the sixth metal region J6 and the seventh metal region J7 in the first direction is less than the minimum distance between the fifth metal region J5 and the sixth metal region J6 in the first direction.

[0082] In some embodiments, the area of the third metal region J3 is greater than the area of at least one of the first metal region J1, the second metal region J2, the sixth metal region J6, and the seventh metal region J7; and the area of the fifth metal region J5 is greater than the area of at least one of the first metal region J1, the second metal region J2, the sixth metal region J6, and the seventh metal region J7.

[0083] The third metal region J3 and the fifth metal region J5 are provided with a large area to facilitate electrical connection with the positive voltage DC+ and the negative voltage DC- outside.

[0084] Figure 9 is a longitudinal sectional schematic diagram of the buffer circuit portion obtained by taking a section along the Figure 7 dashed line path, as shown in Figure 9 , the power module can include a laminated metallization layer on an insulating substrate, an insulating substrate, and a metallization layer under the insulating substrate.

[0085] Figure 10 is another circuit connection schematic diagram of the half-bridge circuit provided by an embodiment of the present application, as shown in Figure 10 , in combination with Figure 3The second metal region J2 includes a first sub-metal region J2' and at least one second sub-metal region J2'', and the second die is arranged on the second sub-metal region J2''; along the first direction, the first sub-metal region J2' and the second sub-metal region J2'' are arranged between the first metal region and the third metal region, the first gate resistor R1 is arranged on the second sub-metal region J2'', the first end of the first gate resistor R1 is electrically connected with the second sub-metal region J2'', the second end of the first gate resistor R1 is electrically connected with the first sub-metal region J2', the cathode of the first voltage-resistant diode is electrically connected with the second sub-metal region J2'', the anode of the first voltage-resistant diode is electrically connected with the anode of the first transient voltage suppression diode, and the second sub-metal region J2'' is electrically connected with the gate of the first transistor; the sixth metal region includes at least one third sub-metal region and a fourth sub-metal region, and the fifth die is arranged on the third sub-metal region; along the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, the second gate resistor R2 is arranged on the third sub-metal region, the first end of the second gate resistor R2 is electrically connected with the third sub-metal region, the second end of the second gate resistor R2 is electrically connected with the seventh metal region; the cathode of the second voltage-resistant diode is electrically connected with the third sub-metal region, the anode of the second voltage-resistant diode is electrically connected with the anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected with the gate of the second transistor.

[0086] It should be noted that, Figure 10 The connection diagram of the half-bridge circuit provided is designed for a power module metal region with a Kelvin source, and the gate resistor is integrated in the power module.

[0087] In terms of the trend of power modules, the gate resistor is integrated in the power module, and the gate resistor is very close to the gate of the power semiconductor chip, thereby reducing the parasitic inductance.

[0088] For such a power module, the Miller clamp circuit added to the driving PCB cannot provide a low-impedance path, and the Miller clamp cannot work effectively. In the application, the lower surface of the first voltage-resistant diode die of the first bridge arm is attached to the integrated second sub-metal region J2'', and the upper surface of the first voltage-resistant diode is connected to the upper surface of the TVS tube through a bonding wire. The half-bridge circuit of the application effectively reduces the parasitic inductance of the circuit before the gate resistor, and the suppression of negative voltage is more obvious. The number of the first transistors of the first bridge arm determines the number of the second sub-metal regions J2'', and there is a voltage-resistant diode on each second sub-metal region J2''. For a power module with a high number of parallel connections, multiple TVS tubes can be connected in parallel.

[0089] Figure 11 is another circuit connection diagram of the half-bridge circuit provided by the application, as Figure 11The first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a laminated substrate and a first metal layer.

[0090] The first metal layer includes an eighth metal region J8, a ninth metal region J9, a tenth metal region J10, an eleventh metal region J11, and a twelfth metal region J12. The eighth metal region J8, the ninth metal region J9, the tenth metal region J10, the eleventh metal region J11, and the twelfth metal region J12 are arranged at intervals in a first direction of the power module. The eighth metal region J8 is provided with a seventh die, and the seventh die includes a first transient voltage suppression diode D2. The cathode of the first transient voltage suppression diode D2 is electrically connected to the eighth metal region J8. The ninth metal region J9 is provided with at least one eighth die, and the eighth die includes a first transistor S1. The drain of the first transistor S1 is electrically connected to the ninth metal region J9. The gate of the first transistor S1 is electrically connected to the eighth metal region J8. The ninth metal region J9 is electrically connected to a positive direct current terminal DC+. The tenth metal region J10 is provided with a ninth die and at least one tenth die. The ninth die includes a first transient voltage suppression diode D2. The cathode of the first transient voltage suppression diode D2 is electrically connected to the tenth metal region J10. The tenth die includes a second transistor S2. The tenth metal region J10 is electrically connected to an alternating current terminal AC. The eleventh metal region J11 is provided with an eleventh die. The eleventh die includes a second transient voltage suppression diode D4. The cathode of the second transient voltage suppression diode D4 is electrically connected to the eleventh metal region J11. The eleventh metal region J11 is electrically connected to a negative direct current terminal DC-. The twelfth metal region J12 is provided with a twelfth die. The twelfth die includes a second voltage-resistant diode D3. The cathode of the second voltage-resistant diode D3 is electrically connected to the twelfth metal region J12. The anode of the second voltage-resistant diode D3 is electrically connected to the anode of the second transient voltage suppression diode D4.

[0091] It should be noted that, Figure 11 The connection diagram of the half-bridge circuit provided is designed for a power module metal region without a Kelvin source. The design of the power module metal region without the Kelvin source is not limited to Figure 11 A, which is not listed one by one here.

[0092] Figure 12 is another circuit connection diagram of the half-bridge circuit provided by the embodiment of the application, as Figure 12 As shown in the figure, the first switch unit includes a first transistor S1, the second switch unit includes a second transistor S2, and the power module includes a laminated substrate and a first metal layer.

[0093] The first metal layer comprises a thirteenth metal region J13, a fourteenth metal region J14, a fifteenth metal region J15, a sixteenth metal region J16, a seventeenth metal region J17, an eighteenth metal region J18, a nineteenth metal region J19 and a twentieth metal region J20; the thirteenth metal region J13 is electrically connected with the alternating current end AC; the fourteenth metal region J14 is provided with at least one thirteenth die, and the thirteenth die comprises a first transistor S1, the source of the first transistor S1 is electrically connected with the thirteenth metal region J13, the drain of the first transistor S1 is electrically connected with the fourteenth metal region J14, and the fourteenth metal region J14 is electrically connected with the positive direct current end DC+; the fifteenth metal region J15 is provided with a fourteenth die, and the fourteenth die comprises a first voltage-resistant diode D1, the cathode of the first voltage-resistant diode D1 is electrically connected with the fifteenth metal region J15; the sixteenth metal region J16 is provided with a fifteenth die, and the fifteenth die comprises a first transient voltage suppression diode D2, the cathode of the first transient voltage suppression diode D2 is electrically connected with the sixteenth metal region J16, and the anode of the first transient voltage suppression diode D2 is electrically connected with the anode of the fourteenth die; the seventeenth metal region J17 is electrically connected with the negative direct current end DC-; the eighteenth metal region J18 is provided with at least one sixteenth die, and the sixteenth die comprises a second transistor S2, the source of the second transistor S2 is electrically connected with the seventeenth metal region J17, and the drain of the second transistor S2 is electrically connected with the eighteenth metal region J18; the nineteenth metal region J19 is provided with a seventeenth die, and the seventeenth die comprises a second voltage-resistant diode D3, the cathode of the second voltage-resistant diode D3 is electrically connected with the nineteenth metal region J19; the twentieth metal region J20 is provided with an eighteenth die, and the eighteenth die comprises a second transient voltage suppression diode D4, the cathode of the second transient voltage suppression diode D4 is electrically connected with the twentieth metal region J20, and the anode of the second transient voltage suppression diode D4 is electrically connected with the anode of the second voltage-resistant diode D3.

[0094] It should be noted that, Figure 12 The provided is for the power module metal region design with Kelvin source, and the power module metal region design with Kelvin source is not limited to Figure 6 , Figure 10 and Figure 12 , which are not listed one by one.

[0095] Figure 13 is a partial enlarged schematic view of the current flow direction when the half-bridge circuit formed in Figure 12 has a suppression effect.

[0096] The structural design layout in the present application is as shown in Figure 6 , Figure 10 , Figure 11 and Figure 12 , wherein Figure 11For the power module without Kelvin source, the half-bridge circuit can still achieve the function of negative voltage Miller clamp by changing the position of the TVS tube at the Kelvin source from the copper line of the Kelvin source to the source copper of the power semiconductor chip. At this time, the current loop distance from the TVS tube to the corresponding power semiconductor chip should be as short as possible to reduce the parasitic inductance of this section.

[0097] In the present application, the first transistor, the second transistor, the voltage-resistant diode and the transient voltage suppression diode can be connected in the same way, and the connection with the metallized pattern can be selected from silver adhesive bonding, tin paste reflow soldering and silver sintering and other mounting processes. The connection between the upper surface of the first transistor, the second transistor and the diode (including the voltage-resistant diode and the transient voltage diode in the present application) and the metallized pattern can be selected from wire bonding (aluminum wire, copper wire), copper sheet welding, conductive film welding and other processes. The connection between the terminal and the metallized layer of the insulating substrate can be selected from wire bonding (aluminum wire, copper wire), reflow soldering, laser welding and other ways to directly connect the terminal with the metallized layer.

[0098] Figure 14 is a schematic diagram of the internal structure and electrical connection of the module of the PCB integrated gate resistor and the half-bridge circuit. The PCB inside the power module is usually bonded on the insulating substrate, and the metallized pattern is drawn on it through the solder pad. 25. First bridge arm PCB pattern, 26. First bridge arm gate pad pattern, 27. First bridge arm integrated resistor pad pattern, 28. First bridge arm Kelvin source pad pattern on the PCB, 29. Second bridge arm PCB pattern, 30. Second bridge arm gate pad pattern, 31. Second bridge arm integrated resistor pad pattern, 32. Second bridge arm Kelvin source pad pattern on the PCB.

[0099] For the power module with an internally bonded PCB, the internal structure and electrical connection schematic diagram is shown in Figure 14 The gate of the first transistor of the first bridge arm of the internally bonded PCB is connected to the metallized pattern 27 on the PCB board through the bonding wire, and the metallized pattern 27 is the solder pad on the PCB board. It should be noted that the metallized pattern 27 is connected with the bonding wire of the gate, the lower surface of the first voltage-resistant diode and one end of the first gate resistor, respectively, which ensures the electrical connection and can replace the metallized pattern to adapt to the metallized pattern inside the power module, or add PCB ink on the surface. The structure of the present application can also achieve good negative voltage Miller clamp suppression in the module with a bonded PCB. At the same time, since the circuit is located before the gate circuit, the parasitic inductance in the module is reduced. Since the PCB is bonded inside the module, the packaged TVS tube and the voltage-resistant diode can be welded on the PCB, but the chip pin will introduce parasitic inductance, and compared with that, the reflow soldering diode die is more suitable.

[0100] In addition, the embodiment of the present application also provides a power chip comprising the half-bridge circuit as described above.

[0101] It should be noted that the element die of the half-bridge circuit in the present application is connected to the metal area in the power module instead of being welded on the PCB as the traditional circuit element, which enhances the performance of the circuit.

[0102] In addition, the half-bridge circuit mentioned in the present application is suitable for different power modules and different cases (with or without a Kelvin source metal area, with or without a gate resistance metal area, etc.). It is not just an example of a metallized pattern.

[0103] In general, the present application proposes a layout design scheme of integrating a half-bridge circuit on the upper metallized surface of an insulating substrate in a power module. By using a voltage-resistant diode and a TVS tube die instead of a packaged device, a Miller peak suppression function is realized on the insulating substrate. This internal structure has the characteristics of small occupied volume, high integration and strong reliability; at the same time, the Miller peak suppression circuit itself has a short line and is very close to the power semiconductor chip, which will not introduce more circuit hybrid inductance to generate a larger negative voltage Miller peak; the metallized pattern is suitable for different power modules. Since the diode chip installation process in the half-bridge circuit uses chip mounting, wire bonding, encapsulation and other processes consistent with the packaging process of the power module, the addition of this Miller peak suppression circuit will not increase additional processes in production, and has good production adaptability.

[0104] The advantages of the present application are that (1) the present application directly integrates a half-bridge circuit inside a power module, reducing the influence of voltage overshoot generated by commutation on the reliability of the device. (2) The half-bridge circuit is very close to the gate and source of the power semiconductor chip, reducing the influence of parasitic inductance on the Miller clamping effect. (3) The voltage-resistant diode and the TVS tube die are used instead of packaged diodes to realize the negative voltage Miller peak suppression function on the insulating substrate with only a single layer of metallized pattern. (4) The half-bridge circuit uses the same packaging process as the power semiconductor chip, without introducing additional process steps in the module production. (5) The positions of the voltage-resistant diode and the TVS tube can be exchanged, but the mounting direction of the cathode and anode of the voltage-resistant diode and the TVS tube is correspondingly changed. (6) For power module products integrated with internal gate resistors, the negative voltage Miller clamping effect is still excellent.

[0105] It should be clear that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after understanding the spirit of the present application.

[0106] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electrical modules, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electrical modules, semiconductor memory devices, read-only memory (ROM), flash memory, erasable read-only memory (EROM), floppy disks, compact disc read-only memory (CD-ROM), optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0107] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0108] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0109] The above merely describes a specific implementation of the present application. Those skilled in the art can clearly understand the specific working processes of the system, modules and units described above for the convenience and brevity of description, and can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein again. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A half bridge circuit, characterized in that, The integrated power module, the half-bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between the positive voltage DC end and the AC end, and the second bridge arm is electrically connected between the negative voltage DC end and the AC end. The first bridge arm comprises: A first switching unit, a first end of the first switching unit is electrically connected to the positive voltage DC end, and a second end of the first switching unit is electrically connected to the AC end; A first inductor, a first end of the first inductor is electrically connected to the second end of the first switching unit; A first suppression unit, a first end of the first suppression unit is electrically connected to a second end of the first inductor, and a second end of the first suppression unit is electrically connected to a control end of the first switching unit, and the first suppression unit is used for suppressing negative voltage between the control end of the first switching unit and the second end of the first switching unit.

2. The half bridge circuit of claim 1, characterized in that, The first switching unit comprises a first transistor, and the first suppression unit comprises: A first voltage-resistant diode, a cathode of the first voltage-resistant diode is electrically connected to the control end of the first switching unit; A first transient voltage suppression diode, an anode of the first transient voltage suppression diode is electrically connected to an anode of the first voltage-resistant diode, and a cathode of the first transient voltage suppression diode is electrically connected to the second end of the first inductor.

3. The half bridge circuit of claim 2, wherein, The second bridge arm comprises: A second switching unit, a first end of the second switching unit is electrically connected to the AC end, and a second end of the second switching unit is electrically connected to the negative voltage DC end; A second inductor, a first end of the second inductor is electrically connected to the second end of the second switching unit and the negative voltage DC end; A second suppression unit, a first end of the second suppression unit is electrically connected to a second end of the second inductor, and a second end of the second suppression unit is electrically connected to a control end of the second switching unit, and the second suppression unit is used for suppressing negative voltage between the control end of the second switching unit and the second end of the second switching unit.

4. The half bridge circuit of claim 3, characterized in that, The second switching unit comprises a second transistor, and the second suppression unit comprises: A second voltage-resistant diode, a cathode of the second voltage-resistant diode is electrically connected to the control end of the second switching unit; A second transient voltage suppression diode, an anode of the second transient voltage suppression diode is electrically connected to an anode of the second voltage-resistant diode, and a cathode of the second transient voltage suppression diode is electrically connected to the second end of the second inductor.

5. The half bridge circuit of claim 4, characterized in that, The first switching unit comprises a first transistor, the second switching unit comprises a second transistor, and the power module comprises a laminated substrate and a first metal layer; The first metal layer comprises a first metal region, a second metal region, a third metal region, a fourth metal region, a fifth metal region, a sixth metal region and a seventh metal region; In a first direction of the power module, the first metal region, the second metal region, the third metal region, the fourth metal region, the fifth metal region, the sixth metal region and the seventh metal region are arranged at intervals; The first metal region is provided with a first die, and the first die comprises a first transient voltage suppression diode, and a cathode of the first transient voltage suppression diode is electrically connected to the first metal region; The second metal region is provided with a second die, and the second die comprises a first voltage-resistant diode, and a cathode of the first voltage-resistant diode is electrically connected with the second metal region; an anode of the first transient voltage suppression diode is electrically connected with an anode of the first voltage-resistant diode; The third metal region is provided with at least one third die, and the third die comprises the first transistor, a drain of the first transistor is electrically connected with the third metal region, a gate of the first transistor is electrically connected with the second metal region, a source of the first transistor is electrically connected with the first metal region, and the third metal region is electrically connected with a positive direct current terminal; The fourth metal region is provided with at least one fourth die, and the fourth die comprises the second transistor, a drain of the second transistor is electrically connected with the fourth metal region, and the fourth metal region is electrically connected with an alternating current terminal; The fifth metal region is electrically connected with a negative direct current terminal, and the fifth metal region is electrically connected with a source of the second transistor; The sixth metal region is provided with a fifth die, and the fifth die comprises a second voltage-resistant diode, a cathode of the second voltage-resistant diode is electrically connected with the sixth metal region, and the sixth metal region is electrically connected with a gate of the second transistor; The seventh metal region is provided with a sixth die, and the sixth die comprises a second transient voltage suppression diode, a cathode of the second transient voltage suppression diode is electrically connected with the seventh metal region, and the seventh metal region is electrically connected with a source of the second transistor.

6. The half bridge circuit of claim 5, wherein, A minimum distance between the first metal region and the second metal region along the first direction is less than a minimum distance between the second metal region and the third metal region along the first direction, and / or, a minimum distance between the sixth metal region and the seventh metal region along the first direction is less than a minimum distance between the fifth metal region and the sixth metal region along the first direction.

7. The half bridge circuit of claim 5, wherein, An area of the third metal region is greater than an area of at least one of the first metal region, the second metal region, the sixth metal region and the seventh metal region; An area of the fifth metal region is greater than an area of at least one of the first metal region, the second metal region, the sixth metal region and the seventh metal region.

8. The half-bridge circuit according to claim 5, characterized in that The second metal region comprises a first sub-metal region and at least one second sub-metal region, and the second die is arranged on the second sub-metal region; along the first direction, the first sub-metal region and the second sub-metal region are arranged between the first metal region and the third metal region, the second sub-metal region is provided with a first gate resistor, a first end of the first gate resistor is electrically connected with the second sub-metal region, a second end of the first gate resistor is electrically connected with the first sub-metal region, a cathode of the first voltage-resistant diode is electrically connected with the second sub-metal region, an anode of the first voltage-resistant diode is electrically connected with an anode of the first transient voltage suppression diode, and the second sub-metal region is electrically connected with a gate of the first transistor; The sixth metal region comprises at least one third sub-metal region and a fourth sub-metal region, and the fifth die is arranged on the third sub-metal region; In the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, and a second gate resistor is arranged on the third sub-metal region, a first end of the second gate resistor is electrically connected with the third sub-metal region, and a second end of the second gate resistor is electrically connected with the seventh metal region; The cathode of the second voltage-resistant diode is electrically connected with the third sub-metal region, the anode of the second voltage-resistant diode is electrically connected with the anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected with the gate of the second transistor.

9. The half bridge circuit of claim 4, wherein, The first switch unit comprises a first transistor, the second switch unit comprises a second transistor, and the power module comprises a laminated substrate and a first metal layer; The first metal layer comprises an eighth metal region, a ninth metal region, a tenth metal region, an eleventh metal region and a twelfth metal region; In the first direction of the power module, the eighth metal region, the ninth metal region, the tenth metal region, the eleventh metal region and the twelfth metal region are arranged at intervals; The eighth metal region is provided with a seventh die, and the seventh die comprises a first transient voltage suppression diode, and the cathode of the first transient voltage suppression diode is electrically connected with the eighth metal region; The ninth metal region is provided with at least one eighth die, the eighth die comprises the first transistor, the drain of the first transistor is electrically connected with the ninth metal region, the gate of the first transistor is electrically connected with the eighth metal region, and the ninth metal region is electrically connected with a positive direct current end; The tenth metal region is provided with a ninth die and at least one tenth die, the ninth die comprises a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode is electrically connected with the tenth metal region, the tenth die comprises the second transistor, and the tenth metal region is electrically connected with an alternating current end; The eleventh metal region is provided with an eleventh die, the eleventh die comprises a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode is electrically connected with the eleventh metal region, and the eleventh metal region is electrically connected with a negative direct current end; The twelfth metal region is provided with a twelfth die, the twelfth die comprises a second voltage-resistant diode, the cathode of the second voltage-resistant diode is electrically connected with the twelfth metal region, and the anode of the second voltage-resistant diode is electrically connected with the anode of the second transient voltage suppression diode.

10. The half bridge circuit of claim 4, wherein, The first switch unit comprises a first transistor, the second switch unit comprises a second transistor, and the power module comprises a laminated substrate and a first metal layer; The first metal layer comprises a thirteenth metal region, a fourteenth metal region, a fifteenth metal region, a sixteenth metal region, a seventeenth metal region, an eighteenth metal region, a nineteenth metal region and a twentieth metal region; The thirteenth metal region is electrically connected with an alternating current end; The fourteenth metal region is provided with at least one thirteenth die, the thirteenth die comprising the first transistor, the source of the first transistor being electrically connected with the thirteenth metal region, the drain of the first transistor being electrically connected with the fourteenth metal region, and the fourteenth metal region being electrically connected with the positive voltage DC end; The fifteenth metal region is provided with a fourteenth die, the fourteenth die comprising a first voltage-resistant diode, the cathode of the first voltage-resistant diode being electrically connected with the fifteenth metal region; The sixteenth metal region is provided with a fifteenth die, the fifteenth die comprising a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode being electrically connected with the sixteenth metal region, and the anode of the first transient voltage suppression diode being electrically connected with the anode of the fourteenth die; The seventeenth metal region is electrically connected with the negative voltage DC end; The eighteenth metal region is provided with at least one sixteenth die, the sixteenth die comprising the second transistor, the source of the second transistor being electrically connected with the seventeenth metal region, and the drain of the second transistor being electrically connected with the eighteenth metal region; The nineteenth metal region is provided with a seventeenth die, the seventeenth die comprising a second voltage-resistant diode, the cathode of the second voltage-resistant diode being electrically connected with the nineteenth metal region; The twentieth metal region is provided with an eighteenth die, the eighteenth die comprising a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode being electrically connected with the twentieth metal region, and the anode of the second transient voltage suppression diode being electrically connected with the anode of the second voltage-resistant diode.

11. A power module, characterized by The half-bridge circuit comprises the half-bridge circuit according to any one of claims 1 to 10.

Images