Electronic package

Abstract

An electronic package includes: a carrier structure; the packaging module is arranged on the bearing structure through a plurality of conductive parts, and the packaging module comprises a plurality of circuit layers and a plurality of conductive through holes; wherein the plurality of conductive through holes are electrically connected with the two circuit layers respectively, and the central axis of each conductive through hole deviates from the central axis of each conductive piece. According to the embodiment of the invention, the stress or external force borne by the conductive part can be prevented from being directly transmitted to the conductive through hole to cause the deflection of the conductive through hole and even the failure of the electronic packaging part, so that the reliability of the electronic packaging part can be improved.

Description

Technical Field

[0001] This application relates to a semiconductor packaging technology, and more particularly to an electronic package. Background Technology

[0002] With the evolution of technology, the development trend of electronic products has begun to move towards heterogeneous integration. As a result, multi-chip module (MCM) or multi-chip package (MCP) structures and technologies have gradually emerged. In the process of placing semiconductor devices on a substrate, the active surface of the chip is usually electrically connected to a circuit structure through multiple solder bumps, and multiple conductive elements that can serve as input / output (I / O) terminals are implanted on the other surface of the circuit structure, so that the semiconductor device can be disposed on the substrate through these conductive elements.

[0003] like Figure 1A As shown, a conventional semiconductor package 1 integrates multiple semiconductor chips 10 onto a rewiring structure 11, then encapsulates these semiconductor chips 10 with an encapsulating colloid 15. The rewiring structure 11 is mounted on a packaging substrate 12 via multiple conductive elements 111. This packaging substrate 12 can then be connected to a circuit board (not shown) via multiple solder balls 13. By packaging multiple semiconductor chips 10 into a single structure, the semiconductor package 1 has a greater number of input / output (I / O) endpoints, significantly increasing its computing / processing capabilities and reducing signal transmission delay. Therefore, it can be applied to high-end products with high line density, high transmission speed, high stack-up, and large size designs.

[0004] But, if Figure 1A Region A in the magnified Figure 1B As shown, in the redistribution structure 11 within the aforementioned semiconductor package 1, the conductive vias 112 are often positioned on conductive bumps 14, such as conductive pillars. This causes stress or external forces generated in the lower layer structure to be easily transmitted directly to the conductive vias above them via the conductive bumps 14, resulting in the skewness of these conductive vias. In severe cases, this can even cause the redistribution structure 11 to break, leading to electrical failure of the semiconductor package 1 and reducing the reliability of the semiconductor package 1.

[0005] Therefore, overcoming the various problems of the existing technologies has become a pressing issue that the industry urgently needs to address. Utility Model Content

[0006] In view of the various deficiencies of the prior art, this application provides an electronic package, including: a carrier structure; and a package module disposed on the carrier structure by a plurality of conductive elements, wherein the package module includes a plurality of circuit layers and a plurality of conductive vias; wherein the plurality of conductive vias are electrically connected to two of the circuit layers respectively, and the central axis of each conductive via is offset from the central axis of each conductive element.

[0007] This application also provides a method for manufacturing an electronic package, comprising: providing a package module including multiple circuit layers and multiple conductive vias; and mounting the package module on a support structure via multiple conductive elements, wherein the multiple conductive vias are electrically connected to two of the circuit layers respectively, and the central axis of each conductive via is offset from the central axis of each conductive element.

[0008] In the aforementioned electronic package and its manufacturing method, the projection of each conductive via is completely offset from the cross-section of each conductive component.

[0009] In the aforementioned electronic package and its manufacturing method, each conductive element has a width, and the central axis of the conductive via is offset from the central axis of the conductive element by a distance of 1 / 4 to 1 / 2 of the width.

[0010] In the aforementioned electronic packaging components and their manufacturing methods, the carrier structure is a substrate, an interposer, a lead frame, or a chip.

[0011] In the aforementioned electronic packaging components and their manufacturing methods, each conductive component is cylindrical.

[0012] In the aforementioned electronic package and its manufacturing method, each conductive component further includes a conductive bump.

[0013] In the aforementioned electronic package and its manufacturing method, at least one of the circuit layers is a redistribution layer.

[0014] In the aforementioned electronic package and its manufacturing method, the plurality of circuit layers are electrically connected to the carrier structure through the plurality of conductive elements.

[0015] In the aforementioned electronic package and its manufacturing method, the package module contains at least one semiconductor chip.

[0016] As can be seen from the above, the electronic package and its manufacturing method of this application mainly improve the reliability of the electronic package by designing the central axis of each conductive via to deviate from the central axis of each conductive component. This avoids the stress or external force on the conductive component being directly transmitted to the conductive via, which would cause the conductive via to become skewed or even cause the electronic package to fail. Attached Figure Description

[0017] Figure 1A This is a cross-sectional view of the existing packaging structure.

[0018] Figure 1B for Figure 1A A magnified view of region A in the image.

[0019] Figures 2A to 2C This is a cross-sectional schematic diagram of an embodiment of the manufacturing method of the electronic package of this application.

[0020] Figure 2C-1 This is a partial cross-sectional schematic diagram of another embodiment of the manufacturing method of the electronic package of this application.

[0021] Figure 2C-2 This is a cross-sectional schematic diagram of another embodiment of the manufacturing method of the electronic package of this application.

[0022] Explanation of reference numerals in the attached figures

[0023] 1 Semiconductor package

[0024] 10 Semiconductor chips

[0025] 11 Rewiring Structure

[0026] 111 Conductive Components

[0027] 112,26 Conductive vias

[0028] 12 Packaging substrate

[0029] 13 Welding balls

[0030] 14,251 conductive bumps

[0031] 15 Encapsulating colloid

[0032] 2 Electronic Packages

[0033] 20 Package Module

[0034] 21 Electronic Components

[0035] 21a Active Surface

[0036] 211 Electrical connection pad

[0037] 221, 222, 223, 224 Line Layer

[0038] 23 Dielectric Materials

[0039] 25 Conductive components

[0040] 30 Load-bearing structure

[0041] C1, C2 central axis

[0042] R b width. Detailed Implementation

[0043] The following specific embodiments illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification.

[0044] It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the scope of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this application, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," and "one" used in this specification are merely for clarity of description and are not intended to limit the scope of this application. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this application's implementation.

[0045] Figures 2A to 2C This is a cross-sectional schematic diagram of an embodiment of the manufacturing method of the electronic package of this application.

[0046] First, a packaged module 20 is provided. For example... Figure 2A As shown, the packaging module 20 includes multiple circuit layers 221, 222, 223, and 224 disposed above at least one electronic component 21, and a dielectric material 23 covering the circuit layers 221, 222, 223, and 224. In this embodiment, a semiconductor chip is used as the electronic component 21 for illustration. The electronic component 21 (semiconductor chip) has an active surface 21a, and multiple electrical connection pads 211 are provided on the active surface 21a. The circuit layers 221 are electrically connected to the electronic component 21 through the electrical connection pads 211.

[0047] In this embodiment, four circuit layers 221, 222, 223, and 224 are used as an example of multiple circuit layers, but this is not a limitation. Multiple conductive vias 26 are provided between circuit layers 221 and 222, between circuit layers 222 and 223, and between circuit layers 223 and 224. These conductive vias 26 electrically connect circuit layers 221 and 222, 222 and 223, and 223 and 224, respectively.

[0048] Again Figure 2BAs shown, a plurality of conductive elements 25 are disposed on the circuit layer 224. These conductive elements 25 are electrically connected to the circuit layer 224. The central axis C2 of each conductive element 25 is offset from the central axis C1 of each conductive via 26, that is, each conductive element 25 is not located directly above any conductive via 26.

[0049] like Figure 2C As shown, finally, the formed packaging module 20 is flipped over and its multiple conductive parts 25 are placed on a support structure 30 to obtain the electronic package 2 illustrated in this embodiment.

[0050] In the electronic package 2 manufactured by the above method, the central axis C1 of each conductive via 26 is offset from the central axis C2 of each conductive element 25. Therefore, when the end of any conductive element 25 is subjected to stress or external force, these forces will not be directly transmitted along the conductive element 25 to each conductive via 26, nor will they be transmitted across the circuit layers 224, 223, 222, and 221. This avoids the external force or stress being transmitted through the conductive element 25 to each conductive via 26, causing the conductive via 26 to become misaligned or deformed, thus leading to the failure of the electronic package 2 and resulting in poor reliability.

[0051] The following is a further explanation of the specific implementation details of the manufacturing method of the electronic package 2 of this application.

[0052] like Figure 2B and Figure 2C As shown, in some embodiments, the projection of the conductive via 26 onto the location of the conductive element 25 is completely offset from the cross-section of the conductive element 25. In such a structure, since the conductive via 26 is completely offset from the extension of the cross-section of the conductive element 25, it is most effective in preventing external forces or stresses from being transmitted from the conductive element 25 to the conductive via 26.

[0053] In such Figure 2C-1 In some other embodiments shown, each conductive element 25 may be designed to have a width R. b And the distance by which the central axis C1 of the conductive via 26 deviates from the central axis C2 of the conductive element 25 falls within R. b / 4 to R b The range is between / 2. This design still reduces the degree to which external forces or stresses on the conductive component 25 are directly and completely transmitted to the conductive via 26, thus preventing problems such as skewing. Of course, depending on the condition of different parts, the above two structural designs with different relative positions of the conductive via 26 and the conductive component 25 can be mixed and used in the same electronic package 2. This embodiment does not have any particular limitations in this regard.

[0054] In some embodiments, the support structure 30 is a substrate, such as a silicon substrate, a glass substrate, or a substrate of any other suitable material. Alternatively, the support structure 30 may also be a lead frame or an interposer. The type of support structure 30 depends entirely on the characteristics of the final product and / or the requirements of the manufacturing process, and there are no particular limitations.

[0055] In some other embodiments, the carrier structure 30 is a semiconductor chip, thereby forming a stacked multi-chip package structure.

[0056] In some embodiments, the conductive element 25 may be a copper pillar or other conductive material pillar, such as a square pillar, a cylindrical pillar, or other cross-sectional shapes, or a solder bump. This depends entirely on the mechanical or electrical properties of the final product and / or the requirements of the manufacturing process, and is not specific.

[0057] In some embodiments, each conductive element 25 further includes a conductive bump 251 at its end. The conductive bump 251 is, for example, a solder ball. The package module 20 is attached to the carrier structure 30 via the conductive elements 25 and the conductive bumps 251.

[0058] In some embodiments, at least one of the circuit layers 221, 222, 223, and 224 is a redistribution layer (RDL). In this embodiment, the circuit layers 221, 222, 223, and 224 are formed of a metal such as copper or any other suitable conductive material. Understandably, the circuit layers 221, 222, 223, and 224 may be formed of the same or different materials, depending on the requirements and design; this embodiment does not impose any particular limitations in this regard.

[0059] The dielectric material 23 can be made of polybenzoxazole (PBO), polyimide (PI), prepreg (PP), or any other suitable dielectric material, without any particular limitation.

[0060] In some embodiments, the circuit layer 224 is electrically connected to the carrier structure 30 through the plurality of conductive elements 25.

[0061] In addition to having only one semiconductor chip as its electronic component 21, as shown in the above embodiment, in other embodiments, the packaging module 20 may also have... Figure 2C-2 The diagram shows a plurality of semiconductor chips that serve as electronic components 21, forming a structure such as a multi-chip package (MCP).

[0062] This embodiment also illustrates an electronic package 2, including: a carrier structure 30; and a package module 20, which is disposed on the carrier structure 30 by a plurality of conductive elements 25, and the package module 20 includes a plurality of circuit layers 221, 222, 223, 224 and a plurality of conductive vias 26; wherein the plurality of conductive vias 26 are respectively located between circuit layers 221 and 222, between circuit layers 222 and 223, and between circuit layers 223 and 224 and are electrically connected to circuit layers 221 and 222, circuit layers 222 and 223, and circuit layers 223 and 224, and the central axis C1 of each conductive via 26 is offset from the central axis C2 of each conductive element 25.

[0063] In some embodiments, the projection of the conductive via 26 is completely off-center from the cross-section of the conductive element 25.

[0064] In some embodiments, each of the conductive elements 25 has a width R. b Furthermore, the distance by which the central axis C1 of the conductive via 26 deviates from the central axis C1 of the conductive element 25 is within R. b / 4 to R b Within the range of / 2.

[0065] In some embodiments, the support structure 30 is a substrate, an intermediate plate, or a lead frame.

[0066] In some embodiments, the carrier structure 30 is a chip.

[0067] In some embodiments, the conductive element 25 is columnar.

[0068] In some embodiments, the conductive element 25 further includes a conductive bump 251.

[0069] In some embodiments, at least one of the line layers 221, 222, 223, and 224 is a redistribution layer.

[0070] In some embodiments, the circuit layer 224 is electrically connected to the carrier structure 30 through the plurality of conductive elements 25.

[0071] In some embodiments, the packaging module 20 contains at least one semiconductor chip.

[0072] In summary, the electronic package 2 and its manufacturing method of this application mainly improve the reliability of the electronic package 2 by designing the central axis C1 of each conductive via 26 to deviate from the central axis C2 of each conductive element 25. This avoids the stress or external force on the conductive element 25 being directly transmitted to the conductive via 26, which would cause the conductive via 26 to become skewed or even cause the electronic package 2 to fail.

[0073] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be as set forth in the claims.

Claims

1. An electronic package, characterized in that, include: Load-bearing structure; as well as The encapsulation module is disposed on the carrier structure through multiple conductive components, and the encapsulation module includes multiple circuit layers and multiple conductive vias; The plurality of conductive vias are electrically connected to the two circuit layers respectively, and the central axis of each conductive via is offset from the central axis of each conductive component.

2. The electronic package as described in claim 1, characterized in that, The projection of each conductive via is completely offset from the cross-section of each conductive element.

3. The electronic package as described in claim 1, characterized in that, Each of the conductive elements has a width, and the central axis of the conductive via is offset from the central axis of each conductive element by a distance of 1 / 4 to 1 / 2 of the width.

4. The electronic package as described in claim 1, characterized in that, The supporting structure can be a substrate, an interposer, a lead frame, or a chip.

5. The electronic package as described in claim 1, characterized in that, Each of these conductive components is columnar.

6. The electronic package as claimed in claim 1, characterized in that, Each conductive element further includes a conductive bump.

7. The electronic package as claimed in claim 1, characterized in that, At least one of the line layers is a rewiring layer.

8. The electronic package as claimed in claim 1, characterized in that, The multiple circuit layers are electrically connected to the supporting structure through the multiple conductive elements.

9. The electronic package as claimed in claim 1, characterized in that, The package module contains at least one semiconductor chip.

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