Double-channel power supply modulator integrated with driving chip

Abstract

The utility model provides a dual-path power supply modulator integrated with a driving chip, and aims to solve the problems of complex structure and low integration level of a dual-path power supply modulator in the prior art. The chip comprises a first metal substrate, a second metal substrate, a third metal substrate, a driving chip located on the first metal substrate, a P-type metal-oxide-semiconductor field effect transistor located on the second metal substrate, a P-type metal-oxide-semiconductor field effect transistor located on the third metal substrate, and eight pins. After two external logic control signals pass through the driving chip, two anti-phase / in-phase driving signals are respectively output, and the driving signals respectively control the on and off of the two P-channel power MOSFETs, so that a double-path independent power supply modulation function is realized, compared with the prior art, one driving chip is reduced on the hardware structure, and the function is ensured; not only is the miniaturization design of the radio frequency receiver system realized, but also the cost of the system is reduced.

Description

Technical Field

[0001] This utility model relates to the field of power modulator technology, and in particular to a dual-channel power modulator with an integrated driver chip. Background Technology

[0002] In an RF transceiver system, the transmitter uses an RF power amplifier, and the receiver uses a low-noise amplifier. To enable the transmitter and receiver to work alternately, a power MOSFET is commonly used as a power switch to control the switching on and off of the power supply to the RF power amplifier and the low-noise amplifier.

[0003] In GaAs power amplifier applications, due to the relatively low operating voltage, a P-channel MOSFET is typically used as the switching power modulator structure for ease of use. This power modulator, composed of a power MOSFET chip and a high-speed MOSFET driver chip, controls the GaAs power amplifier and low-noise amplifier. The circuit diagram is shown below. Figure 1 As shown. After the control signal IN1 passes through the drive circuit 1, it generates a drive signal that is inverted by IN1, which drives the power transistor MOSFET1, thereby controlling the power amplifier power supply to be turned on and off; after the control signal IN2 passes through the drive circuit 2, it generates a drive signal that is inverted by IN2, which drives the power transistor MOSFET2, thereby controlling the low noise amplifier power supply to be turned on and off.

[0004] To enable alternating operation of the power amplifier and low-noise amplifier, two power modulator circuits are required. This is typically achieved using two power MOSFETs and two driver chips. With the increasing miniaturization of transceiver systems, improving system integration is becoming increasingly important, and the most common method for enhancing system integration is through multi-chip packaging technology. Utility Model Content

[0005] This application addresses the shortcomings of the prior art by providing a dual-channel power modulator integrated with a driver chip. The modulator includes two P-channel power MOSFETs and a dual-channel MOSFET driver chip. Two external logic control signals pass through the driver chip and output two inverting / non-inverting drive signals, which control the on and off states of the two P-channel power MOSFETs, thereby achieving dual-channel independent power modulation. Compared with the prior art, this application reduces the number of driver chips in the hardware structure while maintaining functionality.

[0006] The technical solution adopted in this utility model is as follows:

[0007] This utility model provides a dual-channel power modulator with an integrated driver chip, including a first metal substrate, a second metal substrate, a third metal substrate, a driver chip located on the first metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, and eight pins, including an A-channel logic input pin, a B-channel logic input pin, an A-channel modulation output pin, a B-channel modulation output pin, a driver power supply voltage pin, an A-channel power supply voltage pin, a B-channel power supply voltage pin, and a ground pin;

[0008] The first metal substrate is connected to the ground pin, the second metal substrate is connected to the A-channel modulation output pin, and the third metal substrate is connected to the B-channel modulation output pin; the plurality of metal pads in the driver chip are respectively connected to the A-channel logic input pin, the B-channel logic input pin, the driver power supply voltage pin, the ground pin, the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate;

[0009] When the dual-channel power modulator is connected to the controller, the dual-channel power modulator obtains the power supply voltage through the driver power supply voltage pin, the A-channel power supply voltage pin, and the B-channel power supply voltage pin. It receives the A-channel logic level input by the controller through the A-channel logic input pin and the B-channel logic level input by the controller through the B-channel logic input pin. After processing the A-channel logic level and the B-channel logic level through the driver chip, the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, the output is sent to the load through the A-channel modulation output pin and the B-channel modulation output pin, respectively.

[0010] Furthermore, the drain of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate is connected to the second metal substrate via conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel power supply voltage pin via a metal wire connection; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel drive output terminal OUTA of the driver chip via a metal wire connection.

[0011] Furthermore, the drain of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate is connected to the third metal substrate via conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-channel power supply voltage pin via a metal wire connection; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-channel drive output terminal OUTB of the driver chip via a metal wire connection.

[0012] Furthermore, the first metal substrate is connected to the ground pin via a metal frame connection; the second metal substrate is connected to the A-channel modulation output pin via a metal frame connection; and the third metal substrate is connected to the B-channel modulation output pin via a metal frame connection.

[0013] Furthermore, the driver chip includes an input circuit, a level conversion circuit, and a driving circuit.

[0014] Furthermore, the logic level input by the A-path logic input pin is processed sequentially by the input circuit, the level conversion circuit, and the driving circuit to obtain the A-path driving output signal. The A-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate.

[0015] Furthermore, the logic level input by the B-path logic input pin is processed sequentially by the input circuit, the level conversion circuit, and the driving circuit to obtain the B-path driving output signal. The B-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate.

[0016] Furthermore, when the logic level input to the logic input pin is low, the output pin outputs a high impedance.

[0017] When the logic level input to the logic input pin is high, the output pin outputs a high level.

[0018] When the logic level input to the B-path logic input pin is low, the output pin of the B-path output pin outputs a high level.

[0019] When the logic level input to the B-path logic input pin is high, the output pin of the B-path outputs high impedance.

[0020] The beneficial effects of this utility model are as follows:

[0021] Compared to existing technologies, the dual-channel power modulator provided by this utility model includes two P-channel power MOSFETs and a dual-channel MOSFET driver chip. After two external logic control signals pass through the driver chip, they output two inverted / non-inverted drive signals, which control the conduction and turn-off of the two P-channel power MOSFETs respectively, thereby realizing dual-channel independent power modulation function. Compared with existing technologies, it reduces one driver chip in hardware structure while ensuring functionality; it not only helps to realize the miniaturization design of RF receiver systems, but also helps to reduce system costs. Attached Figure Description

[0022] Figure 1 A schematic diagram of the circuit structure of a power modulator in the prior art;

[0023] Figure 2 This is a schematic diagram of the circuit structure of the dual-power modulator in this utility model;

[0024] Figure 3 This is a schematic diagram of the dual-power modulator in this utility model;

[0025] Figure 4 This is a schematic diagram of the external circuit of the dual-power modulator in this utility model;

[0026] Figure 5 This is a logic diagram showing the input-output relationship of the dual-power modulator in this utility model. Detailed Implementation

[0027] The specific embodiments of this utility model are described below with reference to the accompanying drawings.

[0028] This invention provides a dual-power modulator with an integrated driver chip, aiming to solve the problems of insufficient compactness and low integration of existing dual-power modulators.

[0029] like Figures 1 to 5 As shown, this utility model includes a first metal substrate, a second metal substrate, a third metal substrate, a driver chip located on the first metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, and eight pins, including an A-channel logic input pin, a B-channel logic input pin, an A-channel modulation output pin, a B-channel modulation output pin, a driver power supply voltage pin, an A-channel power supply voltage pin, a B-channel power supply voltage pin, and a ground pin;

[0030] The first metal substrate is connected to the ground pin, the second metal substrate is connected to the A-channel modulation output pin, and the third metal substrate is connected to the B-channel modulation output pin; the plurality of metal pads in the driver chip are respectively connected to the A-channel logic input pin, the B-channel logic input pin, the driver power supply voltage pin, the ground pin, the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate;

[0031] When the dual-channel power modulator is connected to the controller, the dual-channel power modulator obtains the power supply voltage through the driver power supply voltage pin, the A-channel power supply voltage pin, and the B-channel power supply voltage pin. It receives the A-channel logic level input by the controller through the A-channel logic input pin and the B-channel logic level input by the controller through the B-channel logic input pin. After processing the A-channel logic level and the B-channel logic level through the driver chip, the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, the output is sent to the load through the A-channel modulation output pin and the B-channel modulation output pin, respectively.

[0032] In one embodiment of this utility model, the drain of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate is connected to the second metal substrate by conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel power supply voltage pin by metal wire connection; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel drive output terminal OUTA of the driver chip by metal wire connection.

[0033] In one embodiment of this utility model, the drain of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate is connected to the third metal substrate via conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-path power supply voltage pin via a metal wire connection; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-path drive output terminal OUTB of the driver chip via a metal wire connection.

[0034] In one embodiment of this utility model, the first metal substrate is connected to the grounding pin via a metal frame connection.

[0035] In one embodiment of this utility model, the second metal substrate is connected to the A-channel modulation output pin via a metal frame connection; the third metal substrate is connected to the B-channel modulation output pin via a metal frame connection.

[0036] In one embodiment of this utility model, the driver chip includes an input circuit, a level conversion circuit, and a driver circuit.

[0037] In one embodiment of this utility model, the logic level input by the A-path logic input pin is processed sequentially by the input circuit, the level conversion circuit and the driving circuit to obtain the A-path driving output signal. The A-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate.

[0038] In one embodiment of this utility model, the logic level input by the B-path logic input pin is processed sequentially by the input circuit, the level conversion circuit and the driving circuit to obtain the B-path driving output signal. The B-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate.

[0039] In one embodiment of this utility model, when the logic level input to the logic input pin is low, the output pin outputs high impedance.

[0040] When the logic level input to the logic input pin is high, the output pin outputs a high level.

[0041] When the logic level input to the B-path logic input pin is low, the output pin of the B-path output pin outputs a high level.

[0042] When the logic level input to the B-path logic input pin is high, the output pin of the B-path outputs high impedance.

[0043] The specific structure and working principle of this utility model are as follows:

[0044] The present invention includes, in terms of structure, a first metal substrate, a second metal substrate, a third metal substrate, a driver chip located on the first metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, and eight pins, including an A-channel logic input pin, a B-channel logic input pin, an A-channel modulation output pin, a B-channel modulation output pin, a driver power supply voltage pin, an A-channel power supply voltage pin, a B-channel power supply voltage pin, and a ground pin.

[0045] like Figure 4 The working principle of the integrated dual-channel power supply modulator circuit shown is as follows: (1) When the external logic input INA is logic "0", the output terminal OUT_A of the drive circuit is an inverted output, outputting logic "1", and the A-channel MOS transistor M1 is turned off; when the external logic input INA is logic "1", the output terminal OUT_A of the drive circuit is an inverted output, outputting logic "0", and the A-channel MOS transistor M1 is turned on. (2) When the external logic input INB is logic "0", the output terminal OUT_B of the drive circuit is a non-inverted output, outputting logic "0", and the B-channel MOS transistor M2 is turned on; when the external logic input INB is logic "1", the output terminal OUT_B of the drive circuit is a non-inverted output, outputting logic "0", and the B-channel MOS transistor M2 is turned off.

[0046] The above description is an explanation of the present utility model and not a limitation thereof. The scope of the present utility model is defined by the claims. Within the protection scope of the present utility model, any form of modification may be made.

Claims

1. A dual-power modulator integrating a driver chip, characterized in that: It includes a first metal substrate, a second metal substrate, a third metal substrate, a driver chip located on the first metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, a P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, and eight pins, the eight pins including an A-way logic input pin, a B-way logic input pin, an A-way modulation output pin, a B-way modulation output pin, a driver power supply voltage pin, an A-way power supply voltage pin, a B-way power supply voltage pin, and a ground pin; The first metal substrate is connected to the ground pin, the second metal substrate is connected to the A-channel modulation output pin, and the third metal substrate is connected to the B-channel modulation output pin; the plurality of metal pads in the driver chip are respectively connected to the A-channel logic input pin, the B-channel logic input pin, the driver power supply voltage pin, the ground pin, the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the gate of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate; When the dual-channel power modulator is connected to the controller, the dual-channel power modulator obtains the power supply voltage through the driver power supply voltage pin, the A-channel power supply voltage pin, and the B-channel power supply voltage pin. It receives the A-channel logic level input by the controller through the A-channel logic input pin and the B-channel logic level input by the controller through the B-channel logic input pin. After processing the A-channel logic level and the B-channel logic level through the driver chip, the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate, and the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate, the output is sent to the load through the A-channel modulation output pin and the B-channel modulation output pin, respectively.

2. The dual-power modulator with integrated driver chip as described in claim 1, characterized in that: The drain of the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate is connected to the second metal substrate via conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel power supply voltage pin via a metal wire; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the second metal substrate is connected to the A-channel drive output terminal OUTA of the driver chip via a metal wire.

3. The dual-power modulator integrating a driver chip as described in claim 1, characterized in that: The drain of the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate is connected to the third metal substrate via conductive adhesive; the source of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-channel power supply voltage pin via a metal wire; and the gate of the P-type metal-oxide-semiconductor field-effect transistor on the third metal substrate is connected to the B-channel drive output terminal OUTB of the driver chip via a metal wire.

4. A dual-power modulator integrating a driver chip as described in claim 1, characterized in that: The first metal substrate is connected to the ground pin via a metal frame connection; the second metal substrate is connected to the A-channel modulation output pin via a metal frame connection; and the third metal substrate is connected to the B-channel modulation output pin via a metal frame connection.

5. A dual-power modulator integrating a driver chip as described in claim 1, characterized in that: The driver chip includes an input circuit, a level conversion circuit, and a driver circuit.

6. A dual-power modulator integrating a driver chip as described in claim 5, characterized in that: The logic level input from the A-path logic input pin is processed sequentially by the input circuit, the level conversion circuit, and the driving circuit to obtain the A-path driving output signal. The A-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the second metal substrate.

7. A dual-power modulator integrating a driver chip as described in claim 5, characterized in that: The logic level input from the B-path logic input pin is processed sequentially by the input circuit, the level conversion circuit, and the driving circuit to obtain the B-path driving output signal. The B-path driving output signal is output to the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate to drive the P-type metal-oxide-semiconductor field-effect transistor located on the third metal substrate.

8. A dual-power modulator integrating a driver chip as described in claim 1, characterized in that: When the logic level input to the logic input pin is low, the output pin outputs high impedance. When the logic level input to the logic input pin is high, the output pin outputs a high level. When the logic level input to the B-path logic input pin is low, the output pin of the B-path output pin outputs a high level. When the logic level input to the B-path logic input pin is high, the output pin of the B-path outputs high impedance.

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