Three-level wind power converter power unit efficiency optimization circuit

By optimizing the power unit efficiency optimization circuit of the three-level wind power converter, the problem of the inability to reduce the driving resistance of the switching transistor was solved, thereby reducing losses and heat dissipation costs, and improving device utilization and system reliability.

CN223652156UActive Publication Date: 2025-12-09天津瑞源电气有限公司
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Patent Information

Application Number
CN202520274840.0
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-02-20
Publication Date
2025-12-09
Estimated Expiration
2035-02-20

AI Technical Summary

Technical Problem

In existing three-level wind power converters, the driving resistance of the switching transistors cannot be further reduced, and the losses cannot be reduced, which leads to increased device stress and heat dissipation requirements, limiting power density and cost optimization.

Method used

Design a three-level wind power converter power unit efficiency optimization circuit. By adjusting the components and control circuit, optimize the driving of the switching transistor, reduce switching losses, improve device utilization, and take into account device stress and heat dissipation requirements.

Benefits of technology

This reduces switching losses of the switching transistors, improves device utilization, lowers heat dissipation costs, and enhances system reliability.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model discloses a three-level wind power converter power unit efficiency optimization circuit comprising a drive circuit, a main power circuit, a sampling circuit and a control circuit. The driving circuit comprises a positive power pack, a negative power pack, a triode and a regulation and control assembly arranged between the positive power pack and the negative power pack. The regulation and control assembly comprises a plurality of groups of resistor strings connected in parallel, each resistor string comprises a plurality of resistors, a switch tube is arranged between the connected resistors, and a switch tube is also arranged between the resistor string and the negative power supply group; the control circuit controls a switch tube in a resistor string of the drive circuit according to information fed back by the sampling circuit. According to the utility model, the switching loss of the switching tube is minimized through an automatic optimization mode, the device stress is considered, the heat dissipation problem is solved, and the system cost is reduced.
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Description

Technical Field

[0001] This utility model belongs to the technical field of three-level wind power converters, specifically relating to an efficiency optimization circuit for the power unit of a three-level wind power converter. Background Technology

[0002] With the development of the wind power industry, the power density of wind power converters is getting higher and higher, and the cost is getting lower and lower. According to the traditional three-level topology controlled by the drive circuit, the drive resistance of the switching tube cannot be further reduced due to the stress of the components, and the loss cannot be reduced to the minimum. In order to balance the stress of the components and heat dissipation, the current utilization rate of the switching tube cannot be increased, which means that to achieve the same power output, higher-specification semiconductor devices are required, as well as greater heat dissipation capacity. Utility Model Content

[0003] This utility model is proposed to overcome the shortcomings of the existing technology, and its purpose is to provide an efficiency optimization circuit for a three-level wind power converter power unit.

[0004] This utility model is achieved through the following technical solution:

[0005] A three-level wind power converter power unit efficiency optimization circuit includes a drive circuit, a main power circuit, a sampling circuit, and a control circuit. The drive circuit includes a positive power supply group, a negative power supply group, transistors, and a control component disposed between the positive and negative power supply groups. The control component includes multiple sets of resistor strings connected in parallel, each resistor string including multiple resistors, with a switch transistor disposed between the connected resistors, and a switch transistor also disposed between the resistor string and the negative power supply group. The control circuit controls the switch transistors in the resistor strings of the drive circuit based on information fed back from the sampling circuit.

[0006] In the above technical solution, the positive power supply group includes at least one positive power supply, and the voltage of the positive power supply is 15V or 5V; when the positive power supply group includes multiple positive power supplies, the voltages of the multiple positive power supplies can be different; the negative power supply group includes at least one negative power supply, and the voltage of the negative power supply is -10V or 0V; when the negative power supply group includes multiple negative power supplies, the voltages of the multiple negative power supplies can be different.

[0007] In the above technical solution, the resistor string includes a positive voltage side resistor and a negative voltage side resistor connected in series. An intermediate switch is provided between the positive voltage side resistor and the negative voltage side resistor. A negative voltage side switch is provided between the negative voltage side resistor and the negative power supply group. The base of a transistor is connected between the intermediate switch and the negative voltage side resistor.

[0008] In the above technical solution, the output terminal of the control component is connected to the base VTX of the transistor (representing a semiconductor device with switching function), where VTX represents VT1 to VT5 in the power topology, and the collector and emitter of the transistor are connected according to the power topology.

[0009] In the above technical solution, the main power circuit is a DC-DC conversion power topology.

[0010] In the above technical solution, the current sampling circuit includes a current sampler and an inductor connected in series. The current sampler is a Hall switch and is located at the front or rear end of the inductor. The voltage sampling circuit is a circuit that uses a resistor divider to divide the voltage.

[0011] The beneficial effects of this utility model are:

[0012] This invention provides an efficiency optimization circuit for a three-level wind power converter power unit. By automatically optimizing the circuit, the switching losses of the switching transistors are minimized. At the same time, it can take into account the stress of the components, improve the utilization rate of the components, reduce the heat dissipation cost, and improve the reliability of the system. Attached Figure Description

[0013] Figure 1 This is the circuit diagram of this utility model;

[0014] Figure 2 This is a schematic diagram of the switching process drive control of the switching transistor of this utility model;

[0015] Figure 3 This is a schematic diagram of the drive control for the turn-off process of the switching transistor according to this utility model;

[0016] Figure 4 This is a circuit diagram of the voltage sampling circuit in this utility model;

[0017] Figure 5 This is the circuit diagram of the control circuit in this utility model.

[0018] For those skilled in the art, other related figures can be obtained from the above figures without any creative effort. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solution of this utility model, the technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.

[0020] like Figure 1 As shown, a three-level wind power converter power unit efficiency optimization circuit includes a drive circuit 1, a main power circuit 2, a sampling circuit 3, and a control circuit 4.

[0021] The driving circuit 1 includes a positive power supply group, a negative power supply group, transistors, and a regulating component disposed between the positive power supply group and the negative power supply group. The positive power supply group includes at least one positive power source, the voltage of which is 15V or 5V. When the positive power supply group includes multiple positive power sources, the voltages of the multiple positive power sources can be different. The negative power supply group includes at least one negative power source, the voltage of which is -10V or 0V. When the negative power supply group includes multiple negative power sources, the voltages of the multiple negative power sources can be different. The regulating component includes multiple sets of resistor strings connected in parallel, each resistor string including multiple resistors. A switching transistor Q is disposed between the connected resistors, and a switching transistor Q is also disposed between the resistor strings and the negative power supply group. The switching transistors of the regulating component are designated Q1, Q2...Q. n Q 11 Q 22 Q nn ;

[0022] The resistor string includes a positive voltage side resistor and a negative voltage side resistor connected in series. An intermediate switch is set between the positive voltage side resistor and the negative voltage side resistor. A negative voltage side switch is set between the negative voltage side resistor and the negative power supply group. The intermediate switch and the negative voltage side resistor form the output terminal, which is connected to the base of the transistor.

[0023] The output terminal of the control component is connected to the base VTX of the transistor (representing a semiconductor device with switching function), where VTX represents VT1 to VT5 in the power topology. The collector and emitter of the transistor are connected according to the power topology.

[0024] The driving circuit can achieve different positive current output capabilities by controlling different combinations of switching transistors, and can also achieve different negative current input capabilities by controlling different combinations of switching transistors; the driving circuit can achieve different driving capabilities at different time periods during the driving turn-on or turn-off process.

[0025] The main power circuit 2 is a common DC-DC conversion power topology; the DC-DC conversion power topology includes a two-level circuit; the DC-DC conversion power topology is a type I ANPC and NPC three-level topology or a type T three-level topology; the main power circuit 2 includes capacitors, switching devices, reactance and other devices required for DC-DC conversion, and each switching device can be freely controlled by the driving circuit.

[0026] In this embodiment, the main power circuit 2 is a common non-isolated DC-DC topology, including type I three-level, type T three-level, H-bridge, flying capacitor topology, etc.

[0027] The sampling circuit 3 is either a current sampling circuit or a voltage sampling circuit; the current sampling circuit includes a current sampler and an inductor connected in series, the current sampler being a Hall switch, and the current sampler being located at the front or rear end of the inductor; the voltage sampling circuit is a differential voltage sampling circuit, such as... Figure 4 As shown.

[0028] The information collected by the sampling circuit 3 is the current or the VCE voltage of VTX;

[0029] like Figure 5 As shown, the control circuit 4 includes one or more control chips, which can realize AD conversion and also output multiple PWM waves. Based on the information fed back from the sampling circuit 3, it controls Q1, Q2...Q in the drive circuit 1. n Q 11 Q 22 Q nn .

[0030] The control circuit determines the required drive waveform pattern based on the voltage and current magnitudes during the switching process of the switching transistors, and then determines the waveform generation timing relationship based on the drive waveform pattern; Q1, Q2...Q n Q 11 Q 22 Q nn In practice, the timing relationship of the wave generation can be determined by fitting curves based on the datasheets of different devices, or by fitting curves based on a large amount of double-pulse data or by looking up tables.

[0031] The working principle of this utility model:

[0032] This invention is based on the fundamental characteristics of semiconductor device switches, such as... Figure 2 , 3 As shown, Figure 2 During the turn-on process, in the first stage from negative voltage to the threshold voltage, the drive voltage can rise as quickly as possible. In the second stage, from the threshold voltage to the Miller plateau, the current gradually increases, and the VCE voltage is initially maintained before decreasing. Increasing the drive current in this stage allows the device to quickly traverse the Miller plateau region during turn-on, reducing the overlap time and area between current and voltage. In the third stage, the voltage drops rapidly to the point of current overshoot or reverse recovery, requiring a reduction in drive current and voltage. This controls dV / dt and the magnitude of current overshoot or reverse recovery current, reducing the resonant energy of the power circuit or reverse recovery losses. The magnitude of the drive current throughout the process can be controlled by adjusting Q. 11 ~Q nn The magnitude of the drive current is controlled by switching several tubes and series resistors on or off.

[0033] Q 11 ~Q nnThe value of the series resistor can be selected according to the needs.

[0034] Figure 3 The turn-off process, unlike the turn-on process, also has three stages. The magnitude of the drive current throughout the process can be controlled by Q1 to Q2. n The magnitude of the drive current is controlled by switching several transistors and series resistors on or off; Q 11 ~Q nn The value of the series resistor can be selected according to the needs.

[0035] Q1~Q n and Q 11 ~Q nn The following methods can be used to combine and activate services:

[0036] (1) The control circuit can freely control Q1 to Q2. n and Q 11 ~Q nn The turn-on and turn-off times were determined by a double-pulse test to obtain Q1 to Q2 under different current magnitudes. n and Q 11 ~Q nn The on / off times and resistance values ​​can be combined; for double-pulse testing, an automated testing platform can be designed, using big data optimization, and the computer will ultimately provide the optimal combination, presented in the form of a list or fitted function. Alternatively, the on / off times can also be implemented using a fitted function based on the actual device model.

[0037] (2) The control circuit can control Q1 to Q2 by searching a list or calling a fitting function based on the real-time operating current read by the sampling circuit. n and Q 11 ~Q nn The on and off times are precisely controlled to ensure that every switching action during the operation of the entire machine is at the optimal speed.

[0038] It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0039] The applicant declares that the above description is only a specific embodiment of the present utility model, but the protection scope of the present utility model is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present utility model fall within the protection and disclosure scope of the present utility model.

Claims

1. A power unit efficiency optimization circuit for a three-level wind power converter, characterized in that: It includes a driving circuit (1), a main power circuit (2), a sampling circuit (3), and a control circuit (4); the driving circuit (1) includes a positive power supply group, a negative power supply group, a transistor, and a regulating component disposed between the positive power supply group and the negative power supply group; the regulating component includes multiple sets of resistor strings connected in parallel, each resistor string including multiple resistors, a switching transistor disposed between the connected resistors, and a switching transistor disposed between the resistor string and the negative power supply group; the control circuit (4) controls the switching transistor in the resistor string of the driving circuit (1) according to the information fed back by the sampling circuit (3).

2. The efficiency optimization circuit for the power unit of a three-level wind power converter according to claim 1, characterized in that: The positive power supply group includes at least one positive power supply, the voltage of which is 15V or 5V; when the positive power supply group includes multiple positive power supplies, the voltages of the multiple positive power supplies may be different; the negative power supply group includes at least one negative power supply, the voltage of which is -10V or 0V; when the negative power supply group includes multiple negative power supplies, the voltages of the multiple negative power supplies may be different.

3. The efficiency optimization circuit for the power unit of a three-level wind power converter according to claim 1, characterized in that: The resistor string includes a positive voltage side resistor and a negative voltage side resistor connected in series. An intermediate switch is set between the positive voltage side resistor and the negative voltage side resistor. A negative voltage side switch is set between the negative voltage side resistor and the negative power supply group. The base of a transistor is connected between the intermediate switch and the negative voltage side resistor.

4. The efficiency optimization circuit for the power unit of a three-level wind power converter according to claim 1, characterized in that: The output terminal of the control component is connected to the base VTX of the transistor, and the collector and emitter of the transistor are connected according to the power topology.

5. The efficiency optimization circuit for the power unit of a three-level wind power converter according to claim 1, characterized in that: The main power circuit (2) is a DC-DC power conversion topology.

6. The efficiency optimization circuit for the power unit of a three-level wind power converter according to claim 1, characterized in that: The current sampling circuit includes a current sampler and an inductor connected in series. The current sampler is a Hall switch and is located at the front or rear end of the inductor. The voltage sampling circuit is a circuit that uses a resistor divider to divide the voltage.