SiC MOSFET device with L-shaped gate oxide structure

Abstract

The utility model discloses a SiC MOSFET device with an L-shaped gate oxide structure, and relates to the technical field of semiconductors. Comprising a drain metal layer, an N + substrate layer, an N-type buffer layer, an N-drift layer, a source ohmic contact alloy layer and a source metal layer which are sequentially arranged from bottom to top, an N-region, a P-well region, an NP region, a PP region, a P + region, a gate bottom oxide layer, a gate oxide layer and a Poly layer are arranged in the N-drift layer; the reliability of the gate oxide bottom is remarkably improved under the condition that the on resistance of the device is not influenced by the gate bottom oxide layer, and the Crss stray capacitance of the chip can be reduced by the gate bottom oxide layer, so that the high-frequency application of the device is facilitated; and the P + region is utilized to shield the electric field at the bottom of the gate oxide, so that the gate oxide reliability can be further improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor, especially to SiC MOSFET device with L type gate oxide structure. BACKGROUND

[0002] SiC MOSFET has the characteristics of low on-resistance, high frequency and high voltage, and is widely used in electric vehicles, rail transit, smart grid and other fields, and has become one of the hot spots of current power device research. However, compared with Si IGBT, the defect density of SiC / SiO2 interface is 1-2 orders of magnitude higher than that of Si / SiO2. The high defect density will cause a significant decrease in gate oxide quality, causing serious reliability problems in the actual application of the device, which has become a key bottleneck for the large-scale practical application of SiC MOSFET devices.

[0003] SiC MOSFET is divided into planar and trench types. Although the planar SiC MOS process is simple, the cell consistency is good, and the avalanche energy is high. However, when the current is limited in the narrow N region near the P body region, JFET effect will occur when flowing through, increasing the on-state resistance, and the parasitic capacitance is large. Therefore, how to solve the SiC MOSFET gate oxide quality, JFET effect and parasitic capacitance is a technical problem that needs to be solved at present. UTILITARY MODEL CONTENT

[0004] In view of the above problems, the utility model provides a kind of SiC MOSFET device with L type gate oxide structure for improving the reliability of gate oxide bottom and reducing chip Crss parasitic capacitance.

[0005] The technical scheme of the utility model is:

[0006] SiC MOSFET device with L type gate oxide structure, including from bottom to top sequentially arranged drain metal layer, N + Substrate layer, N - Drift layer, source ohmic contact alloy layer and source metal layer;

[0007] N - Drift layer is equipped with:

[0008] N - Region, from the top surface of N - Drift layer extends downward;

[0009] P-well region, is equipped with several, respectively from the top surface of N - Region extends downward;

[0010] NP region, is equipped with several, respectively from the top surface of P-well region extends downward;

[0011] PP region, several are provided, respectively from the top surface of the P-well region downwardly extending, located in the side of the NP region;

[0012] P + Region, located in the N - Region, the bottom surface is connected with the N - Drift layer;

[0013] Gate bottom oxide layer, located in the top surface of the P + Region;

[0014] Gate oxide layer, provided with a pair, respectively sequentially through the NP region, P-well region and N - Region top surface downwardly extending to the top surface of the gate bottom oxide layer;

[0015] Poly layer, covers the top surface of the gate bottom oxide layer and gate oxide layer;The top surface of the Poly layer is provided with a dielectric layer (13), and the side portion of the dielectric layer extends downward to the top surface of the NP region.

[0016] Specifically, the thickness of the N - Drift layer is 5-15um.

[0017] Specifically, the thickness of the gate oxide layer is between 40-60nm.

[0018] Specifically, the thickness of the gate bottom oxide layer is between 200-500nm.

[0019] Specifically, the cross section of the gate oxide layer is L-shaped structure.

[0020] Specifically, the NP region and the N - Region are provided with a spacing.

[0021] The utility model improves SiC MOSFET device gate oxygen quality:

[0022] Gate oxygen structure first step utilizes the depositing process to form the gate bottom oxide layer, then second step utilizes dry oxygen thermal oxidation process to form the gate oxide layer structure.Gate bottom oxide layer can significantly improve the reliability of the gate oxygen bottom under the condition of not affecting the on-resistance of the device, and the gate bottom oxide layer can also reduce the Crss parasitic capacitance of the chip, which is beneficial to the high-frequency application of the device;Then utilize P + Region shielding electric field of the gate oxygen bottom, can further improve the reliability of the gate oxygen.

[0023] The utility model improves the JEFT region current-carrying capacity of SiC MOSFET device:

[0024] The L-shaped gate oxide layer is adopted, the horizontal part of the gate oxide layer is responsible for the channel switch and is the same as the conventional device structure, but the vertical part of the gate electrode can attract electrons to gather and increase the carrier concentration of the JEFT area in the opening process, the through-flow capacity is improved, and the JEFT effect in the working state is improved; in the turn-off process, the vertical part of the gate electrode can repel electrons, the concentration of the N - area is reduced, and the leakage between the source electrode and the drain electrode is also reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is the structure schematic diagram of step S100 of the utility model;

[0026] Figure 2 is the structure schematic diagram of step S200 of the utility model;

[0027] Figure 3 is the structure schematic diagram of step S300 of the utility model;

[0028] Figure 4 is the structure schematic diagram of step S400 of the utility model;

[0029] Figure 5 is the structure schematic diagram of step S500 of the utility model;

[0030] Figure 6 is the structure schematic diagram of step S600 of the utility model;

[0031] Figure 7 is the structure schematic diagram of step S700 of the utility model;

[0032] Figure 8 is the structure schematic diagram of step S800 of the utility model;

[0033] Figure 9 is the structure schematic diagram of step S900 of the utility model;

[0034] Figure 10 is the structure schematic diagram of step S1000 of the utility model;

[0035] Figure 11 is the structure schematic diagram of step S1100 of the utility model;

[0036] Figure 12 is the structure schematic diagram of step S1200 of the utility model;

[0037] Figure 13 is the structure schematic diagram of step S1300 of the utility model;

[0038] Figure 14 is the structure schematic diagram of step S1400 of the utility model;

[0039] Figure 15 is the structural schematic diagram of the step S1500 of the utility model;

[0040] Fig. 1 is N + Substrate layer, 2 is N-type buffer layer, 3 is N - Drift layer, 4 is N - Region, 5 is P-well region, 6 is NP region, 7 is PP region, 8 is trench region, 9 is P + Region, 10 is gate bottom oxide layer, 11 is gate oxide layer, 12 is Poly layer, 13 is dielectric layer, 14 is source ohmic contact alloy layer, 15 is source metal layer, 16 is drain metal layer. DETAILED DESCRIPTION

[0041] The utility model will be explained in detail in combination with specific actual case. The example of the embodiment is shown in the drawing, and the illustrative embodiment and its explanation of the utility model are only used for explaining the utility model, and are not as the limitation of the utility model.

[0042] The preparation method of SiC MOSFET device with L-shaped gate oxide structure comprises the following steps:

[0043] S100, refer to Figure 1 Fig. 1, a layer of N-type buffer layer 2 is grown on the heavily doped N + Substrate layer 1;

[0044] The N + Substrate layer 1 of step S100 is doped with N ions, and the thickness is 360-400um, and the doping concentration is 1e 19 cm -2 ± 10%, and the N-type buffer layer is also doped with N ions, and the thickness is 0.8-1.2um, and the doping concentration is 1e 18 cm -2 ± 10%.

[0045] S200, refer to Figure 2 Fig. 2, a layer of primary N - Drift layer 3 is epitaxially grown on the N-type buffer layer 2;

[0046] The primary N - Drift layer 3 of step S200 is doped with N ions, and the doping concentration is 8e 15 -1e 16 cm -2 , and the thickness is 5-15um.

[0047] S300, refer to Figure 3 Fig. 3, the N - Region 4 is formed on the top surface of the N - Drift layer 3 by ion implantation.

[0048] N in step S300 - Region 4 is doped with N ions at a doping concentration of 5e 16 -1e 17 cm -2 .

[0049] S400, refer to Figure 4 illustrated, N - Region 4 top surface by ion implantation of P-well region 5;

[0050] P-well region 5 in step S300 is doped with Al ions at a doping concentration of 1e 17 -1e 18 cm -2 .

[0051] S500, refer to Figure 5 illustrated, P-well region 5 top surface by ion implantation of NP region 6;

[0052] NP region 6 in step S500 is doped with N ions at a doping concentration of 1e 18 -1e 19 cm -2 , the implantation depth is less than the depth of P-well region 5.

[0053] S600, refer to Figure 6 illustrated, P-well region 5 top surface by ion implantation of PP region 7 connected with NP region 6;

[0054] PP region 7 in step S600 is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm -2 , the implantation depth is less than the depth of P-well region 5

[0055] S700, refer to Figure 7 illustrated, P-well region 5 on the surface by dry etching to form a trench region 8;

[0056] Trench region 8 in step S700 etching depth is less than the depth of P-well region 5.

[0057] S800, refer to Figure 8 illustrated, the bottom of the trench region 8 by ion implantation to form P + region 9, after implantation high temperature ion activation;

[0058] P + region 9 in step S800 is doped with Al ions at a doping concentration of 1e 18 -1e 19 cm-2 The activation annealing temperature is 1650-1750℃, and the annealing time is 10-30min.

[0059] S900, refer to Figure 9 As shown, in P + The top surface of zone 9 forms a gate bottom oxide layer 10 by depositing oxides;

[0060] The gate oxide layer 10 in step S900 has a thickness of 200-500 nm, which is much larger than that of the gate oxide layer 11.

[0061] S1000, refer to Figure 10 As shown, a gate oxide layer 11 is formed on the sidewalls and top of the trench region 8 by a dry oxygen thermal oxidation process, forming a channel at the interface with the P-well region 5;

[0062] In step S1000, the growth temperature of the gate oxide layer 11 is 1250-1350℃, the growth thickness is 40-60nm, and it needs to be annealed in a NO atmosphere at a temperature of 1250℃ for 1 hour to improve the density of the gate oxide layer 11 and reduce defects.

[0063] S1100, refer to Figure 11 As shown, a poly layer 12 is formed on the gate bottom oxide layer 10 and the gate oxide layer 11 by depositing polysilicon, and the gate electrode is led out.

[0064] S1200, refer to Figure 12 As shown, a dielectric layer 13 is formed on top of the Poly layer 12 by depositing an oxide layer, which isolates the gate electrode and the source electrode metal.

[0065] S1300, refer to Figure 13 As shown, a source ohmic contact alloy layer 14 is formed on top of NP region 6 and PP region 7 by sputtering Ni or other metals;

[0066] In step S1300, the annealing temperature of the source electrode ohmic contact alloy layer 14 is 1000℃ and the annealing time is 5min, so as to form an alloy and achieve the ohmic contact effect.

[0067] S1400, refer to Figure 14 As shown, a source metal layer 15 is formed on top of the source ohmic contact alloy layer 14 and the dielectric layer 13 by sputtering Ti / AlCu or other metals to bring out the source electrode;

[0068] S1500, refer to Figure 15 As shown, in N + The back side of substrate 1 is thinned to reduce N. +The drain metal layer 16 is formed by sputtering Ni metal and then evaporating Ti / Ni / Ag metal in the manner of the substrate layer 1 thickness.

[0069] The drain metal layer 16 in step S1500 needs to be laser annealed after sputtering Ni metal, and the laser energy is 2-4 mJ / cm 2 ; then evaporate Ti / Ni / Ag and other multi-layer metals, with a total thickness of 1.4-2um.

[0070] The SiC MOSFET device with L-shaped gate oxide structure includes, from bottom to top, a drain metal layer 16, an N + substrate layer 1, an N-type buffer layer 2, an N - drift layer 3, a source ohmic contact alloy layer 14 and a source metal layer 15;

[0071] The N - drift layer 3 is provided with:

[0072] N - region 4, extending downward from the top surface of the N - drift layer 3, with a spacing between the bottom surface of the N - drift layer 3;

[0073] P-well region 5, provided with several, respectively extending downward from the top surface of the N - region 4, and level with the bottom surface of the N - region 4;

[0074] NP region 6, provided with several, respectively extending downward from the top surface of the P-well region 5, and with a spacing between the bottom surface of the P-well region 5;

[0075] PP region 7, provided with several, respectively extending downward from the top surface of the P-well region 5, located on the side of the NP region 6; the bottom surface of the PP region 7 is spaced apart from the bottom surface of the P-well region 5;

[0076] P + region 9, located in the N - region 4, with the bottom surface level with the bottom surface of the N - region 4;

[0077] Gate bottom oxide layer 10, located on the top surface of the P + region 9; the top surface of the gate bottom oxide layer 10 is located below the top surface of the N - region 4;

[0078] Gate oxide layer 11, provided with a pair, respectively passing through the NP region 6, P-well region 5 and N -The top surface of the region 4 extends downward to the top surface of the gate bottom oxide layer 10; a pair of the gate oxide layers 11 are provided with a spacing; in the case, the gate oxide layer 11 is in an L-shaped structure;

[0079] The Poly layer 12 is in a T-shaped structure in cross section, and covers the top surfaces of the gate bottom oxide layer 10 and the gate oxide layer 11; the top surface of the Poly layer 12 is provided with a dielectric layer 13, and the side portion of the dielectric layer 13 extends downward to the top surface of the NP region 6.

[0080] The dielectric layer 13 is connected with the NP region 6, the gate oxide layer 11 and the Poly layer 12 respectively.

[0081] The source ohmic contact alloy layer 14 is provided with a plurality of source ohmic contact alloy layers, and is located at the side portion of the dielectric layer 13, and the bottom surface is connected with the NP region 6 and the PP region 7 respectively.

[0082] The bottom surface of the source metal layer 15 covers the source ohmic contact alloy layer 14 and the dielectric layer 13.

[0083] The utility model makes improvement for the gate oxide quality of SiC MOSFET device, first step utilizes the depositing process to form the relatively thick gate bottom oxide layer 10 (thickness is 200-500nm), second step utilizes dry oxygen thermal oxidation process to form the gate oxide layer 11 structure, and the relatively thick gate bottom oxide layer 10 can significantly improve the reliability of the gate oxide bottom under the condition of not affecting the on-resistance of device, and the relatively thick gate bottom oxide layer 10 can also reduce the Crss parasitic capacitance of chip, is favorable to the high frequency application of device, simultaneously utilizes P + The region 9 shields the electric field of the gate oxide bottom, and further improves the reliability of the gate oxide.

[0084] In addition, the utility model also makes improvement for the current-carrying capacity of the JEFT region of SiC MOSFET device, and the gate oxide layer 11 of the utility model is in an L-shaped structure, wherein the horizontal portion is responsible for the channel switch and is the same as the conventional plane SiC MOSFET device structure, but the vertical portion gate electrode will also attract electron aggregation in the opening process, increases the carrier concentration of the JEFT region, improves the current-carrying capacity, and improves the JEFT effect under working condition; in the turn-off process, the vertical portion repels electrons, reduces the concentration of the N - Region, and reduces the leakage between the source electrode and the drain electrode.

Claims

1. A SiC MOSFET device having an L-shaped gate oxide structure, characterized by, comprises, from bottom to top, a drain metal layer (16), an N + substrate layer (1), an N-type buffer layer (2), an N - drift layer (3), a source ohmic contact alloy layer (14), and a source metal layer (15); The N - The drift layer (3) is provided with: N - region (4) from the N - the top surface of the drift layer (3) extends downward; P-well region (5) is provided with several, respectively from the N - region (4) top surface extends downward; NP region (6), provided with several, respectively from the top surface of the P-well region (5) downwardly extending; PP region (7), provided with several, respectively from the top surface of the P-well region (5) downwardly extending, located in the side of the NP region (6); P + region (9) located in the N - region (4), the bottom surface connected with the N - drift layer (3); a gate bottom oxide layer (10) located on the P + top surface of the region (9); A pair of gate oxide layers (11) are provided, which extend from the top surface of the NP region (6), the P-well region (5) and the N - region (4) to the top surface of the gate bottom oxide layer (10) in sequence. Poly layer (12), covers the top surface of the gate bottom oxide layer (10) and gate oxide layer (11); the top surface of the Poly layer (12) is provided with a dielectric layer (13), and the side of the dielectric layer (13) extends downwardly to the top surface of the NP region (6).

2. The SiC MOSFET device with L-shaped gate oxide structure of claim 1, wherein, The N - The drift layer (3) has a thickness of 5-15 um.

3. The SiC MOSFET device with L-shaped gate oxide structure of claim 1, wherein, The thickness of the gate oxide layer (11) is between 40-60nm.

4. The SiC MOSFET device with L-shaped gate oxide structure of claim 1, wherein, The thickness of the gate bottom oxide layer (10) is between 200-500nm.

5. The SiC MOSFET device with L-shaped gate oxide structure of claim 3, wherein, The cross section of the gate oxide layer (11) is in L-shaped structure.

6. The SiC MOSFET device with L-shaped gate oxide structure of claim 1, wherein, The NP region (6) is provided with a spacing between the N - region (4).

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