Novel high-voltage input cascade topology control application circuit

Abstract

The utility model discloses a novel high-voltage input cascade topology control application circuit, which comprises a first control chip, a second control chip and a synchronizing signal circuit, the working frequency of the first control chip is smaller than that of the second control chip, the second control chip is connected with the first control chip through the synchronizing signal circuit, and the synchronizing signal circuit is connected with the first control chip. And the second control chip controls the post-stage working frequency of the first control chip through the synchronous signal circuit. According to the utility model, the second control chip is added, the second control chip sets the post-stage working frequency required by the first control chip as the target working efficiency, the driving wave of the second control chip is differentiated into a 50nS pulse signal through the synchronizing signal circuit, and the 50nS pulse signal is sent to the RC oscillator in the first control chip; the RC oscillation circuit in the first control chip acts in advance, so that the pre-stage working frequency of the first control chip is equal to the post-stage working frequency of the first control chip, thereby reducing the switching loss of pre-stage power conversion, reducing the heating of a power supply and improving the efficiency of the power supply.

Description

Technical Field

[0001] This utility model relates to a high-voltage to low-voltage DC / DC converter, specifically, to a novel high-voltage input cascaded topology control application circuit. Background Technology

[0002] Currently, cascaded conversion topologies are increasingly used in DC / DC converters. To reduce low-frequency oscillations in cascaded topologies, a common practice is to have the operating frequencies of the pre-stage and post-stage converters be the same or multiples of each other. The chips are cascaded chips, with the operating frequency of the pre-stage power supply generated by the internal RC oscillation of the chip, and the operating frequency of the post-stage controlled by a D flip-flop controlled by the operating frequency of the pre-stage converter.

[0003] Currently, the industry commonly adopts the approach of setting the switching frequency of the preceding stage to be equal to that of the following stage. This approach works fine in low-voltage DC / DC converters, but in high-voltage DC / DC converters, due to the higher input voltage, the switching losses of the preceding stage topology increase. The original oscillator inside the chip cannot meet the requirement of increasing the operating frequency of the following stage to the same level as that of the preceding stage. The operating frequency of the following stage is only half that of the preceding stage, which is not conducive to improving efficiency and reducing thermal stress. To address this problem, this design proposes a novel design scheme that can reconcile and solve this issue. Utility Model Content

[0004] To overcome the problems in existing high-voltage DC / DC converters where the high input voltage leads to increased switching losses in the front-end topology, and the inability of the original oscillator inside the chip to meet the requirement of increasing the operating frequency of the subsequent stage to the same level as the front-end stage (resulting in the subsequent stage operating frequency being only half that of the front-end stage), which is detrimental to improving efficiency and reducing thermal stress, this invention provides a novel high-voltage input cascaded topology control application circuit.

[0005] The technical solution of this utility model is as follows:

[0006] A novel high-voltage input cascaded topology control application circuit includes a first control chip, a second control chip, and a synchronization signal circuit. The operating frequency of the first control chip is lower than that of the second control chip. The second control chip is connected to the first control chip through the synchronization signal circuit. The second control chip controls the operating frequency of the stage following the first control chip through the synchronization signal circuit, so that the operating frequency of the stage preceding the first control chip is the same as the operating frequency of the stage following the first control chip.

[0007] According to the present invention based on the above scheme, the synchronization signal circuit includes a differentiating circuit, an anti-negative voltage diode, a discharge resistor, and a first RC oscillation resistor. One end of the differentiating circuit is connected to the second control chip, and the other end of the differentiating circuit is connected to the common terminal of the anti-negative voltage diode and the discharge resistor. The cathode of the anti-negative voltage diode is connected to the first terminal of the first RC oscillation resistor, and the discharge resistor is connected to the second terminal of the RC oscillation resistor.

[0008] According to the present invention based on the above scheme, the differentiating circuit includes a first resistor and a first capacitor, wherein the first resistor and the first capacitor are connected in series.

[0009] According to the above-described scheme, this utility model further includes a second RC oscillation resistor, and the second control chip is connected to the second RC oscillation resistor.

[0010] According to the above-described scheme of this utility model, the first control chip is connected to a first decoupling capacitor bank.

[0011] According to the present invention based on the above scheme, the first decoupling capacitor group includes a second capacitor, a third capacitor, and a fourth capacitor. The first end of the second capacitor is connected to the first pin and the seventh pin of the first control chip. The first end of the third capacitor is connected to the fourth pin of the first control chip. The first end of the fourth capacitor is connected to the thirteenth pin of the first control chip. The second ends of the second capacitor, the third capacitor, and the fourth capacitor are all grounded.

[0012] According to the above-described scheme of this utility model, the second control chip is connected to a second decoupling capacitor bank.

[0013] According to the present invention based on the above scheme, the second decoupling capacitor group includes a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first end of the fifth capacitor is connected to the first pin and the seventh pin of the second control chip. The first end of the sixth capacitor is connected to the fourth pin of the second control chip. The first end of the seventh capacitor is connected to the sixteenth pin of the second control chip. The second ends of the fifth capacitor, the sixth capacitor, and the seventh capacitor are all grounded.

[0014] According to the above-described solution, the beneficial effects of this utility model are as follows: By adding a second control chip, the second control chip sets the required operating frequency of the first control chip to the target operating efficiency. The driving wave of the second control chip is divided into a 50ns pulse signal by a synchronization signal circuit and sent to the internal RC oscillator of the first control chip, causing the RC oscillation circuit inside the first control chip to operate in advance. This makes the operating frequency of the first control chip's output stage equal to the operating frequency of the second control chip, and makes the operating frequency of the first control chip's output stage equal to the operating frequency of the output stage. This reduces the switching losses of the power conversion in the output stage, reduces power supply heat generation, improves power supply efficiency, and enhances power supply output performance. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the circuit structure of this utility model.

[0016] Figure 2 This is the circuit schematic diagram of this utility model. Detailed Implementation

[0017] To make the technical problems, technical solutions and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.

[0018] It should be noted that the terms "comprising" and "having," and any variations thereof, in the specification and claims of this utility model are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. Terms such as "set up" should be interpreted broadly; for example, it can refer to a fixed connection, a detachable connection, or an integral part; it can refer to a mechanical connection or an electrical connection; it can refer to a direct connection or an indirect connection through an intermediate medium; it can refer to the internal communication of two elements or the interaction between two elements, unless otherwise expressly defined. Terms such as "upper," "lower," "left," "right," "front," "rear," and "bottom" indicate orientations or positions based on the orientations or positions shown in the accompanying drawings, and are only for ease of description and should not be construed as limiting the present technical solution.

[0019] It should be noted that the industry generally adopts the approach of having the switching frequency of the preceding stage equal to that of the following stage. This approach works fine in low-voltage DC / DC converters, but in high-voltage DC / DC converters, due to the higher input voltage, the switching losses of the preceding stage topology increase. The original oscillator inside the chip cannot meet the requirement of increasing the operating frequency of the following stage to the same level as that of the preceding stage. The operating frequency of the following stage is only half that of the preceding stage, which is not conducive to improving efficiency and reducing thermal stress. To address this issue, this design proposes a novel design scheme that can reconcile and solve this problem.

[0020] like Figures 1-2 As shown, a novel high-voltage input cascaded topology control application circuit adds a second control chip. This second control chip sets the required operating frequency of the subsequent stage of the first control chip to the target operating efficiency. A synchronization signal circuit divides the drive wave of the second control chip into a 50ns pulse signal, which is then sent to the internal RC oscillator of the first control chip. This causes the RC oscillation circuit inside the first control chip to activate in advance, ensuring that the operating frequency of the subsequent stage of the first control chip is equal to that of the second control chip. This also ensures that the operating frequency of the preceding stage of the first control chip is equal to that of the subsequent stage, thereby reducing switching losses in the preceding stage power conversion, reducing power supply heat generation, improving power supply efficiency, and enhancing power supply output performance.

[0021] Specifically, it includes a first control chip, a second control chip, and a synchronization signal circuit. The operating frequency of the first control chip is lower than that of the second control chip. The second control chip is connected to the first control chip through the synchronization signal circuit. The second control chip controls the operating frequency of the subsequent stage of the first control chip through the synchronization signal circuit, so that the operating frequency of the preceding stage of the first control chip is the same as that of the subsequent stage of the first control chip.

[0022] In one embodiment, the synchronization signal circuit includes a differentiating circuit, an anti-negative voltage diode, a discharge resistor, and a first RC oscillation resistor. One end of the differentiating circuit is connected to the second control chip, and the other end is connected to the common terminal of the anti-negative voltage diode and the discharge resistor. The cathode of the anti-negative voltage diode is connected to the first terminal of the first RC oscillation resistor, and the discharge resistor is connected to the second terminal of the RC oscillation resistor. The anti-negative voltage diode acts as a protective element to prevent the pulse signal output by the differentiating circuit (if it is a negative voltage) from damaging subsequent circuits. The discharge resistor is connected in parallel with the first RC oscillation resistor to quickly discharge when the RC oscillation circuit is not working, ensuring the stability and reliability of the circuit. The first RC oscillation resistor is used to set the original operating frequency of the first control chip. The first RC oscillation resistor works together with the RC oscillator inside the first control chip to control the oscillation frequency of the first control chip.

[0023] The differentiating circuit includes a first resistor and a first capacitor connected in series. The first resistor and the first capacitor together constitute the differentiating circuit, which can differentiate the driving wave input from the second control chip into a 50ns pulse signal.

[0024] like Figure 1 As shown, U10 is the first control chip, U4 is the second control chip, resistor R191 and capacitor C156 form a differentiating circuit, D19 is a negative voltage protection diode, R191 is a discharge resistor, and R25 is the first RC oscillation resistor.

[0025] In one embodiment, a second RC oscillation resistor is further included. The second control chip is connected to the second RC oscillation resistor to set the operating frequency of the subsequent stage of the first control chip. The second RC oscillation resistor works together with the RC oscillator inside the second control chip to control the oscillation frequency of the second control chip. Figure 1 In the diagram, R181 is the second RC oscillation resistor.

[0026] In one embodiment, the first control chip is connected to a first decoupling capacitor bank. The main function of the first decoupling capacitor bank is to reduce voltage fluctuations on the power line caused by load changes, i.e., to reduce power supply noise and ensure the stable operation of the first control chip.

[0027] The first decoupling capacitor bank includes a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the second capacitor is connected to the first pin and the seventh pin of the first control chip. The first terminal of the third capacitor is connected to the fourth pin of the first control chip. The first terminal of the fourth capacitor is connected to the thirteenth pin of the first control chip. The second terminals of the second, third, and fourth capacitors are all grounded.

[0028] When the first control chip is operating, its internal circuitry generates dynamic current demands, which may cause voltage fluctuations on the power line. The second capacitor, by providing a bypass path for high-frequency signals, can quickly absorb or release these transient currents, thereby maintaining a stable voltage on the power line.

[0029] The third and fourth capacitors are connected to the fourth and thirteenth pins of the first control chip, respectively. Their main function is to reduce high-frequency noise on these pins. When external signals enter or leave the first control chip through these pins, the capacitors can absorb or isolate high-frequency noise, protect the integrity of the signal, and prevent noise from interfering with the internal circuitry of the chip.

[0030] In one embodiment, the second control chip is connected to a second decoupling capacitor bank. The main function of the second decoupling capacitor bank is to reduce voltage fluctuations on the power line caused by load changes, i.e., to reduce power supply noise and ensure the stable operation of the second control chip.

[0031] The second decoupling capacitor bank includes a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first terminal of the fifth capacitor is connected to the first and seventh pins of the second control chip. The first terminal of the sixth capacitor is connected to the fourth pin of the second control chip. The first terminal of the seventh capacitor is connected to the sixteenth pin of the second control chip. The second terminals of the fifth, sixth, and seventh capacitors are all grounded.

[0032] When the second control chip is operating, its internal circuitry generates dynamic current demands, which may cause voltage fluctuations on the power line. The fifth capacitor, by providing a bypass path for high-frequency signals, can quickly absorb or release these transient currents, thereby maintaining voltage stability on the power line.

[0033] The sixth and seventh capacitors are connected to the fourth and sixteenth pins of the second control chip, respectively. Their main function is to reduce high-frequency noise on these pins. When external signals enter or leave the second control chip through these pins, the capacitors can absorb or isolate high-frequency noise, protect the integrity of the signal, and prevent noise from interfering with the internal circuitry of the chip.

[0034] It should be understood that those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

[0035] The present utility model patent has been described above with reference to the accompanying drawings. Obviously, the implementation of the present utility model patent is not limited to the above-described manner. Any improvements made by adopting the inventive concept and technical solution of the present utility model patent, or the direct application of the inventive concept and technical solution of the present utility model patent to other occasions without modification, are all within the protection scope of the present utility model.

Claims

1. A novel high-voltage input cascaded topology control application circuit, characterized in that, It includes a first control chip, a second control chip, and a synchronization signal circuit. The operating frequency of the first control chip is lower than that of the second control chip. The second control chip is connected to the first control chip through the synchronization signal circuit. The second control chip controls the operating frequency of the subsequent stage of the first control chip through the synchronization signal circuit, so that the operating frequency of the preceding stage of the first control chip is the same as that of the subsequent stage of the first control chip.

2. The novel high-voltage input cascaded topology control application circuit according to claim 1, characterized in that, The synchronization signal circuit includes a differentiating circuit, an anti-negative voltage diode, a discharge resistor, and a first RC oscillation resistor. One end of the differentiating circuit is connected to the second control chip, and the other end of the differentiating circuit is connected to the common terminal of the anti-negative voltage diode and the discharge resistor. The cathode of the anti-negative voltage diode is connected to the first terminal of the first RC oscillation resistor, and the discharge resistor is connected to the second terminal of the RC oscillation resistor.

3. The novel high-voltage input cascaded topology control application circuit according to claim 2, characterized in that, The differentiating circuit includes a first resistor and a first capacitor, which are connected in series.

4. The novel high-voltage input cascaded topology control application circuit according to claim 1, characterized in that, It also includes a second RC oscillation resistor, and the second control chip is connected to the second RC oscillation resistor.

5. The novel high-voltage input cascaded topology control application circuit according to claim 1, characterized in that, The first control chip is connected to a first decoupling capacitor bank.

6. The novel high-voltage input cascaded topology control application circuit according to claim 5, characterized in that, The first decoupling capacitor bank includes a second capacitor, a third capacitor, and a fourth capacitor. The first terminal of the second capacitor is connected to the first pin and the seventh pin of the first control chip. The first terminal of the third capacitor is connected to the fourth pin of the first control chip. The first terminal of the fourth capacitor is connected to the thirteenth pin of the first control chip. The second terminals of the second capacitor, the third capacitor, and the fourth capacitor are all grounded.

7. A novel high-voltage input cascaded topology control application circuit according to claim 1, characterized in that, The second control chip is connected to a second decoupling capacitor bank.

8. A novel high-voltage input cascaded topology control application circuit according to claim 7, characterized in that, The second decoupling capacitor bank includes a fifth capacitor, a sixth capacitor, and a seventh capacitor. The first end of the fifth capacitor is connected to the first and seventh pins of the second control chip. The first end of the sixth capacitor is connected to the fourth pin of the second control chip. The first end of the seventh capacitor is connected to the sixteenth pin of the second control chip. The second ends of the fifth capacitor, the sixth capacitor, and the seventh capacitor are all grounded.

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