Packaging carrier and Doherty amplifier

Abstract

The utility model discloses a packaging carrier and a Doherty amplifier comprising the packaging carrier, the packaging carrier comprises a first input interface, a second input interface, a first output interface, a second output interface, a substrate, a first transistor, a second transistor, a third transistor, a fourth transistor and an interstage matching circuit, the first transistor, the second transistor, the third transistor and the fourth transistor are located on the substrate, control ends of the first transistor and the third transistor are respectively coupled to the first input interface and the second input interface, output ends of the first transistor and the third transistor are respectively coupled to control ends of the second transistor and the fourth transistor, and output ends of the second transistor and the fourth transistor are respectively coupled to the first output interface and the second output interface; and wherein each of the first and third transistors includes a silicon-based transistor, and at least one of the second and fourth transistors includes a silicon carbide-based transistor; and the inter-stage matching circuit is configured to provide an impedance matching function for the first and second transistors, and to provide an impedance matching function for the third and fourth transistors.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of radio frequency communication, specifically, relate to a kind of packaging carrier and a kind of Doherty amplifier including the packaging carrier. BACKGROUND

[0002] To meet the requirements of high power, high efficiency and miniaturization of various amplifiers in the field of radio frequency communication, it is increasingly popular to package multiple transistors in parallel in the same carrier. Such packaging carriers, in cooperation with appropriate peripheral circuits, can support various amplifier architectures, such as balance PA, Doherty PA and out-phasing PA, etc.

[0003] In related technologies, transistors of the same semiconductor process are often packaged in the same carrier. For example, Figure 1A The packaging carrier 110 shown includes four silicon-based transistors (111, 112, 113, 114), Figure 1B The packaging carrier 120 shown includes two gallium nitride-based transistors (121, 122). However, on the one hand, silicon-based transistors, although low in cost, have lower efficiency and larger parasitic capacitance. On the other hand, gallium nitride-based transistors, although having higher efficiency, are more expensive, and such transistors have more significant nonlinear characteristics and trap effects. SUMMARY

[0004] In view of the above, the utility model discloses a kind of packaging carrier and a kind of Doherty amplifier including the packaging carrier, to alleviate, mitigate, even eliminate the above problems.

[0005] According to one aspect of the present application, the embodiments of the present application disclose a packaging carrier, comprising: a first input interface and a second input interface; a first output interface and a second output interface; a substrate; a first transistor and a second transistor, wherein the first transistor and the second transistor are located on the substrate, a control end of the first transistor is coupled to the first input interface, an output end of the first transistor is coupled to a control end of the second transistor, and an output end of the second transistor is coupled to the first output interface; a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are located on the substrate, a control end of the third transistor is coupled to the second input interface, an output end of the third transistor is coupled to a control end of the fourth transistor, and an output end of the fourth transistor is coupled to the second output interface, and wherein each of the first transistor and the third transistor comprises a silicon-based transistor, and at least one of the second transistor and the fourth transistor comprises a silicon carbide-based transistor; and an inter-stage matching circuit configured to provide an impedance matching function for the first transistor and the second transistor, and to provide an impedance matching function for the third transistor and the fourth transistor.

[0006] In some embodiments, the packaging structure further comprises a first sub-packaging structure, the first sub-packaging structure being located on the substrate and comprising the first transistor and the third transistor.

[0007] In some embodiments, the packaging structure further comprises a second sub-packaging structure, the second sub-packaging structure being located on the substrate and comprising the second transistor and the fourth transistor.

[0008] In some embodiments, the second sub-packaging structure further comprises at least one opening, the at least one opening penetrating at least a portion of the second sub-packaging structure.

[0009] In some embodiments, at least a portion of the at least one opening is grounded.

[0010] In some embodiments, the second sub-package structure further comprises: a first input node coupled to an output terminal of the first transistor and a control terminal of the second transistor; a second input node coupled to an output terminal of the third transistor and a control terminal of the fourth transistor; a first capacitor having one end coupled to an output terminal of the second transistor and the other end coupled to a first output node of the second sub-package structure; a second capacitor having one end coupled to an output terminal of the fourth transistor and the other end coupled to a second output node of the second sub-package structure; a base supporting at least part of the circuit elements in the second sub-package structure; and a protective cover cooperating with the base to enclose at least part of the circuit elements in the second sub-package structure.

[0011] In some embodiments, the length of the base and the protective cover is between 10 mm and 20 mm, and wherein the length of the second transistor and the fourth transistor is between 5 mm and 10 mm.

[0012] In some embodiments, at least one of the coupling between the first input node and the output terminal of the first transistor and the control terminal of the second transistor, the coupling between the second input node and the output terminal of the third transistor and the control terminal of the fourth transistor, the coupling between the first capacitor and the output terminal of the second transistor and the first output node of the second sub-package structure, and the coupling between the second capacitor and the output terminal of the fourth transistor and the second output node of the second sub-package structure can be implemented in any one of the following forms: a bonding wire, a microstrip line.

[0013] In some embodiments, the inter-stage matching circuit comprises a first matching circuit and a second matching circuit, each of the first matching circuit and the second matching circuit is attached to the substrate, the first matching circuit is configured to provide an impedance matching function for the first transistor and the second transistor, and the second matching circuit is configured to provide an impedance matching function for the third transistor and the fourth transistor.

[0014] In some embodiments, the package structure comprises a third sub-package structure on the substrate, the third sub-package structure comprises the inter-stage matching circuit and a biasing circuit, the biasing circuit is configured to provide a corresponding bias voltage for the first transistor, the second transistor, the third transistor, and the fourth transistor.

[0015] In some embodiments, the gate bias voltage provided to each of the second transistor and the fourth transistor is between -6 volts and -4 volts.

[0016] According to another aspect of the present application, the embodiments of the present application disclose a Doherty amplifier, comprising: a radio frequency input interface coupled to an input end of a power divider of the Doherty amplifier; the packaging carrier according to any one of the preceding embodiments of the present application, wherein the first input interface and the second input interface of the packaging carrier are coupled to output ends of the power divider, the first transistor and the second transistor are configured to obtain a first amplified signal based on a first signal from the first input interface, the third transistor and the fourth transistor are configured to obtain a second amplified signal based on a second signal from the second input interface; a combiner matching network coupled between the first output interface, the second output interface of the packaging carrier and a radio frequency output interface of the Doherty amplifier.

[0017] In some embodiments, the packaging carrier further comprises: a third input interface and a third output interface, wherein the third input interface is coupled to an output end of the power divider, and the third output interface is coupled to the combiner matching network; a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are located on the substrate, a control end of the fifth transistor is coupled to the third input interface, an output end of the fifth transistor is coupled to a control end of the sixth transistor, an output end of the sixth transistor is coupled to the third output interface, and wherein the fifth transistor and the sixth transistor are configured to obtain a third amplified signal based on a third signal from the third input interface.

[0018] In the packaging carrier provided by the embodiments of the present application, a plurality of transistors located on the substrate of the packaging carrier are provided, wherein a part of the transistors comprise silicon-based transistors, and another part of the transistors comprise silicon carbide-based transistors. These transistors cooperate with other circuit elements in the packaging carrier, can exert the respective advantages of silicon-based transistors and silicon carbide-based transistors, and thus help to control the cost of the packaging carrier, the parasitic capacitance of the plurality of transistors in the packaging carrier, and make the packaging carrier have higher working efficiency and better linear characteristics.

[0019] These and other aspects of the present application will become clear from the embodiments described below, and will be elucidated with reference to the embodiments described below. BRIEF DESCRIPTION OF DRAWINGS

[0020] In the following description of exemplary embodiments in conjunction with the accompanying drawings, more details, features and advantages of the technical solutions of the present application are disclosed, in the drawings:

[0021] Figure 1A And Figure 1B An exemplary architecture diagram of a packaging carrier in the related art is schematically shown;

[0022] Figure 2 An exemplary architecture diagram of a package carrier is schematically shown in accordance with some embodiments of the present application;

[0023] Figure 3 An exemplary architecture diagram of a package carrier is schematically shown in accordance with some other embodiments of the present application;

[0024] Figure 4 An exemplary architecture diagram of a package carrier is schematically shown in accordance with some embodiments of the present application;

[0025] Figure 5 An exemplary package diagram of a package carrier is schematically shown in accordance with some other embodiments of the present application;

[0026] Figure 6 An exemplary package diagram of a package carrier is schematically shown in accordance with some other embodiments of the present application;

[0027] Figure 7 An exemplary architecture diagram of a package carrier is schematically shown in accordance with some other embodiments of the present application;

[0028] Figure 8 An exemplary architecture diagram of a package carrier is schematically shown in accordance with some other embodiments of the present application;

[0029] Figure 9 An exemplary package diagram of a Doherty amplifier is schematically shown in accordance with some embodiments of the present application;

[0030] Figure 10 An exemplary package diagram of a Doherty amplifier is schematically shown in accordance with some other embodiments of the present application; and

[0031] Figure 11 An exemplary performance diagram of a Doherty amplifier is schematically shown in accordance with some embodiments of the present application. DETAILED DESCRIPTION

[0032] Several embodiments of the present application will be described in detail herein below with reference to the drawings, in order to enable a person skilled in the art to implement the technical solutions of the present application. The technical solutions of the present application can be embodied in many different forms and purposes, and should not be limited to the embodiments described herein. These embodiments are provided in order to make the technical solutions of the present application clear and complete, but do not limit the protection scope of the present application.

[0033] Here, first, some terms involved in each embodiment of the present application are described in order to facilitate understanding by those skilled in the art.

[0034] 1. Package structure: refers to a product formed by different elements being fabricated on the same substrate and sealed in the same package shell through integration process. The package structure can be in the form of a chip. Similarly, the term "sub-package structure" mentioned herein has similar characteristics as the above-mentioned package structure, which can be in the form of a chip, but the "sub-package structure" is fabricated on the substrate of the above-mentioned package structure and sealed inside the package structure, i.e. the sub-package structure can be regarded as an element of the package structure.

[0035] 2. Transistor: refers to a semiconductor device including three terminals, which can include a gate, a source and a drain, or a base, a collector and an emitter. The control terminal of the transistor mentioned herein refers to the gate or the base, and the output terminal of the transistor refers to one of the source and the drain, or one of the collector and the emitter.

[0036] 3. Silicon-based transistor: refers to a transistor whose current conduction channel is mainly made of silicon semiconductor material. Examples of silicon-based transistors include but are not limited to lateral double-diffused metal oxide semiconductor (LDMOS) transistors, metal oxide semiconductor field effect transistors (MOSFETs), bipolar junction transistors (BJT).

[0037] 4. Silicon carbide-based transistor: refers to a transistor whose current conduction channel is mainly made of silicon carbide semiconductor material. Examples of silicon carbide-based transistors include but are not limited to lateral double-diffused metal oxide semiconductor (LDMOS) transistors, metal oxide semiconductor field effect transistors (MOSFETs), junction field effect transistors (JFET).

[0038] 5. Input interface, input node, output interface and output node: refer to the connection points / connection elements between the package carrier including such interfaces / nodes and the external circuit or system, and the device (e.g. Doherty amplifier) including such package carrier. Taking the input interface and the output interface as an example, from the physical layer, the input interface (e.g. the first input interface, the second input interface, the radio frequency input interface described below with reference to the multiple drawings) is the physical connection point / connection element for the corresponding package carrier and the Doherty amplifier to receive external radio frequency signals, while the output interface (e.g. the first output interface, the second output interface, the radio frequency output interface described below with reference to the multiple drawings) is the physical connection point / connection element for the corresponding package carrier and the Doherty amplifier to output the amplified radio frequency signals to the external circuit or system. These input and output interfaces can have various suitable shapes and structures, including but not limited to pads, pads, sockets, pins, etc. From the electrical layer, these interfaces not only provide physical connection, but also can be designed to have specific impedance characteristics to ensure good matching with the external circuit, reduce signal reflection and loss.

[0039] Figure 2 An exemplary architectural diagram of a packaging carrier 200 according to some embodiments of the present invention is shown schematically. Figure 2 As shown, the package carrier 200 includes: a first input interface 270a and a second input interface 270b, a first output interface 280a and a second output interface 280b, a substrate, a first transistor 210, a second transistor 220, a third transistor 230, a fourth transistor 240, and interstage matching circuits (250a, 250b). Interstage matching circuit 250a is configured to provide impedance matching for the first transistor 210 and the second transistor 220, and interstage matching circuit 250b is configured to provide impedance matching for the third transistor 230 and the fourth transistor 240.

[0040] The first transistor 210, the second transistor 220, the third transistor 230, and the fourth transistor 240 are located on a substrate. The control terminal of the first transistor 210 is coupled to the first input interface 270a, and the output terminal of the first transistor 210 is coupled to the control terminal of the second transistor 220. Figure 2 In the example shown, the output of the first transistor 210 is coupled to the control terminal of the second transistor 220 via an interstage matching circuit 250a; the output of the second transistor 220 is coupled to the first output interface 280a; the control terminal of the third transistor 230 is coupled to the second input interface 270b; and the output of the third transistor 230 is coupled to the control terminal of the fourth transistor 240 (in...). Figure 2 In the example shown, the output of the third transistor 230 is coupled to the control terminal of the fourth transistor 240 via an interstage matching circuit 250b, and the output of the fourth transistor 240 is coupled to the second output interface 280b. Figure 2 In the example shown, the first transistor 210, the third transistor 230, and the fourth transistor 240 are all silicon (Si)-based transistors, while the second transistor 220 is a silicon carbide (SiC)-based transistor. Specifically, the gate bias voltage supplied to the second transistor 220 can be between -6 volts and -4 volts to ensure its excellent performance, such as lower parasitic capacitance, higher efficiency, and better linearity. The packaging carrier of this transistor exhibits superior performance compared to, for example… Figure 1A The encapsulation carrier 110 and shown Figure 1B The encapsulation carrier 120 shown.

[0041] It should be noted here that... Figure 2 The interstage matching circuit (250a, 250b) between two amplifiers located on the same path can be an interstage matching network (ISMN). Figure 2In the multi-stage amplifier shown, the design of the ISMN can comprehensively consider multiple factors (including impedance matching, phase matching, frequency response, and physical size, etc.) to ensure that the entire amplifier system can perform well under various working conditions.

[0042] For at least the convenience of process considerations, in some embodiments, the package structure can further include a first sub-package structure located on the substrate and including the first transistor and the third transistor. As Figure 3 As shown, the package carrier 300 includes a first sub-package structure 310 located on the substrate, and the first transistor 311 and the third transistor 312 of the package carrier 300 are both packaged in the first sub-package structure 310. Optionally, in other embodiments, the package carrier 300 can further include, for example, Figure 3 As shown, a second sub-package structure 320 is located on the substrate of the package carrier 300, and the second transistor 321 and the fourth transistor 322 of the package carrier 300 are both packaged in the second sub-package structure 320. The control end of the first transistor 311 is coupled to the first input interface 350a of the package carrier 300, the output end of the first transistor 311 is coupled to the control end of the second transistor 321 via the circuit 330 (which includes a corresponding two-way ISMN inter-stage matching circuit and a bias circuit), the output end of the second transistor 321 is coupled to the first output interface 360a of the package carrier 300, the control end of the third transistor 312 is coupled to the second input interface 360b of the package carrier 300, the output end of the third transistor 312 is coupled to the control end of the fourth transistor 322 via the circuit 330, and the output end of the fourth transistor 322 is coupled to the second output interface 360b of the package carrier 300. In Figure 3 In the example shown, the first transistor 311 and the third transistor 312 are both silicon (Si) based transistors, and the second transistor 321 and the fourth transistor 322 are both silicon carbide (SiC) based transistors. Forming two-way transistors on the same sub-package structure helps to improve the consistency of the characteristic parameters (such as the on-voltage, gain, and on-resistance) of these transistors, which in turn helps to improve the consistency of the package carrier mass production, and can reduce costs (for example, at least the cutting loss can be reduced).

[0043] Figure 4 An implementation form of the second sub-package structure 320 in Figure 3 is schematically shown. As Figure 4As shown, the second sub-package structure 400 includes: a protective cover 401 (which can be made of metal, ceramic, plastic, etc.), which cooperates with the base 403 to enclose at least part of the circuit elements in the second sub-package structure 400, thereby protecting at least part of the circuit elements in the package cavity, and when appropriate material is selected, the protective cover 401 can also serve as a sealing and electromagnetic shielding; a cavity peripheral material 402 (which can be made of ceramic, etc.); the base 403 (which can be made of diamond, metal, etc.), which is used to carry at least part of the circuit elements in the second sub-package structure 400, and when appropriate material is selected, the base 403 can also provide heat dissipation and grounding loop; a second transistor 404, whose control terminal is electrically connected to a first input node 406 of the second sub-package structure 400 via a bonding wire 407, and whose output terminal is electrically connected to a first capacitor 408, which is then indirectly coupled to a first output node 409 of the second sub-package structure 400 via the first capacitor 408; a fourth transistor 405, whose control terminal is electrically connected to a second input node 410 of the second sub-package structure 400 via a bonding wire 411, and whose output terminal is electrically connected to a second capacitor 412, which is then indirectly coupled to a second output node 413 of the second sub-package structure 400 via the second capacitor 412.

[0044] Although not shown in Figure 4 , it should be understood by those skilled in the art that the first input node 406 is coupled to the output terminal of the first transistor of the corresponding package carrier, and the second input node 410 is coupled to the output terminal of the third transistor of the corresponding package carrier. In addition, the first output node 409 can be coupled to the first output interface of the corresponding package carrier, and the second output node 413 can be coupled to the second output interface of the corresponding package carrier.

[0045] In addition, although the cavity peripheral material 402 is shown in the example of Figure 4 , it should be understood by those skilled in the art that the cavity peripheral material 402 can be used to achieve better assembly of the protective cover 401 and the base 403, but this is not necessary, and alternatively, the protective cover 401 can be directly assembled with the base 403, for example, by mechanical fastening or adhesive bonding.

[0046] As to the size of each element in the second sub-package structure 400, exemplarily, the length of the protective cover 401 and the base 403 (i.e. the length of the long side of the corresponding rectangle) is between 10 mm and 20 mm (e.g. 10 mm, 15.4 mm, 17 mm, 20 mm), and the length of the second transistor 404 and the fourth transistor 405 (i.e. the length of the long side of the corresponding rectangle) is between 5 mm and 10 mm (e.g. 5 mm, 6.2 mm, 7.3 mm, 10 mm), so as to have a better heat dissipation performance of the second sub-package structure 400 while having a smaller size, thereby helping to improve the performance of the corresponding package carrier.

[0047] In addition, the inventors of the present application have noticed that the radio frequency signal can cause the occurrence of standing waves after passing through different transistors located on the same amplification path of the package carrier, for example, Figure 2 The positions 260a between the first transistor 210 and the second transistor 220, and the positions 260b between the third transistor 230 and the fourth transistor 240 as shown can have standing waves. The standing waves can be caused by one or more of the following factors: there is a phase difference between the incident signals after passing through different transistors, and the impedances of different transistors on the same amplification path are not completely matched. The inventors of the present application have realized that, although the impedances of different transistors on the same amplification path can be matched as much as possible by using ISMNs (e.g. Figure 2 The inventors of the present application have realized that, although the impedances of different transistors on the same amplification path can be matched as much as possible by using ISMNs (e.g. Figure 4 The inventors of the present application have realized that, although the impedances of different transistors on the same amplification path can be matched as much as possible by using ISMNs (e.g. Figure 4 In the example shown, seven rectangular openings are schematically drawn, which pass through at least a portion of the second sub-package structure, and in the example shown, all of these openings or a part of them can pass through at least a portion of the base 415 (as shown in Figure 4 The inventors of the present application have realized that, although the impedances of different transistors on the same amplification path can be matched as much as possible by using ISMNs (e.g. Figure 4 The base 415 is located on the base 403) where the second transistor 404 and the fourth transistor 405 are located. For example, all of these openings can completely pass through the base 415 in a direction perpendicular to the base 415, so as to reach the base 403 to further improve the grounding.

[0048] It should be noted that, Figure 4The number and shape of the openings shown are merely exemplary, and in practice, the number and shape thereof can be flexibly set according to actual needs, and the shape of each opening does not have to be the same (in addition to a rectangle, they can be various regular or irregular shapes such as a square, a circle, a triangle, etc.), and the size of each opening does not have to be the same either. In addition, in terms of the openings penetrating at least a portion of the second sub-package structure, the depth at which each opening penetrates the second sub-package structure can also be different, which provides a more abundant and refined solution for improving standing waves.

[0049] In addition, although in the example of Figure 4 the second transistor 404 and the fourth transistor 405 are located on the same base 415, this is merely exemplary, and the second transistor 404 and the fourth transistor 405 can also be located on different bases, or even one of the transistors can be located on a base, and the other transistor is directly located on the base 403. In these cases, the position of the opening 414 can be adjusted adaptively. Exemplarily, the second sub-package structure can include multiple bases, and the second transistor 404 and the fourth transistor 405 are respectively arranged on the bases, and at least one opening can exist on each of the bases of the second sub-package structure.

[0050] In some embodiments, at least one of the coupling between the first input node and the output end of the first transistor and the control end of the second transistor, the coupling between the second input node and the output end of the third transistor and the control end of the fourth transistor, the coupling between the first capacitor and the output end of the second transistor and the first output node of the second sub-package structure, and the coupling between the second capacitor and the output end of the fourth transistor and the second output node of the second sub-package structure can be implemented in the form of any one of the following: a bonding wire, a microstrip line. Still taking Figure 4 the example, the coupling between the first input node 406 of the second sub-package structure 400 and the control end of the second transistor 404 is implemented through a bonding wire 407. The coupling between the first capacitor 408 and the output end of the second transistor 404 and the first output node 409 of the second sub-package structure 400 is also implemented through the corresponding bonding wire shown. Figure 4 The coupling between the second input node 410 of the second sub-package structure 400 and the control end of the fourth transistor 405 is implemented through a bonding wire 411. The coupling between the second capacitor 412 and the output end of the fourth transistor 405 and the second output node 413 of the second sub-package structure 400 is also implemented through the corresponding bonding wire shown. Figure 4 Alternatively, these couplings can also be implemented in the form of a microstrip line. As yet another example, part of these couplings can be implemented in the form of a bonding wire, and the other part can be implemented in the form of a microstrip line.

[0051] Figure 5 An exemplary packaging structure diagram of a packaging carrier 500 according to other embodiments of the present invention is shown schematically. Figure 5 As shown, the package carrier 500 (which can be an LGA structure or a QFN structure) includes: a metal pad 501 (which can be used to carry circuit components and provide heat dissipation and grounding loops); a first transistor chip 503 based on SiC technology; a second transistor chip 504 based on SiC technology; and a driver stage amplifier circuit chip 502 fabricated based on Si technology, which includes a first input matching circuit 505, a first driver stage transistor 506, and a first interstage matching network 507 (which is electrically connected to the chip 503 via bonding wires), wherein a first gate bias circuit composed of an inductor and a capacitor is electrically connected to pin 518 (which provides a first gate voltage), and pins 516 and 517 are respectively connected to the first... The chip 502 includes a gate and drain bias circuit for the driver stage transistor 506; it also includes a second input matching circuit 508, a second driver stage transistor 509, and a second inter-stage matching network 510 (which is electrically connected to the chip 504 via bonding wires). The second gate bias circuit, composed of an inductor and a capacitor, is electrically connected to pin 521 (which provides the second gate voltage). Pins 519 and 520 are respectively connected to the gate and drain bias circuits of the second driver stage transistor 509. The two input terminals of the chip 502 are connected to pins 512 and 515 via corresponding bonding wires (e.g., bonding wire 511) (these two pins respectively serve as the first and second input interfaces of the package carrier 500). The output terminal of the chip 503 is connected to pin 514 (the first output interface of the package carrier 500) via bonding wire 513, and the output terminal of the chip 504 is electrically connected to pin 522 (the second output interface of the package carrier 500) via bonding wire 523. Additionally, in... Figure 5 In the example, the encapsulation carrier 500 also includes seven rectangular openings 524.

[0052] Figure 6 An exemplary packaging structure diagram of a packaging carrier 600 according to further embodiments of the present invention is shown schematically. Figure 6As shown, the package carrier 600 (which can be an LGA structure or a QFN structure) includes: metal pads 601 (which can be used to carry circuit elements and provide heat dissipation and ground return); a first transistor chip 604 based on SiC process; a second transistor chip 605 based on SiC process; a driver stage amplifier circuit chip 602 made of Si process, which includes a first input matching circuit 606, a first driver stage transistor 607, a first inter-stage matching network 608 (which is electrically connected to the chip 604 by bonding wires), wherein a first gate bias circuit composed of inductors and capacitors is electrically connected to a pin 617 (which provides a first gate voltage), a pin 615 and a pin 616 are connected to a gate and a drain bias circuit of the first driver stage transistor 607, respectively, and the chip 602 is connected to a pin 612 (a first input interface of the package carrier 600) by a bonding wire 613; a driver stage amplifier circuit chip 603 made of Si process, which includes a second input matching circuit 609, a second driver stage transistor 610, a second inter-stage matching network 611 (which is electrically connected to the chip 605 by bonding wires), wherein a second gate bias circuit composed of inductors and capacitors is electrically connected to a pin 620 (which provides a second gate voltage), a pin 618 and a pin 619 are connected to a gate and a drain bias circuit of the second driver stage transistor 610, respectively, and the chip 603 is connected to a pin 614 (a second input interface of the package carrier 600) by a corresponding bonding wire. An output terminal of the chip 604 is connected to a pin 622 (a first output interface of the package carrier 600) by a bonding wire 621, and an output terminal of the chip 605 is electrically connected to a pin 624 (a second output interface of the package carrier 600) by a bonding wire 623. In addition, in the example of Figure 6 the package carrier 600 also includes seven rectangular openings 625.

[0053] In some embodiments, the inter-stage matching circuit includes a first matching circuit and a second matching circuit, each of the first matching circuit and the second matching circuit is attached to the substrate, the first matching circuit is configured to provide an impedance matching function for the first transistor and the second transistor, and the second matching circuit is configured to provide an impedance matching function for the third transistor and the fourth transistor. Exemplarily, as Figure 7As shown, the package carrier 700 includes: first and second input interfaces 770a and 770b, first and second output interfaces 780a and 780b, a substrate, a first transistor 710, a second transistor 720, a third transistor 730, a fourth transistor 740, and an inter-stage matching circuit, where the inter-stage matching circuit includes a first matching circuit 750a and a second matching circuit 750b (both of which are attached to the substrate of the package carrier 700). The first matching circuit 750a is configured to provide an impedance matching function for the first and second transistors 710 and 720, and the second matching circuit 750b is configured to provide an impedance matching function for the third and fourth transistors 730 and 740. In Figure 7 In the example shown, the first and third transistors 710 and 730 are both silicon (Si) based transistors, and the second and fourth transistors 720 and 740 are both silicon carbide (SiC) based transistors. By employing silicon carbide based transistors with excellent performance at the end stages of both amplification paths of the package carrier 700, the performance of the package carrier can be further improved. In particular, the gate bias voltages provided to the second and fourth transistors 720 and 740 can both be between -6 volts and -4 volts to ensure that they both have excellent performance.

[0054] In some embodiments, the package structure includes a third sub-package structure on the substrate, the third sub-package structure including the inter-stage matching circuit and a biasing circuit configured to provide respective bias voltages for the first, second, third, and fourth transistors. Illustratively, as shown in Figure 8 As shown, the package carrier 800 includes: first and second input interfaces 870a and 870b, first and second output interfaces 880a and 880b, a substrate, a first transistor 810, a second transistor 820, a third transistor 830, a fourth transistor 840, and a third sub-package structure 850, where the third sub-package structure includes an inter-stage matching circuit (dual ISMN) and a biasing circuit. In Figure 8 In the example shown, the first and third transistors 810 and 830 are both silicon (Si) based transistors, and the second and fourth transistors 820 and 840 are both silicon carbide (SiC) based transistors. Figure 8 The main difference between the embodiments shown in Figure 7 and Figure 8 is that, in Figure 7The first matching circuit 750a and the second matching circuit 750b in the third sub-encapsulation structure 850 are integrated (for example, the third sub-encapsulation structure 850 can adopt the form of a chip), and the biasing circuits for providing the respective biasing voltages for the four transistors 810-840 are simultaneously implemented in the third sub-encapsulation structure 850, and the biasing circuits are respectively connected to the external voltage sources 860a, 860b, 860c, 860d via the respective output terminals of the third sub-encapsulation structure 850. In particular, in order to obtain the encapsulation carrier 800 with excellent performance, the gate voltage provided to the second transistor 820 can be between -6V and -4V, the gate voltage provided to the fourth transistor 840 can be between -6V and -4V, the drain voltage provided to the first transistor 810 can be between 10V and 50V, and the drain voltage provided to the third transistor 830 can be between 10V and 50V.

[0055] Figure 9 An exemplary encapsulation structure diagram of a Doherty amplifier according to some embodiments of the present application is schematically shown. Exemplarily, as shown in Figure 9 , the Doherty amplifier can include a carrier board 900, and a first sub-encapsulation structure 904 and a second sub-encapsulation structure 901 arranged on the carrier board 900, the first sub-encapsulation structure 904 can be implemented in a form similar in structure to Figure 4 , in which case Figure 4 part of the structure, for example, the opening 414, can not be necessary), the first sub-encapsulation structure 904 includes the aforementioned first transistor and third transistor. The second sub-encapsulation structure 901 can also be implemented in a form similar in structure to Figure 4 , the second sub-encapsulation structure 901 includes the aforementioned second transistor and fourth transistor. The carrier board 900 can include a printed circuit board (PCB).

[0056] As shown in Figure 9 , the Doherty amplifier further includes a radio frequency input interface 902 coupled to the input terminal of the power divider 903 thereof, a transmission line 906, a heat sink 920, an inductor 907, a transmission line 908, capacitors (905, 909, 910, 914), a radio frequency output interface 911. The capacitor 910 and the transmission line 908 constitute a combining matching network, which combines the first amplification signal generated by the first amplification path in which the first transistor and the second transistor are located, and the second amplification signal generated by the second amplification path in which the third transistor and the fourth transistor are located, and outputs from the radio frequency output interface 911.

[0057] As shown in Figure 9As shown, the Doherty amplifier also includes DC voltage input terminals (912, 913, 915, 916, 917, 918, 919), which transmit corresponding DC voltages to the control terminals (e.g., gates) and output terminals (e.g., drains) of the first, second, third, and fourth transistors, respectively. Exemplarily, an interstage matching network and bias circuit are located between the first sub-package structure 904 and the second sub-package structure 901: the gate bias circuit of the second transistor is formed by components such as capacitor 905, inductor 907, and filter capacitor 914 and is connected to an external DC power supply port 915; similarly, the gate bias circuit of the fourth transistor is connected to an external DC power supply port 919, and these capacitors and inductors, together with corresponding transmission lines (e.g., transmission line 906), form a corresponding interstage matching network. The first and second output nodes of the second sub-package structure 901 are electrically connected to the radio frequency output interface 911 via transmission line 908 and capacitor 910, wherein capacitor 909 forms the drain bias circuit of the second transistor and the fourth transistor and is connected to the external DC power supply port 916.

[0058] Figure 10 The diagram schematically illustrates an exemplary package structure of a Doherty amplifier according to other embodiments of the present invention. Exemplarily, as... Figure 10 As shown, the Doherty amplifier may include a carrier board 1000 and a package carrier 1001 disposed on the carrier board 1000. The package carrier 1001 includes the aforementioned first transistor, second transistor, third transistor, fourth transistor, and other corresponding circuit elements. The carrier board 1000 may include a printed circuit board (PCB). Exemplarily, the package carrier 1001 may be... Figure 6 The encapsulation carrier 600 shown.

[0059] like Figure 10 As shown, the first and second input interfaces of the package carrier 1001 are respectively coupled (via, for example, transmission line 1004) to the output of the power divider 1003 of the Doherty amplifier. The input of the power divider 1003 is coupled to the RF input interface 1002 of the Doherty amplifier. The first and second transistors of the package carrier 1001 are configured to obtain a first amplified signal based on a first signal from the first input interface, and the third and fourth transistors are configured to obtain a second amplified signal based on a second signal from the second input interface. The capacitor 1014 and the transmission line 1013 form a combining matching network, which is coupled between the first and second output interfaces of the package carrier 1001 and the RF output interface 1015 of the Doherty amplifier, and combines the first and second amplified signals and outputs them from the RF output interface 911.

[0060] like Figure 10As shown, the capacitor 1012 and the corresponding transmission line constitute a drain bias circuit of the second transistor and the fourth transistor inside the package carrier 1001 and are connected to the external DC supply port 1008, which provides corresponding drain voltages for these transistors. In addition, the package carrier 1001 is electrically connected to the external DC supply ports (1005, 1006, 1009, 1010) through corresponding transmission lines, which provide corresponding gate and drain voltages for the driving stage amplifiers (including the first transistor and the third transistor) inside the package carrier 1001. Furthermore, the package carrier 1001 is electrically connected to the external DC supply port 1007 and the external DC supply port 1011 through corresponding transmission lines, thereby providing corresponding gate voltages for the second transistor and the fourth transistor inside the package carrier 1001.

[0061] It should be noted that although in the above embodiments described with reference to, for example, Figure 9 and Figure 10 Although the package carrier only includes two input interfaces and corresponding two output interfaces (the first input interface, the second input interface, the first output interface, and the second output interface) in the above embodiments described with reference to, for example, It should be understood by those skilled in the art that when applied to a Doherty amplifier, the package carrier can also include more input interfaces and corresponding output interfaces to realize a Doherty amplifier of more paths (for example, three paths, four paths, or even more). Exemplarily, taking a three-path Doherty amplifier as an example, the package carrier further includes: a third input interface and a third output interface, wherein the third input interface is coupled to an output end of a power divider of the Doherty amplifier, and the third output interface is coupled to a combiner matching network of the Doherty amplifier; a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are located on a substrate of the package carrier, a control end of the fifth transistor is coupled to the third input interface, an output end of the fifth transistor is coupled to a control end of the sixth transistor, an output end of the sixth transistor is coupled to the third output interface, and wherein the fifth transistor and the sixth transistor are configured to obtain a third amplified signal based on a third signal from the third input interface. Correspondingly, the combiner matching network combines the first amplified signal, the second amplified signal, and the third amplified signal and outputs them from a radio frequency output interface of the Doherty amplifier.

[0062] Figure 11 A performance example diagram of a Doherty amplifier according to some embodiments of the present application is schematically shown. As shown, Figure 11 as described above, Figure 2The input interface of the package carrier 1100 of the illustrated architecture is connected to the radio frequency input interface of the Doherty amplifier through a power divider to obtain the corresponding radio frequency input, and the output interface of the package carrier 1100 is connected to the radio frequency output interface through the power combiner (i.e. the combining matching network) of the Doherty amplifier to realize the corresponding radio frequency output. Through Figure 11 It can be seen that the two radio frequency paths of the Doherty amplifier can simultaneously obtain high gain performance, and have a wider bandwidth than the Doherty amplifier based on Figure 1A The Doherty amplifier of the illustrated package carrier architecture has a wider bandwidth.

[0063] It will be understood that, although the terms first, second, etc. can be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these terms. These terms are only used to distinguish one device, element, component or part from another. The "connection", "coupling" mentioned herein can be any one of "direct connection" or "indirect connection".

[0064] Although the present application has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Rather, the scope of the present application is limited only by the claims that follow. Additionally, although individual features can be included in different claims, these can possibly be advantageously combined, and the inclusion in different claims does not imply that a combination of features is not feasible and / or advantageous. The order of the features in the claims does not imply any specific order of working of the features. Furthermore, in the claims, the word "comprising" does not exclude other elements, and the terms "a" or "an" do not exclude a plurality. The number of references in the claims is merely intended to further clarify the claim and is not intended to limit the scope of the claims in any way.

Claims

1. A package carrier, comprising: a first input interface and a second input interface; a first output interface and a second output interface; a substrate; a first transistor and a second transistor, wherein the first transistor and the second transistor are located on the substrate, a control terminal of the first transistor is coupled to the first input interface, an output terminal of the first transistor is coupled to a control terminal of the second transistor, and an output terminal of the second transistor is coupled to the first output interface; a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are located on the substrate, a control terminal of the third transistor is coupled to the second input interface, an output terminal of the third transistor is coupled to a control terminal of the fourth transistor, and an output terminal of the fourth transistor is coupled to the second output interface, and wherein each of the first transistor and the third transistor comprises a silicon-based transistor, and at least one of the second transistor and the fourth transistor comprises a silicon carbide-based transistor; and an inter-stage matching circuit configured to provide an impedance matching function for the first transistor and the second transistor, and to provide an impedance matching function for the third transistor and the fourth transistor.

2. The package carrier of claim 1, wherein the package carrier further comprises a first sub-package structure, the first sub-package structure being located on the substrate and comprising the first transistor and the third transistor.

3. The package carrier of claim 1, wherein the package carrier further comprises a second sub-package structure, the second sub-package structure being located on the substrate and comprising the second transistor and the fourth transistor.

4. The package carrier of claim 3, wherein the second sub-package structure further comprises at least one opening, the at least one opening penetrating through at least a portion of the second sub-package structure.

5. The package carrier of claim 4, wherein at least a portion of the at least one opening is grounded.

6. The package carrier of claim 3, wherein the second sub-package structure further comprises: a first input node coupled to the output terminal of the first transistor and the control terminal of the second transistor; a second input node coupled to the output terminal of the third transistor and the control terminal of the fourth transistor; a first capacitor having one end coupled to the output terminal of the second transistor and another end coupled to a first output node of the second sub-package structure; a second capacitor having one end coupled to the output terminal of the fourth transistor and another end coupled to a second output node of the second sub-package structure; a base to carry at least some circuit elements in the second sub-package structure; and a protective cover to cooperate with the base to enclose at least some circuit elements in the second sub-package structure.

7. The package carrier of claim 6, wherein a length of the base and the protective cover is between 10 millimeters and 20 millimeters, and wherein a length of the second transistor and the fourth transistor is between 5 millimeters and 10 millimeters. ​ 8. The package carrier of claim 6, wherein, At least one of the coupling between the first input node and the output terminal of the first transistor and the control terminal of the second transistor, the coupling between the second input node and the output terminal of the third transistor and the control terminal of the fourth transistor, the coupling between the first capacitor and the output terminal of the second transistor and the first output node of the second sub-package structure, and the coupling between the second capacitor and the output terminal of the fourth transistor and the second output node of the second sub-package structure can be implemented in any one of the following forms: a bonding wire, a microstrip line.

9. The package carrier of claim 1, wherein the inter-stage matching circuit comprises a first matching circuit and a second matching circuit, each of the first matching circuit and the second matching circuit being attached to the substrate, the first matching circuit being configured to provide an impedance matching function for the first transistor and the second transistor, the second matching circuit being configured to provide an impedance matching function for the third transistor and the fourth transistor.

10. The package carrier of claim 1, wherein the package carrier comprises a third sub-package structure on the substrate, the third sub-package structure comprising the inter-stage matching circuit and a biasing circuit, the biasing circuit being configured to provide respective bias voltages for the first transistor, the second transistor, the third transistor, and the fourth transistor.

11. The package carrier of claim 1, wherein, The gate bias voltage provided to each of the second transistor and the fourth transistor is between -6 volts and -4 volts.

12. A Doherty amplifier, comprising: a radio frequency input interface coupled to an input terminal of a power divider of the Doherty amplifier; the package carrier of any one of claims 1-11, wherein the first input interface and the second input interface of the package carrier are coupled to output terminals of the power divider, the first transistor and the second transistor are configured to obtain a first amplified signal based on a first signal from the first input interface, the third transistor and the fourth transistor are configured to obtain a second amplified signal based on a second signal from the second input interface; a combining matching network coupled between the first output interface, the second output interface of the package carrier, and a radio frequency output interface of the Doherty amplifier.

13. The Doherty amplifier of claim 12, wherein the package carrier further comprises: a third input interface and a third output interface, wherein the third input interface is coupled to an output terminal of the power divider, and the third output interface is coupled to the combining matching network. a fifth transistor and a sixth transistor, wherein the fifth transistor and the sixth transistor are located on the substrate, a control terminal of the fifth transistor is coupled to the third input interface, an output terminal of the fifth transistor is coupled to a control terminal of the sixth transistor, an output terminal of the sixth transistor is coupled to the third output interface, and wherein the fifth transistor and the sixth transistor are configured to obtain a third amplified signal based on a third signal from the third input interface.

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