Chip stacking packaging structure and packaging product
By using a chip stacking package structure with a accommodating groove on the substrate, the first chip is connected to the pad in the accommodating groove, eliminating the need for a wire bonding structure. Electrical connection is achieved by combining conductive wires and conductive pillars, which solves the problem of large size of multi-chip stacked packages and realizes miniaturized and thin packaging.
Patent Information
- Application Number
- CN202423191977.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-23
AI Technical Summary
Existing wire bonding stacking structures result in large package sizes when multiple chips are stacked, making it difficult to achieve miniaturization and thinning.
The chip stacking packaging structure with a receiving groove on the substrate is adopted. The first chip is placed in the receiving groove and connected to the pad in the receiving groove through the first bump, eliminating the need for wire bonding structure. The second chip is electrically connected to the substrate or the first chip. The back-to-back mounting method is adopted, and the electrical connection is achieved by combining conductive lines and conductive posts.
It effectively reduces the package height and lateral dimensions, achieving miniaturized and thinner packaging. The structure is compact, the process is simple, and it is easy to accurately control the package thickness, making it suitable for mass production.
Smart Images
Figure CN223680097U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor packaging, especially to a chip stack packaging structure and a packaging product. BACKGROUND
[0002] With the increasing integration of electronic products, the requirement for packaging size is also increasing, and the overall packaging structure needs to be miniaturized and thinned. In particular, the capacity stack of memory chips inevitably occupies additional packaging volume.
[0003] In the current wire bonding stack structure, each chip added in the height direction needs to reserve sufficient wire bonding space. With more stacked chips and higher height, the wire becomes more complex, and more space needs to be reserved to accommodate the wire, resulting in a larger overall packaging size. In addition, in order to ensure the effectiveness of electrical isolation and interconnection, there must be a proper safety distance between the pads of adjacent chips and between the pads, and between the wires, which also increases the packaging size.
[0004] Therefore, how to realize the thin and small size of the stacked structure of multiple chips is a technical problem that needs to be solved in the industry at present. UTILITY MODEL CONTENT
[0005] The utility model aims at providing a chip stack packaging structure and a packaging product, which is beneficial to reducing the packaging size, reducing the volume, and realizing miniaturized packaging.
[0006] In a first aspect, the utility model provides a chip stack packaging structure, comprising:
[0007] A substrate is provided with a receiving groove; the groove bottom of the receiving groove is provided with a first pad;
[0008] A first chip is provided with a first bump; one side of the first chip provided with the first bump faces the groove bottom of the receiving groove, and the first bump and the first pad are electrically connected;
[0009] A second chip is provided with a second bump; one side of the second chip away from the second bump is connected to one side of the first chip away from the first bump;
[0010] The second chip is electrically connected to the first chip and / or the substrate.
[0011] In an optional embodiment, a bonding wire is further included; the substrate is provided with a second pad, one end of the bonding wire is electrically connected to the second bump, and the other end is electrically connected to the second pad.
[0012] In an optional embodiment, the second pad is located on a side surface of the substrate having the accommodation groove.
[0013] In an optional embodiment, the second pad is located on a bottom or a wall of the accommodation groove.
[0014] In an optional embodiment, the substrate is provided with a conductive wire, one end of the conductive wire is electrically connected with the first pad, and the other end of the conductive wire is electrically connected with the second pad.
[0015] In an optional embodiment, the substrate is provided with a wire embedding groove, and the conductive wire is arranged in the wire embedding groove.
[0016] In an optional embodiment, the chip stack package structure further comprises a conductive column, the conductive column penetrates through the first chip and the second chip, one end of the conductive column is electrically connected with the first bump, and the other end of the conductive column is electrically connected with the second bump.
[0017] In an optional embodiment, the thickness of the chip stack package structure is H, H = H1 + H2 - D, wherein H1 is the thickness of the substrate, H2 is the thickness of the stacked chips formed by the first chip and the second chip, and D is the depth of the accommodation groove.
[0018] In an optional embodiment, the first chip and the second chip are provided with an adhesive film layer.
[0019] In a second aspect, the utility model provides a packaging product, including any one of the chip stack package structure of preceding embodiment.
[0020] The chip stack package structure and the packaging product provided by the embodiments of the utility model have the following beneficial effects:
[0021] The chip stack package structure provided by the embodiments of the utility model is provided with an accommodation groove on the substrate, and the first chip is arranged in the accommodation groove, so that the overall packaging height is reduced. The first bump of the first chip is connected with the first pad in the accommodation groove, and the wire bonding structure is omitted, which is beneficial to reduce the overall packaging height and the transverse size of the package, compact the structure, reduce the packaging volume, and realize miniaturization and thin-type packaging.
[0022] The packaging product provided by the embodiments of the utility model comprises the chip stack package structure, and has the advantages of compact structure, small volume, high-density integration, miniaturization and thin-type production of the packaging product. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described in the following description are some embodiments of the present application, and all other drawings obtained by those skilled in the art without creative labor on the basis of these drawings also belong to the protection scope of the present application.
[0024] Figure 1 The first structure schematic diagram of the chip stack packaging structure provided by the embodiment of the present application is shown in the figure.
[0025] Figure 2 The second structure schematic diagram of the chip stack packaging structure provided by the embodiment of the present application is shown in the figure.
[0026] Figure 3 The third structure schematic diagram of the chip stack packaging structure provided by the embodiment of the present application is shown in the figure.
[0027] Icon: 100-chip stack packaging structure; 110-substrate; 111-receiving groove; 112-first pad; 113-second pad; 114-welding ball; 120-first chip; 121-first bump; 130-second chip; 131-second bump; 140-bonding wire; 150-conductive wire; 160-conductive column; 170-gel film layer; 180-plastic encapsulation body. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to make a clear and complete description of the technical scheme in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.
[0029] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor also belong to the protection scope of the present application.
[0030] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.
[0031] In the description of the utility model, it is necessary to explain that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "internal", "external" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the utility model product is used, and are only for the convenience of describing the utility model and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the utility model. In addition, the terms "first", "second", "third" and the like are only used for differentiation in description and cannot be understood as indicating or implying relative importance.
[0032] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.
[0033] In the description of the utility model, it is also necessary to explain that, unless otherwise explicitly specified and limited, the terms "setting", "mounting", "connecting", "connecting" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication between two elements inside. For ordinary skilled persons in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.
[0034] Some embodiments of the utility model will be described in detail below in combination with the drawings. In the case of no conflict, the following examples and features in the examples can be combined with each other.
[0035] The chip stacking packaging structure provided by the embodiment of the utility model can effectively reduce the packaging size, reduce the packaging volume, and realize miniaturization and thin packaging.
[0036] In combination with Figure 1The chip stack package structure 100 comprises a substrate 110, a first chip 120 and a second chip 130. The substrate 110 is provided with a receiving groove 111, and the groove bottom of the receiving groove 111 is provided with a first pad 112. The first chip 120 is provided with a first bump 121, and the side of the first chip 120 provided with the first bump 121 faces the groove bottom of the receiving groove 111, and the first bump 121 is electrically connected with the first pad 112. The second chip 130 is provided with a second bump 131, and the side of the second chip 130 away from the second bump 131 is connected to the side of the first chip 120 away from the first bump 121. The second chip 130 is electrically connected with the first chip 120 and / or the substrate 110. Since the substrate 110 is provided with the receiving groove 111, and the first chip 120 is arranged in the receiving groove 111, the overall package height is reduced. The first bump 121 of the first chip 120 is connected with the first pad 112 in the receiving groove 111, and the wire bonding structure is omitted, which is beneficial to reduce the overall package height and the lateral size of the package, and the structure is compact, the package volume is reduced, and miniaturization and thinness packaging are facilitated.
[0037] In the embodiment, the position of the first bump 121 corresponds to the position of the first pad 112. The first bump 121 and the first pad 112 are welded to realize the electrical connection between the first chip 120 and the substrate 110.
[0038] Since the first chip 120 and the second chip 130 are arranged in a back-to-back manner, there is no connecting bump on the mounting surface of the two, and there is no need to avoid the connecting bump, that is, there is no need to use staggered stacking. The side surfaces of the first chip 120 and the second chip 130 can be aligned, which reduces the package area, that is, reduces the lateral size of the package. Moreover, this stacking method has simple process, small thickness deviation, and is convenient for accurately controlling the thickness of the package product.
[0039] It can be understood that the second chip 130 can be electrically connected with the substrate 110. Alternatively, the second chip 130 can be electrically connected with the first chip 120. Alternatively, the second chip 130 can be electrically connected with the first chip 120 and the substrate 110 respectively.
[0040] Optionally, the second chip 130 is connected with the substrate 110 through a bonding wire 140. The substrate 110 is provided with a second pad 113, one end of the bonding wire 140 is electrically connected with the second bump 131, and the other end is electrically connected with the second pad 113. In the embodiment, one end of the bonding wire 140 is welded with the second bump 131, and the other end is welded with the second pad 113. In this way, the electrical connection between the second chip 130 and the substrate 110 is realized. It should be noted that the material of the bonding wire 140 can be a single metal such as iron, aluminum, silver, copper, gold or tin, or an alloy material such as any two or more of iron, aluminum, silver, copper, gold and tin, as long as electrical connection can be realized, which is not limited here. In the embodiment, the bonding wire 140 is made of gold wire or copper wire, which has good conductivity and good toughness and is not easy to break.
[0041] Optionally, the second pad 113 is located on the side surface of the substrate 110 having the accommodating groove 111. In order to shorten the wire bonding path, the second pad 113 is located on the upper surface of the substrate 110, i.e. the side surface of the substrate 110 having the accommodating groove 111. In this way, the wire bonding operation is more convenient, the wire bonding path is short, the signal transmission efficiency is high, and the loss is low.
[0042] Of course, in other embodiments, the second pad 113 can also be designed on the back surface of the substrate 110, i.e. on the side surface of the substrate 110 away from the accommodating groove 111. One end of the bonding wire 140 is welded with the second bump 131, and the other end can be routed through the side surface of the substrate 110 to the back surface and welded with the second pad 113. Alternatively, a through hole is formed on the substrate 110, one end of the bonding wire 140 is welded with the second bump 131, and the other end can extend through the through hole to the back surface and be welded with the second pad 113. Here, no specific limitation is made.
[0043] It can be understood that the size of the accommodating groove 111 can be designed according to the size of the first chip 120, such as that the cross section of the groove is substantially equal to the cross section of the first chip 120. The second pad 113 is located outside the accommodating groove 111. In this way, the accommodating groove 111 also plays a limiting role on the first chip 120. Optionally, the bottom of the first chip 120 and the groove bottom of the accommodating groove 111 can be filled with protective glue, which protects the welding structure of the first bump 121 and the first pad 112, and the electrical connection is more reliable. In addition, the protective glue can better fix the first chip 120 in the accommodating groove 111, and the structure is more stable.
[0044] Of course, in other embodiments, the cross-sectional size of the accommodating groove 111 can be larger than the cross-sectional size of the first chip 120. That is, after the first chip 120 is installed into the accommodating groove 111, there is still enough space between the first chip 120 and the groove wall of the accommodating groove 111. In the subsequent packaging process, the space can be filled with protective glue or a plastic package 180, which is not limited here.
[0045] Optionally, the cross-sectional dimension of the accommodating groove 111 can be larger than that of the first chip 120. The second pad 113 can be designed on the groove bottom or groove wall of the accommodating groove 111. In this way, the electrical connection between the second chip 130 and the second pad 113 on the substrate 110 can also be achieved.
[0046] In combination Figure 2 The groove bottom of the accommodating groove 111 is provided with the second pad 113, and the second bump 131 of the second chip 130 is electrically connected to the second pad 113 through the bonding wire 140.
[0047] Similarly, if the groove wall of the accommodating groove 111 is provided with the second pad 113, the second pad 113 on the groove wall can also be electrically connected to the second bump 131 on the second chip 130 through the bonding wire 140.
[0048] Optionally, the substrate 110 is provided with a conductive wire 150, one end of the conductive wire 150 is electrically connected to the first pad 112, and the other end is electrically connected to the second pad 113. The conductive wire 150 extends from the first pad 112 inside the substrate 110 to the upper surface of the substrate 110 and is connected to the second pad 113.
[0049] Optionally, the substrate 110 is provided with a buried wire groove, and the conductive wire 150 is arranged in the buried wire groove. It can be understood that the buried wire groove extends from the first pad 112 at the groove bottom of the accommodating groove 111, extends through the inside of the substrate 110 to the second pad 113 on the surface of the substrate 110, and the routing mode of the conductive wire 150 is consistent with the extension path of the buried wire groove. In this way, the electrical connection between the first pad 112 and the second pad 113 can be achieved. In other words, the second chip 130 can be electrically connected to the substrate 110 through the bonding wire 140, and can also be indirectly electrically connected to the first chip 120 through the bonding wire 140 and the conductive wire 150.
[0050] It can be understood that the conductive wire 150 is used to rewire and distribute the substrate 110, which has lower cost than wafer rewire and more flexible routing, and can be compatible with multiple different types of chips.
[0051] In combination Figure 3 Optionally, in some embodiments, the first chip 120 and the second chip 130 can be directly connected in a vertical direction through a TSV (Through Silicon Via) perforation process. TSV is the abbreviation of Through Silicon Via, which means silicon perforation. The chip stack package structure 100 further comprises a conductive column 160, which penetrates the first chip 120 and the second chip 130. One end of the conductive column 160 is electrically connected to the first bump 121, and the other end is electrically connected to the second bump 131. In this way, the vertical interconnection between the first chip 120 and the second chip 130 is achieved, the conductive path is shorter, the transmission efficiency is higher, and the package size is smaller.
[0052] It can be understood that the thickness of the chip stack packaging structure is H, H=H1+H2-D; wherein, H1 is the thickness of the substrate 110, H2 is the thickness of the stacked chip formed by the first chip 120 and the second chip 130, and D is the depth of the accommodating groove 111.
[0053] Optionally, the depth of the accommodating groove 111 can be flexibly set according to actual conditions, and the depth D of the accommodating groove 111 can be less than, equal to, or greater than H2. For example, it can be equal to the thickness of the first chip 120, or greater than the thickness of the first chip 120 and less than the sum of the thickness of the first chip 120 and the thickness of the second chip 130, or equal to the sum of the thickness of the first chip 120 and the thickness of the second chip 130. Herein, no specific limitation is made.
[0054] In the embodiment, the depth of the accommodating groove 111 is equal to the thickness of the first chip 120. In this way, the overall packaging height can be reduced, the second chip 130 and the substrate 110 can be connected through the bonding wire 140, and the heat dissipation performance can be improved.
[0055] Optionally, a glue film layer 170 is arranged between the first chip 120 and the second chip 130. The first chip 120 and the second chip 130 are fixed in a back-to-back bonding manner. The glue film layer 170 can include but is not limited to DAF insulating glue.
[0056] It should be noted that the number and type of the first chip 120 and the second chip 130 are not limited, and the first chip 120 and the second chip 130 can be storage chips or other types of chips, which are not specifically limited herein.
[0057] Optionally, the chip stack packaging structure 100 further includes a plastic package 180 arranged on the upper surface (front surface) of the substrate 110, for covering the second chip 130 and the bonding wire 140, etc., and protecting the components on the substrate 110. The back surface of the substrate 110 is provided with solder balls 114 for electrical connection with other external modules such as a circuit board.
[0058] The utility model embodiment further provides a packaging product comprising the aforementioned chip stack packaging structure 100. The structure is compact and small in size, which is conducive to realizing high-density integration and realizing the miniaturization and thinness production of the packaging product.
[0059] In summary, the chip stack packaging structure 100 and the packaging product provided by the utility model embodiment have the following beneficial effects, including:
[0060] The chip stacking packaging structure 100 provided by the embodiment of the utility model, the substrate 110 is equipped with the accommodation groove 111, the first chip 120 is located in the accommodation groove 111, and the overall packaging height is reduced. The first bump 121 of the first chip 120 and the first pad 112 in the accommodation groove 111 are welded, the wire structure is saved, the electric connection is stable and reliable, the overall packaging height is reduced and the transverse size of the packaging is reduced, the structure is compact, the packaging volume is reduced, miniaturization and thin type packaging are facilitated. And the overall process operation of the chip stacking packaging structure 100 is simple and efficient, and mass production is facilitated.
[0061] The packaging product provided by the embodiment of the utility model, including the chip stacking packaging structure 100, the structure is compact and small, high-density integration is facilitated, and miniaturization and thin type production of the packaging product are realized.
[0062] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the utility model, and not to limit them; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; any modification, equivalent replacement, improvement, etc. should be included in the protection scope of the utility model.
Claims
1. A chip stack package structure, characterized by, The chip stack package structure comprises: a substrate (110) provided with a receiving groove (111); a groove bottom of the receiving groove (111) is provided with a first pad (112); a first chip (120) provided with a first bump (121); one side of the first chip (120) provided with the first bump (121) faces the groove bottom of the receiving groove (111), and the first bump (121) and the first pad (112) are electrically connected; a second chip (130) provided with a second bump (131); one side of the second chip (130) away from the second bump (131) is connected to one side of the first chip (120) away from the first bump (121); the second chip (130) is electrically connected to the first chip (120) and / or the substrate (110).
2. The chip stack package structure of claim 1, wherein, The chip stack package structure further comprises a bonding wire (140); the substrate (110) is provided with a second pad (113), one end of the bonding wire (140) is electrically connected to the second bump (131), and the other end is electrically connected to the second pad (113).
3. The chip stack package structure of claim 2, wherein, The second pad (113) is located on a side surface of the substrate (110) having the receiving groove (111).
4. The chip stack package structure of claim 2, wherein, The second pad (113) is located on the groove bottom or groove wall of the receiving groove (111).
5. The chip stack package structure of claim 2, wherein, The substrate (110) is provided with a conductive wire (150), one end of the conductive wire (150) is electrically connected to the first pad (112), and the other end is electrically connected to the second pad (113).
6. The chip stack package structure of claim 5, wherein, The substrate (110) is provided with a wire embedding groove, and the conductive wire (150) is arranged in the wire embedding groove.
7. The chip stack package structure of claim 1, wherein, The chip stack package structure further comprises a conductive column (160) penetrating the first chip (120) and the second chip (130), one end of the conductive column (160) is electrically connected to the first bump (121), and the other end is electrically connected to the second bump (131).
8. The chip stack package structure of claim 1, wherein, The thickness of the chip stack package structure is H, H=H1+H2-D; wherein H1 is the thickness of the substrate (110), H2 is the thickness of the stacked chips formed by the first chip (120) and the second chip (130), and D is the depth of the receiving groove (111).
9. The chip stack package structure of any one of claims 1 to 8, wherein, The first chip (120) and the second chip (130) are provided with a glue film layer (170).
10. A packaged product characterized by comprising The chip stack package structure comprises any one of claims 1 to 9. The chip stack package structure comprises any one of claims 1 to 9.