Pipeline analog-to-digital converter
By designing a two-stage quantizer structure, the balance between power consumption and linearity in the existing technology is solved, achieving the goal of reducing power consumption and linearity while ensuring the linearity of the ADC.
Patent Information
- Application Number
- CN202423264658.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2034-12-30
AI Technical Summary
Existing pipelined ADC designs face a difficult balance between power consumption and linearity. Increasing the number of bits in the first-stage quantization improves linearity but increases power consumption, while decreasing the number of bits in the first-stage quantization reduces linearity. Furthermore, existing designs are complex and costly.
A two-stage cascaded quantization stage unit structure is adopted, in which the output of the second quantizer is fed back to the minor bit of the first quantizer. The output is connected to the quantizer of the second quantization stage unit through an interstage amplifier to realize the recalculation of the residual. By quantizing the input signal multiple times, fine adjustment and reuse of the signal are achieved through the design of switches and capacitors.
This approach achieves improved ADC linearity while reducing the power consumption of the first-stage quantizer and interstage amplifier, thus lowering power consumption.
Smart Images
Figure CN223681060U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to analog digital converter design technical field especially relates to a pipeline type analog digital converter. BACKGROUND
[0002] Analog digital converter (ADC) is an important device for converting analog signals into digital signals, and has a wide range of applications in modern electronic devices. Among them, in high-speed, high-precision data acquisition system, pipeline type (Pipeline) ADC is widely used due to its advantages of high sampling rate and high resolution. In the pipeline type ADC, the input analog signal is quantized by multiple quantization stages in turn, and each quantization stage includes a digital-to-analog converter (DAC) and a quantizer.
[0003] The existing pipeline type ADC is usually composed of multiple identical quantization stages, and each quantization stage quantizes the input signal once. In practical applications, the number of bits of the first-stage quantizer determines the dynamic range and linearity of the entire ADC. However, increasing the number of bits of the first-stage quantizer significantly increases the accuracy requirement of the first-stage quantizer, and in turn significantly increases the power consumption and area. In order to balance the linearity and power consumption, the existing design adopts a smaller number of first-stage quantization bits, but this method reduces the linearity of the ADC.
[0004] Therefore, the existing pipeline type ADC design faces a dilemma, that is, if a smaller number of first-stage quantization bits is used, the linearity of the ADC will be reduced, but if a larger number of first-stage quantization bits is used, the power consumption will be greatly increased.
[0005] In addition, the existing design usually requires that the DAC and quantizer of each quantization stage have high performance, which increases the complexity and cost of the design.
[0006] Therefore, the existing pipeline type ADC design has a difficult balance between power consumption and linearity. SUMMARY
[0007] The technical problem to be solved by the utility model is how to balance the conflict between linearity, power consumption and cost of the pipeline type ADC.
[0008] The utility model provides a pipeline type analog digital converter, at least including first, second two-stage cascaded quantization stage units, each quantization stage unit is equipped with a DAC and quantizer, and a first-stage inter-stage amplifier is arranged between the first quantization stage unit and the second quantization stage unit, wherein:
[0009] The output end of the second quantization stage unit is connected with the minor bits of the DAC of the first quantization stage unit through a multiplier to re-generate the residual of the first quantization stage unit, and the residual is connected with the input end of the quantizer of the second quantization stage unit through the first inter-stage amplifier.
[0010] Further, the second quantization stage unit performs quantization at least twice.
[0011] Further, the first quantization stage unit comprises a switch array, a capacitor array, a comparator and a logic control module, wherein:
[0012] The input signal is sequentially connected with the negative input end of the switch array, the capacitor array and the comparator, the positive input end of the comparator is grounded, the output end of the comparator is connected with the input end of the logic control module, the output end of the logic control module outputs the first-stage quantized signal to the combiner, and the output end of the logic control module is connected with the switch array.
[0013] Further, the DAC of the first quantization stage unit is composed of the capacitor C1 and the capacitor C2.
[0014] Further, the second quantization stage unit comprises a switch array, a capacitor array, a second-stage quantizer and a multiplier, and an inter-stage amplifier is arranged between the first quantization stage unit and the second quantization stage unit, wherein:
[0015] The input signal is sequentially connected with the negative input end of the switch array, the capacitor array and the input end of the inter-stage amplifier, the output end of the inter-stage amplifier is connected with the input end of the second-stage quantizer, the output end of the second-stage quantizer is connected with the input end of the multiplier, and the output end of the multiplier is connected with the switch array.
[0016] Further, the inter-stage amplifier and the second-stage quantizer are utilized at least twice.
[0017] Compared with the prior art, the embodiment of the utility model has the following beneficial effects:
[0018] The utility model discloses a second quantization stage unit is quantized the result is fed back to the lower bit of the DAC of the second quantization stage unit, then re-amplifies the residual of the first quantization stage unit, makes the second quantization stage unit re-quantizes again, greatly reduces the performance requirement of the first-stage quantizer and inter-stage amplifier, thereby improves the linearity of ADC.
[0019] Meanwhile, the quantization process repeatedly utilizes the inter-stage amplifier and the second-stage quantizer, greatly reduces the power consumption of the first-stage quantizer and the inter-stage amplifier, that is, realizes the target of reducing the power consumption while guaranteeing the linearity of the pipeline ADC. BRIEF DESCRIPTION OF DRAWINGS
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.
[0021] Figure 1 The circuit principle schematic diagram disclosed by the embodiments of the present application.
[0022] In the drawings:
[0023] 10, first quantization stage unit; 20, second quantization stage unit. DETAILED DESCRIPTION
[0024] In order to make the person skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0025] As known in the art, the first quantizer plays a crucial role in the pipeline ADC, as it directly determines the dynamic range and linearity of the subsequent quantization stages. If the first quantizer has insufficient bits, it will not be able to provide sufficient resolution to support the high accuracy requirements of the subsequent quantization stages, resulting in a decrease in the performance of the entire ADC. If the first quantizer has a high number of bits, it will increase the power consumption consumed by the first stage.
[0026] The present application aims to solve the conflict problem between the decrease of ADC linearity caused by the small number of first quantization bits and the great increase of power consumption consumed by the first stage caused by the large number of first quantization bits in the traditional pipeline ADC design.
[0027] The pipeline ADC provided by the present application comprises at least two cascaded quantization stage units, i.e. a first quantization stage unit 10 and a second quantization stage unit 20, each of which is configured with a DAC and a quantizer, and a first inter-stage amplifier is arranged between the first quantization stage unit 10 and the second quantization stage unit 20.
[0028] In a further aspect of the embodiment, the output of the second quantization stage unit 20 is connected via a multiplier to the less significant bits of the DAC of the first quantization stage unit 10 to reproduce the residue of the first quantization stage unit 10, and the residue is connected via a first inter-stage amplifier to the input of the quantizer of the second quantization stage unit 20.
[0029] The skilled person further explains that the "less significant bits" of the DAC of the first quantization stage unit 10, i.e. the lower bits of the DAC of the first quantization stage unit 10, refer to the bits of the DAC with smaller weights, which have a relatively smaller but still important influence on the final output.
[0030] Referring to Fig. 2, a schematic diagram of a modified pipeline ADC with two stages of cascaded first quantization stage unit 10 and second quantization stage unit 20 is shown. Figure 1
[0031] First, the structure design of the first quantization stage unit 10 is described.
[0032] The first quantization stage unit 10 comprises a switch array, a capacitor array, a comparator and a logic control module.
[0033] In a further aspect of the embodiment, the input signal is connected in sequence to the switch array, the capacitor array and the negative input of the comparator, the positive input of the comparator is connected to ground, the output of the comparator is connected to the input of the logic control module, the output of the logic control module outputs the first-stage quantized signal to the combiner, and the output of the logic control module is connected to the switch array.
[0034] The skilled person further explains that the logic control module controls the opening and closing of the corresponding switches in the switch array according to the received quantization result of the second quantization stage unit 20. These switches are connected to different bits of the DAC of the first quantization stage unit 10 to achieve fine adjustment of the lower bits.
[0035] The DAC of the first quantization stage unit 10 is composed of capacitor C1 and capacitor C2. In the DAC of the first quantization stage unit 10, the capacitor array is the key component for realizing the conversion of the analog signal. Each capacitor corresponds to a specific weight, and the combination of different weights can be achieved by the control of the switches.
[0036] Next, the structure design of the second quantization stage unit 20 is described.
[0037] The second quantization stage unit 20 comprises a switch array, a capacitor array, a second-stage quantizer and a multiplier, and an inter-stage amplifier is provided between the first quantization stage unit 10 and the second quantization stage unit 20.
[0038] In a further scheme of the embodiment, the input signal is sequentially connected with the switch array, the capacitor array and the input end of the inter-stage amplifier, the output end of the inter-stage amplifier is connected with the input end of the second quantizer, the output end of the second quantizer is connected with the input end of the multiplier, and the output end of the multiplier is connected with the switch array.
[0039] In particular, the second quantization stage unit 20 can be repeatedly quantized multiple times.
[0040] In other schemes, there can also be a later-stage inter-stage amplifier and quantizer after the second quantization stage unit 20.
[0041] According to actual needs, different quantization stages and bit numbers are selected to meet the needs of different application scenarios.
[0042] The utility model discloses a feedback quantization result of the second quantization stage unit 20 to the lower bit of the DAC of the first quantization stage unit 10, then re-amplifies the residual error of the first quantization stage unit 10, and the second quantization stage unit 20 re-quantizes, and this process can be repeated multiple times. The performance requirement of the first-stage quantizer and the inter-stage amplifier is greatly reduced, thereby improving the linearity of the ADC. At the same time, by repeatedly using the inter-stage amplifier and the second-stage quantizer, the power consumption of the first-stage quantizer and the inter-stage amplifier is greatly reduced. The linearity of the ADC is ensured while the power consumption is reduced.
[0043] The utility model discloses can be widely applied in the field of application such as analog-digital converter design field, integrated circuit design field and signal processing technology field.
[0044] Firstly, in the field of analog-digital converter design, by repeatedly using the inter-stage amplifier and the second-stage quantizer, the performance requirement of the first-stage quantizer and the inter-stage amplifier is greatly reduced, thereby reducing the design cost. This new structure has important significance for improving the performance of the analog-digital converter and reducing the cost.
[0045] Secondly, in the field of integrated circuit design, the utility model provides a new integrated circuit design idea, by optimizing the structure of the pipeline ADC, the balance of power consumption and linearity is realized, which has important value for improving the performance of the integrated circuit and reducing the power consumption. With the development of integrated circuit technology, the demand for high-performance and low-power integrated circuits is increasing, and the technical scheme is expected to be widely applied in the field of integrated circuit design.
[0046] Finally, in the field of signal processing technology, the new structure of the pipeline ADC provided by the technical scheme can improve the precision and quality of signal processing, which has important significance for the development of signal processing technology. With the wide application of signal processing technology in various fields such as communication, audio processing, image processing, etc., the technical scheme is expected to be widely applied in the field of signal processing technology.
[0047] Although the embodiments of the utility model have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and spirits of the utility model, and the scope of the utility model is defined by the appended claims and their equivalents.
Claims
1. A pipelined analog-to-digital converter, characterized in that, It includes at least two cascaded quantization stage units, each equipped with a DAC and a quantizer. A first interstage amplifier is provided between the first quantization stage unit (10) and the second quantization stage unit (20); wherein: The output of the second quantization stage unit (20) is connected to the minor bit of the DAC of the first quantization stage unit (10) via a multiplier to regenerate the residual of the first quantization stage unit (10), and the residual is connected to the input of the quantizer of the second quantization stage unit (20) via the first interstage amplifier.
2. The pipelined analog-to-digital converter according to claim 1, characterized in that, The second quantization level unit (20) is quantized at least twice.
3. The pipelined analog-to-digital converter according to claim 1, characterized in that, The first quantization level unit (10) includes a switch array, a capacitor array, a comparator, and a logic control module, wherein: The input signal is connected to the negative input terminal of the comparator in sequence through the switch array, the capacitor array, and grounded. The output terminal of the comparator is connected to the input terminal of the logic control module. The output terminal of the logic control module outputs the first-stage quantized signal to the combiner, and the output terminal of the logic control module is connected to the switch array.
4. The pipelined analog-to-digital converter according to claim 3, characterized in that, The DAC of the first quantization level unit (10) is composed of capacitors C1 and C2.
5. The pipelined analog-to-digital converter according to claim 3, characterized in that, The second quantization stage unit (20) includes a switch array, a capacitor array, a second-stage quantizer, and a multiplier. An interstage amplifier is provided between the first quantization stage unit (10) and the second quantization stage unit (20); wherein: The input signal is connected to the input terminal of the interstage amplifier in sequence through the switch array, the capacitor array, the output terminal of the interstage amplifier, the input terminal of the second-stage quantizer, the output terminal of the second-stage quantizer, the input terminal of the multiplier, and the output terminal of the multiplier, which is connected to the switch array.
6. The pipelined analog-to-digital converter according to claim 5, characterized in that, The interstage amplifier and the second-stage quantizer are used at least twice.