Watchdog function implementation circuit

Abstract

The utility model discloses a watchdog function realization circuit, which realizes that whether a main chip is in a normal working state or not is periodically judged, and a system reset signal is output when the main chip is judged to be in an abnormal working state. Whether the circuit periodically judges whether the main chip is in the normal working state or not can be rapidly and manually changed, the action of outputting the system reset signal when the main chip is in the abnormal working state is stopped, and the phenomenon that the watchdog function is repeatedly triggered when software and hardware of a microprocessor are debugged is avoided. Whether the watchdog function is performed or not can be rapidly and manually changed, so that a user is allowed to rapidly change the working mode of the circuit according to an actual use scene, the time consumed by debugging and testing is greatly shortened, the use cost caused by the use of tools and components is reduced, and the applicability of equipment is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of watchdog circuit, concretely is a watchdog function implementation circuit. BACKGROUND

[0002] With the development of modern electronic technology, electronic devices with various microprocessors have been widely used in various industries of national production. But with the increasingly powerful function of electronic devices, the increasingly complex program structure, and the increasingly long instruction code, combined with the interference of the field working environment, the device out of control, and the unstable probability of each function module also increases exponentially. To this end, the common solution is to use hardware or software to implement a timer to monitor program running to prevent the system from becoming unstable due to software failure or abnormality.

[0003] The watchdog circuit is a protection mechanism for preventing microprocessors from falling into a dead loop due to program errors. It monitors the program running through a timer, and if the program does not reset the timer (i.e. "feed the dog") within the set time, the watchdog will trigger a system reset. The existing hardware watchdog uses a special hardware chip to control the microprocessor, while the software watchdog uses the internal timer / counter of the microcontroller to control the microprocessor through software.

[0004] However, the existing technology will repeatedly trigger the watchdog function during microprocessor software and hardware debugging, resulting in system failure and increasing the difficulty of debugging. UTILITY MODEL CONTENTS

[0005] Therefore, it is necessary to provide a watchdog function implementation circuit. The present application provides a watchdog function implementation circuit, which periodically judges whether the main chip is in a normal working state, and outputs a system reset signal when the main chip is in an abnormal working state. At the same time, the circuit can quickly manually change whether the circuit periodically judges whether the main chip is in a normal working state, and stops outputting the system reset signal when the main chip is in an abnormal working state.

[0006] A watchdog function implementation circuit, comprising a main chip signal output module, a logic circuit module, a watchdog monitoring module, a main chip control signal input module, a direct current power supply module and a common ground module; the signal output end of the main chip signal output module is connected with the signal input end of the logic circuit module, the signal output end of the logic circuit module is connected with the signal input end of the watchdog monitoring module, the signal output end of the watchdog monitoring module is connected with the signal input end of the main chip control signal input module, the direct current power supply module is electrically connected with the logic circuit module and the watchdog monitoring module respectively, and the common ground module is electrically connected with the logic circuit module and the watchdog monitoring module respectively;

[0007] The logic circuit module comprises a manual selection unit and a driving unit, and a signal output end of the manual selection unit is connected with a signal input end of the driving unit.

[0008] In one of the embodiments, the watchdog monitoring module comprises a microprocessor monitoring unit, a manual reset pull-up unit and a manual reset pull-down unit, one end of the manual reset pull-up unit is electrically connected with the DC power module, and the other end is electrically connected with the microprocessor monitoring unit; one end of the manual reset pull-down unit is electrically connected with the microprocessor monitoring unit, and the other end is electrically connected with the common ground module, and a signal output end of the driving unit is connected with a signal input end of the microprocessor monitoring unit.

[0009] In one of the embodiments, the manual selection unit comprises a first resistor and a first switch, one end of the first resistor is connected with the DC power module, and the other end is connected with one end of the first switch, and the other end of the first switch is connected with the driving unit.

[0010] In one of the embodiments, the microprocessor monitoring unit comprises a microprocessor monitoring subunit and a seventh resistor, and the seventh resistor is connected with the microprocessor monitoring subunit.

[0011] In one of the embodiments, the manual reset pull-up unit comprises a sixth resistor, one end of the sixth resistor is connected with the DC power module, and the other end is connected with the microprocessor monitoring subunit.

[0012] In one of the embodiments, the manual reset pull-down unit comprises a fifth resistor, a second switch, an electrostatic protection diode and a first capacitor, one end of the fifth resistor is connected with the microprocessor monitoring subunit, and the other end is connected with the second switch, the other end of the second switch is connected with the common ground module, the electrostatic protection diode is connected between the fifth resistor and the common ground module, and the electrostatic protection diode and the first capacitor are connected in parallel with the fifth resistor in sequence.

[0013] In one of the embodiments, the main chip control signal input module comprises an eighth resistor, one end of the eighth resistor is connected with the microprocessor monitoring subunit, and the other end is connected with a system reset signal pin.

[0014] In one of the embodiments, the microprocessor monitoring subunit is an integrated microprocessor monitoring device.

[0015] In one of the embodiments, the main chip signal output module comprises a second resistor, a third resistor and a fourth resistor, one end of the second resistor is connected with a main chip watchdog enable pin, the other end is connected with the driving unit, one end of the third resistor is connected with a main chip watchdog period signal pin, the other end is connected with the driving unit, one end of the fourth resistor is connected with the driving unit, the other end is connected with the common ground module.

[0016] In one of the embodiments, the driving unit is a single-channel non-inverting buffer / bus driver.

[0017] The above-mentioned watchdog function implementation circuit has the beneficial effects that: through the cooperation of the main chip signal output module, the logic circuit module, the watchdog monitoring module, the main chip control signal input module, the direct current power supply module and the common ground module, the implementation circuit realizes the periodic judgment of whether the main chip is in a normal working state, and when the main chip is in an abnormal working state, outputs a system reset signal, at the same time, can quickly manually change whether the circuit performs the periodic judgment of whether the main chip is in a normal working state, and stops the action of outputting the system reset signal when the main chip is in an abnormal working state, avoiding the repeated triggering of the watchdog function during the debugging of the microprocessor software and hardware. Since the watchdog function can be quickly manually changed, the user can quickly change the circuit working mode according to the actual use scene, greatly reducing the time consumed by debugging and testing, reducing the use cost caused by the use of tools and components, and improving the applicability of the equipment. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a structural schematic diagram of the watchdog function implementation circuit of the present application;

[0019] Figure 2 FIG. 2 is a circuit schematic diagram of the watchdog function implementation circuit of the present application; Figure 1 FIG. 3 is a circuit principle diagram of the watchdog function implementation circuit of the present application. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings. In the following description, many specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0021] It is to be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" to another element, there are no intervening elements present.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As shown in Figure 1 and Figure 2 A watchdog function implementation circuit, comprising a main chip signal output module 100, a logic circuit module 200, a watchdog monitoring module 300, a main chip control signal input module 400, a direct current power supply module 500 and a common ground module 600; the signal output end of the main chip signal output module 100 is connected with the signal input end of the logic circuit module 200, the signal output end of the logic circuit module 200 is connected with the signal input end of the watchdog monitoring module 300, the signal output end of the watchdog monitoring module 300 is connected with the signal input end of the main chip control signal input module 400, the direct current power supply module 500 is respectively electrically connected with the logic circuit module 200 and the watchdog monitoring module 300, and the common ground module 600 is respectively electrically connected with the logic circuit module 200 and the watchdog monitoring module 300.

[0024] The logic circuit module 200 comprises a manual selection unit 210 and a driving unit 220, and the signal output end of the manual selection unit 210 is connected with the signal input end of the driving unit 220.

[0025] The driving unit 220 is a single-channel non-inverting buffer / bus driver. The chip model of the driving unit 220 is 74LVC1G125SE-7, which is a single-channel non-inverting buffer / bus driver with 3-state output. The first pin of the driving unit 220 is an output enable pin, the second pin is an input pin, the second pin is connected to the main chip watchdog period signal pin through a series connection of the third resistor R3, the third pin is a ground pin, the third pin is connected to the common ground module 600, the fourth pin is an output pin, the fifth pin is a power supply pin, and the fifth pin is connected to the DC power supply module 500. The output enable pin and the input pin of the driving unit 220 have the following properties: when the voltage of one of the pins is less than or equal to 0.8V, the logic level of the pin is low, and when the voltage of one of the pins is greater than or equal to 2V, the logic level of the pin is high. When the logic level of the output pin of the driving unit 220 is low, its voltage is less than 0.6V, and when the logic level is high, its voltage is greater than 2.2V. The logic level of the output enable pin, the logic level of the input pin, and the logic level of the output pin of the driving unit 220 have the following three logic relationships: when the logic level of the output enable pin is low and the logic level of the input pin is high, the logic level of the output pin is high; when the logic level of the output enable pin is low and the logic level of the input pin is low, the logic level of the output pin is low; when the logic level of the output enable pin is high, the output pin is in a high impedance state.

[0026] The DC power supply module 500 can be a battery, a solar panel, an electronic device adapter, or any circuit and device that can provide DC power. The DC power supply module 500 provides voltage to the driving unit 220 and the integrated microprocessor monitoring device 301. More specifically, the DC power supply 500 provides a 3.3V voltage.

[0027] More specifically, the common ground module 600 provides voltage to the connected circuit. More specifically, the common ground module 600 provides a 0V voltage.

[0028] In one embodiment, the watchdog monitoring module 300 includes a microprocessor monitoring unit 310, a manual reset pull-up unit 320, and a manual reset pull-down unit 330. One end of the manual reset pull-up unit 320 is electrically connected to the DC power supply module 500, and the other end is electrically connected to the microprocessor monitoring unit 310. One end of the manual reset pull-down unit 330 is electrically connected to the microprocessor monitoring unit 310, and the other end is electrically connected to the common ground module 600. The signal output end of the driving unit 220 is connected to the signal input end of the microprocessor monitoring unit 310.

[0029] In one of the embodiments, the manual selection unit 210 comprises a first resistor R1 and a first switch KEY1, one end of the first resistor R1 is connected with the direct current power module 500, the other end is connected with one end of the first switch KEY1, the other end of the first switch KEY1 is connected with the driving unit 220. The other end of the first switch KEY1 is connected with the first pin of the driving unit 220. The first switch KEY1 can be a single-pole double-throw toggle switch, or a single-pole double-throw slide switch.

[0030] In one of the embodiments, the microprocessor monitoring unit 310 comprises a microprocessor monitoring subunit 311 and a seventh resistor R7, the seventh resistor R7 is connected with the microprocessor monitoring subunit 311.

[0031] The second pin and the third pin of the microprocessor monitoring subunit 311 are respectively connected with the two ends of the seventh resistor R7. The microprocessor monitoring subunit 311 is an integrated microprocessor monitoring device. The chip model of the microprocessor monitoring subunit 311 is SGM706B-SXMS8G / TR. The first pin of the microprocessor monitoring subunit 311 is a reset pin, the first pin is connected with the system reset signal pin through the eighth resistor R8 in series, the second pin is a watchdog output pin, the voltage of the second pin is VWDO, the third pin is a manual reset input pin, the second pin is connected with the third pin through the seventh resistor R7, the fourth pin is a power supply pin, the fourth pin is connected with the DC power supply module 500, the fifth pin is a ground pin, the fifth pin is connected with the common ground module 600, the sixth pin is a power-off monitoring input pin, the sixth pin is connected with the common ground module 600, the seventh pin is a power-off monitoring output pin, the seventh pin is suspended and not connected with any circuit, the eighth pin is a watchdog input pin, and the eighth pin is connected with the fourth pin of the driving unit 220. When the voltage of the third pin of the microprocessor monitoring subunit 311 is greater than or equal to 2V, the logic level of the third pin of the microprocessor monitoring subunit 311 is high, and when the voltage of the third pin of the microprocessor monitoring subunit 311 is less than or equal to 0.8V, the logic level of the third pin of the microprocessor monitoring subunit 311 is low. When the voltage of the eighth pin of the microprocessor monitoring subunit 311 is greater than or equal to 0.7 times the voltage of the fourth pin of the microprocessor monitoring subunit 311, the logic level of the eighth pin is high, and when the voltage of the eighth pin is less than or equal to 0.8V, the logic level of the eighth pin is low. When the logic level of the second pin of the microprocessor monitoring subunit 311 is high, the voltage of the second pin is greater than or equal to 0.7 times the voltage of the fourth pin of the microprocessor monitoring subunit 311, and when the logic level of the second pin is low, the voltage of the second pin is less than or equal to 0.2V. When the logic level of the first pin of the microprocessor monitoring subunit 311 is high, the voltage of the first pin is greater than or equal to 0.7 times the voltage of the fourth pin of the microprocessor monitoring subunit 311, and when the logic level of the first pin is low, the voltage of the first pin is less than or equal to 0.4V.

[0032] In one embodiment, the manual reset pull-up unit 320 includes a sixth resistor R6, one end of the sixth resistor R6 is connected with the DC power supply module 500, and the other end is connected with the microprocessor monitoring subunit 311. One end of the sixth resistor R6 is connected with the DC power supply module 500, and the other end is connected with the microprocessor monitoring subunit 311.

[0033] In one of the embodiments, the manual reset pull-down unit 330 includes a fifth resistor R5, a second switch KEY2, an electrostatic protection diode ESD1 and a first capacitor C1. One end of the fifth resistor R5 is connected to the microprocessor monitoring sub-unit 311, and the other end is connected to the second switch KEY2. The other end of the second switch KEY2 is connected to the common ground module 600. The electrostatic protection diode ESD1 is connected between the fifth resistor R5 and the common ground module 600. The electrostatic protection diode ESD1 and the first capacitor C1 are connected in parallel to the fifth resistor R5 in sequence.

[0034] One end of the fifth resistor R5 is connected to the third pin of the microprocessor monitoring sub-unit 311. The electrostatic protection diode ESD1 and the first capacitor C1 can keep the voltage of the third pin of the microprocessor monitoring sub-unit 311 relatively stable when a large current occurs in the second switch KEY2 due to external reasons.

[0035] More specifically, the second switch KEY2 is a key switch. When the second switch KEY2 is in the off state, the current of the third pin of the microprocessor monitoring sub-unit 311 will not flow to the common ground module 600 through the manual reset pull-down unit 330. The voltage of the third pin of the microprocessor monitoring sub-unit 311 is: VMR = VWDO + (VCC - VWDO) * R7 / (R6 + R7). When the second switch KEY2 is in the on state, the voltage of the third pin of the integrated microprocessor monitoring device 301 is: VMR = 0.

[0036] More specifically, if the eighth pin of the microprocessor monitoring sub-unit 311 remains at a high level or a low level for more than the watchdog timeout period, the internal watchdog timer will expire, and the second pin of the microprocessor monitoring sub-unit 311 will change from a high logic level to a low logic level, with a typical value of 1.6 seconds. When a logic level change occurs from high to low or from low to high at the eighth pin of the microprocessor monitoring sub-unit 311, the timer will also be cleared. When the eighth pin of the microprocessor monitoring sub-unit 311 is left floating or connected to a high impedance output, the watchdog function will be disabled.

[0037] More specifically, when the second switch KEY2 is in the off state and the second pin of the microprocessor monitoring subunit 311 is in the high logic level, the logic level of the third pin of the microprocessor monitoring subunit 311 is high, and the logic level of the first pin of the microprocessor monitoring subunit 311 is high. When the second switch KEY2 is in the off state and the second pin of the microprocessor monitoring subunit 311 is in the low logic level, the logic level of the third pin of the microprocessor monitoring subunit 311 is low, and the logic level of the first pin of the microprocessor monitoring subunit 311 is low. When the second switch KEY2 is in the on state, the logic level of the third pin of the microprocessor monitoring subunit 311 is low, and the logic level of the first pin of the microprocessor monitoring subunit 311 is low.

[0038] In one embodiment, the main chip control signal input module 400 includes an eighth resistor R8, one end of which is connected to the microprocessor monitoring subunit 311, and the other end is connected to the system reset signal pin. One end of the eighth resistor R8 is connected to the first pin of the microprocessor monitoring subunit 311. When the system reset signal pin is in the low logic level for more than a certain period of time, the main chip system reset occurs, and the period of time is the time period required for the main chip to receive the low logic level of the system reset signal.

[0039] In one embodiment, the main chip signal output module 100 includes a second resistor R2, a third resistor R3, and a fourth resistor R4, one end of the second resistor R2 is connected to the main chip watchdog enable pin, the other end is connected to the driving unit 220, one end of the third resistor R3 is connected to the main chip watchdog period signal pin, the other end is connected to the driving unit 220, one end of the fourth resistor R4 is connected to the driving unit 220, and the other end is connected to the common module 600.

[0040] The main chip watchdog enable pin is connected to the first pin of the driving unit 220, and the main chip watchdog period signal pin is connected to the second pin of the driving unit 220. The main chip watchdog enable pin and the main chip watchdog period signal pin 1 are signals controlled by the main chip.

[0041] When the first switch KEY1 is off and the voltage of the chip watchdog enable pin is VEN, the voltage of the output enable pin of the driving unit 220 is VOE = VEN * R4 / (R2 + R4). When the first switch KEY1 is on, the voltage of the output enable pin of the driving unit 220 is VOE = VCC * R4 / (R1 + R4). According to the voltage VCC of the DC power module 500 and the voltage VEN of the main chip watchdog enable pin in the actual application of the watchdog function implementation circuit, the resistance values of the first resistor R1, the second resistor R2 and the fourth resistor R4 in the actual application of the watchdog function implementation circuit are calculated.

[0042] The working principle of the present application is as follows: (1) When the main chip works normally: the first switch KEY1 is off, the WATCHDOG-EN signal is low, and the WATCHDOG-SIG signal is a periodic pulse signal. The first pin of the driving unit 220 is low, and the logic relationship of the driving unit 220 makes the fourth pin equal to the second pin, which is a periodic pulse, and is then given to the eighth pin of the microprocessor monitoring subunit 311. The periodic pulse of the eighth pin of the microprocessor monitoring subunit 311 keeps the second pin of the microprocessor monitoring subunit 311 high, the third pin of the microprocessor monitoring subunit 311 high, and the first pin of the microprocessor monitoring subunit 311 high, so that the main chip works normally.

[0043] (2) When the main chip does not work normally: the eighth pin of the microprocessor monitoring subunit 311 counts down for 1.6 seconds after a level change, and if there is no level change within 1.6 seconds, it means that the main chip does not work normally, and the second pin of the microprocessor monitoring subunit 311 is pulled low (i.e. the second pin low means that the main chip does not work normally), and the third pin of the microprocessor monitoring subunit 311 is pulled low, so that the first pin of the microprocessor monitoring subunit 311 outputs a low signal, and a system reset signal (SOC-RESET low) is generated.

[0044] (3) When the watchdog function implementation circuit does not work (such as in the debugging stage): the first switch KEY1 is on, the first pin of the driving unit 220 is high, the fourth pin of the driving unit 220 is in a high resistance state, and the eighth pin of the microprocessor monitoring subunit 311 is in a high resistance state, so that the microprocessor monitoring subunit 311 does not work, i.e. it does not periodically judge whether the main chip is in a normal working state, and does not output a system reset signal when the main chip is in an abnormal working state, and does not pull the first pin low.

[0045] (4) When it is desired to manually restart the watchdog function implementation circuit: the first switch KEY1 is disconnected, the WATCHDOG-EN signal is at low level, and the WATCHDOG-SIG signal is a periodic pulse signal. The first pin of the driving unit 220 is at low level, and the logic relationship of the driving unit 220 makes the fourth pin equal to the second pin to be a periodic pulse, and then given to the eighth pin of the microprocessor monitoring subunit 311. Pressing the second switch KEY2 makes it connected, the third pin of the microprocessor monitoring subunit 311 is pulled low, the first pin of the microprocessor monitoring subunit 311 outputs a low level signal, and the system is reset.

[0046] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above-described embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as within the scope of the present disclosure.

[0047] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be pointed out that, for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A watchdog function implementation circuit, characterized by: The application relates to a main chip signal output module, a logic circuit module, a watchdog monitoring module, a main chip control signal input module, a direct current power supply module and a common ground module; a signal output end of the main chip signal output module is connected with a signal input end of the logic circuit module; a signal output end of the logic circuit module is connected with a signal input end of the watchdog monitoring module; a signal output end of the watchdog monitoring module is connected with a signal input end of the main chip control signal input module; the direct current power supply module is electrically connected with the logic circuit module and the watchdog monitoring module respectively; and the common ground module is electrically connected with the logic circuit module and the watchdog monitoring module respectively. The logic circuit module comprises a manual selection unit and a driving unit; a signal output end of the manual selection unit is connected with a signal input end of the driving unit.

2. The watchdog function implementation circuit according to claim 1, characterized in that: The watchdog monitoring module comprises a microprocessor monitoring unit, a manual reset pull-up unit and a manual reset pull-down unit; one end of the manual reset pull-up unit is electrically connected with the direct current power supply module, and the other end is electrically connected with the microprocessor monitoring unit; one end of the manual reset pull-down unit is electrically connected with the microprocessor monitoring unit, and the other end is electrically connected with the common ground module; and a signal output end of the driving unit is connected with a signal input end of the microprocessor monitoring unit.

3. The watchdog function implementation circuit of claim 1, wherein: The manual selection unit comprises a first resistor and a first switch; one end of the first resistor is connected with the direct current power supply module, and the other end is connected with one end of the first switch; and the other end of the first switch is connected with the driving unit.

4. The watchdog function implementation circuit of claim 2, wherein: The microprocessor monitoring unit comprises a microprocessor monitoring subunit and a seventh resistor; and the seventh resistor is connected with the microprocessor monitoring subunit.

5. The watchdog function implementation circuit according to claim 4, characterized in that: The manual reset pull-up unit comprises a sixth resistor; one end of the sixth resistor is connected with the direct current power supply module, and the other end is connected with the microprocessor monitoring subunit.

6. The watchdog function implementation circuit of claim 4, wherein: The manual reset pull-down unit comprises a fifth resistor, a second switch, an electrostatic protection diode and a first capacitor; one end of the fifth resistor is connected with the microprocessor monitoring subunit, and the other end is connected with the second switch; the other end of the second switch is connected with the common ground module; the electrostatic protection diode is connected between the fifth resistor and the common ground module; and the electrostatic protection diode and the first capacitor are connected in parallel with the fifth resistor in sequence.

7. The watchdog function implementation circuit of claim 4, wherein: The main chip control signal input module comprises an eighth resistor; one end of the eighth resistor is connected with the microprocessor monitoring subunit, and the other end is connected with a system reset signal pin.

8. The watchdog function implementation circuit according to claim 7, characterized in that: The microprocessor monitoring subunit is an integrated microprocessor monitoring device.

9. The watchdog function implementation circuit of claim 1, wherein: The main chip signal output module comprises a second resistor, a third resistor and a fourth resistor; one end of the second resistor is connected with a main chip watchdog enable pin, and the other end is connected with the driving unit; one end of the third resistor is connected with a main chip watchdog period signal pin, and the other end is connected with the driving unit; one end of the fourth resistor is connected with the driving unit, and the other end is connected with the common ground module.

10. The watchdog function implementation circuit of claim 1, wherein: The driving unit is a single-channel non-inverting buffer / bus driver. The driving unit is a single-channel non-inverting buffer / bus driver.

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