Fan-out wafer level packaging unit
By employing a technique of filling the grooves with metal paste before grinding in the fan-out wafer-level packaging unit, combined with the design of conductive pillars and dielectric layers, the high cost and environmental protection issues of conductive lines are solved, achieving a thin, light, and compact packaging effect and double-sided electrical connection, thus improving reliability and efficiency.
Patent Information
- Application Number
- CN202422275837.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-18
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-09-18
AI Technical Summary
In existing fan-out wafer-level packaging technologies, the fabrication cost of the redistribution layer's conductive lines is high and not environmentally friendly. At the same time, it is difficult to achieve double-sided electrical connection of the bare die without increasing the overall thickness.
The technology involves filling the grooves with metal paste and then grinding to form the conductive lines. Multiple conductive lines are formed on the carrier and the bare die, and double-sided electrical connection is achieved by using conductive pillars. Combined with the design of the dielectric layer and the outer sheath, the process is simplified and the cost is reduced.
It achieves a thin and compact conductive circuit, reduces manufacturing costs, simplifies the manufacturing process, improves reliability and efficiency, and meets the design requirements of thin and compact electronic products.
Smart Images
Figure CN223693116U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a packaging unit, in particular to a fan-out wafer level packaging unit. BACKGROUND
[0002] Light, thin, short and small packaging technology with high efficiency and high reliability is the development trend of semiconductor industry, and the fan-out wafer level packaging (FOWLP) is an existing packaging technology.
[0003] In the advanced FOWLP, the redistribution layer (RDL) is the most critical, because the various interconnection lines in the RDL can make the multiple pads on the bare die have XY plane electrical extension and interconnection effect to form multiple pads around the bare die, which can effectively improve the design space and reliability of the interconnection lines, but how to make the various interconnection lines in the RDL have XY plane electrical extension and interconnection effect while also maintaining or achieving a certain degree of light, thin, short and small effect is the most critical for the manufacturing of various interconnection lines in the RDL.
[0004] However, the forming method of various interconnection lines in the RDL technology applied in the existing FOWLP packaging technology is made by using plating forming technology or electroplating forming technology, so that in addition to relatively high material and manufacturing costs, the process in the existing technology also does not meet or is not conducive to environmental protection requirements.
[0005] In addition, in order to meet the light, thin, short and small design requirements of the overall electronic product, how to allow the bare die in the fan-out wafer level packaging unit to be electrically connected to the outside from the opposite double sides of the packaging unit without increasing the overall thickness is also a problem to be solved. UTILITY MODEL CONTENTS
[0006] The main purpose of the utility model is to provide a fan-out wafer level packaging unit, which comprises a carrier plate, at least one bare die, a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first interconnection lines, a first outer protective layer, a third dielectric layer, a plurality of second interconnection lines and a second outer protective layer; wherein the bare die can be electrically connected to the outside from at least one first pad around the chip area on the second surface of the bare die; wherein the bare die can also be electrically connected to the outside from a second pad in at least one opening of the second outer protective layer; wherein each first interconnection line and each second interconnection line is made by first filling metal paste into a groove and then grinding the interconnection line, effectively solving the problem of high manufacturing cost and environmental protection in the existing fan-out packaging technology in the module when manufacturing various interconnection lines.
[0007] To achieve the above object, the utility model provides a fan-out wafer level package unit, the fan-out wafer level package unit includes a carrier plate, at least one bare crystal (Die), a first dielectric layer, at least one conductive column, a second dielectric layer, a plurality of first lead lines, a first outer protective layer, a third dielectric layer, a plurality of second lead lines and a second outer protective layer, wherein the carrier plate has a first surface and an opposite second surface, wherein the carrier plate has at least one first through hole penetrating through the first surface and the second surface, wherein each bare crystal is divided from a wafer, each bare crystal has a first surface and an opposite second surface, the first surface of each bare crystal is fixed on the second surface of the carrier plate, the second surface of each bare crystal has a plurality of crystal pads, and the vertical chip area of the second surface is defined as a chip area, wherein the first dielectric layer is arranged on the second surface of the carrier plate and covers each bare crystal, the first dielectric layer has at least one first groove and at least one second through hole extending horizontally, wherein each second through hole is in communication with each first through hole, wherein each conductive column is formed in each first through hole and each second through hole and exposed outside each first through hole and each second through hole, wherein the second dielectric layer is arranged on the first dielectric layer, the second dielectric layer has a plurality of second grooves extending horizontally, wherein each first groove is exposed outside a plurality of second grooves, and each conductive column is exposed outside a plurality of second grooves, wherein each first lead line is composed of metal paste filled in a plurality of first grooves and a plurality of second grooves, each first lead line is electrically connected with a plurality of crystal pads of each bare crystal and each conductive column respectively, wherein the first outer protective layer is arranged on the second dielectric layer and a plurality of first lead lines, the first outer protective layer has a plurality of first openings, and at least one first opening is located around the chip area on the second surface of the bare crystal, wherein each first lead line is exposed outside a plurality of first openings to form a first solder pad in each first opening, wherein the third dielectric layer is arranged on the first surface of the carrier plate, the third dielectric layer has a plurality of third grooves extending horizontally, and each third groove is in communication with each first through hole, wherein each second lead line is composed of metal paste filled in a plurality of third grooves, and each second lead line is electrically connected with each conductive column, wherein the second outer protective layer is arranged on the third dielectric layer, the second outer protective layer has a plurality of second openings, wherein each second lead line is exposed outside a plurality of second openings to form a second solder pad in each second opening, wherein the bare crystal can be electrically connected outside in sequence through each crystal pad, each first lead line and each first solder pad around the chip area on the second surface of the bare crystal, thereby forming the fan-out wafer level package unit.Wherein the die is more capable of sequentially externally electrically connected via each of the stud bump, each of the first via, each of the conductive pillar, each of the second via and each of the second solder pad.
[0008] In a preferred embodiment of the present application, the carrier plate is a silicon (Si) carrier plate, a glass carrier plate or a ceramic carrier plate.
[0009] In a preferred embodiment of the present application, the metal paste forming each of the first vias is silver paste, nano-silver paste, copper paste or nano-copper paste.
[0010] In a preferred embodiment of the present application, the metal paste forming each of the second vias is silver paste, nano-silver paste, copper paste or nano-copper paste.
[0011] In a preferred embodiment of the present application, the first surface of each of the dies is further disposed on the carrier plate by a die attach film (DAF).
[0012] In a preferred embodiment of the present application, each of the first openings is further provided with a solder ball, and each of the solder balls is electrically connected to each of the first solder pads in each of the first openings.
[0013] In a preferred embodiment of the present application, the fan-out wafer level package unit is electrically connected to a printed circuit board (PCB) by each of the solder balls.
[0014] In a preferred embodiment of the present application, each of the second openings is further provided with a solder ball, and each of the solder balls is electrically connected to each of the second solder pads in each of the second openings.
[0015] In a preferred embodiment of the present application, the fan-out wafer level package unit further comprises a plurality of electronic components, and each of the electronic components is electrically connected to the fan-out wafer level package unit by each of the solder balls. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a side view of a plane schematic diagram of an application embodiment of the fan-out wafer level package unit of the present application.
[0017] Figure 2 is a side view of a plane schematic diagram of a carrier plate and a die of the present application.
[0018] Figure 3 is a side view of a plane schematic diagram of a carrier plate in Figure 2 is provided with a first dielectric layer.
[0019] Figure 4 is a plan view of a side sectional view of forming a first via in a carrier board and forming a second via on a first dielectric layer in Figure 3 .
[0020] Figure 5 is a plan view of a side sectional view of disposing a conductive pillar in the first via and the second via in Figure 4 .
[0021] Figure 6 is a plan view of a side sectional view of forming a first recess on the first dielectric layer in Figure 5 .
[0022] Figure 7 is a plan view of a side sectional view of disposing a second dielectric layer on the first dielectric layer in Figure 6 .
[0023] Figure 8 is a plan view of a side sectional view of filling a metal paste in the first recess and the second recess in Figure 7 .
[0024] Figure 9 is a plan view of a side sectional view of grinding and forming the metal paste in Figure 8 as a first conductive trace.
[0025] Figure 10 is a plan view of a side sectional view of disposing a first outer protective layer on the first conductive trace in Figure 9 .
[0026] Figure 11 is a plan view of a side sectional view of disposing a third dielectric layer on the carrier board in Figure 10 .
[0027] Figure 12 is a plan view of a side sectional view of filling a metal paste in a third recess in Figure 11 .
[0028] Figure 13 is a plan view of a side sectional view of grinding and forming the metal paste in Figure 12 as a second conductive trace.
[0029] Figure 14 is a plan view of a side sectional view of disposing a second outer protective layer on the second conductive trace in Figure 13 .
[0030] Figure 15 is a plan view of a side sectional view of disposing a tin ball on the first opening and the second opening in Figure 14 .
[0031] Figure 16 is a plan view of a side sectional view ofFigure 15 FIG. 1 is a schematic diagram of a side view of a fan-out wafer level package unit according to an embodiment of the present application.
[0032] BRIEF DESCRIPTION OF DRAWINGS 1 - fan-out wafer level package unit; 1a - chip region; 10 - carrier plate; 11 - first surface; 12 - second surface; 13 - first through hole; 20 - die; 21 - first surface; 22 - second surface; 23 - bump; 30 - first dielectric layer; 31 - first recess; 32 - second through hole; 40 - conductive pillar; 50 - second dielectric layer; 51 - second recess; 60 - first routing line; 60a - metal paste; 61 - first solder pad; 70 - first outer protective layer; 71 - first opening; 80 - third dielectric layer; 81 - third recess; 90 - second routing line; 91 - second solder pad; 100 - second outer protective layer; 101 - second opening; 110 - die attach film; 120 - solder ball; 2 - printed circuit board; 3 - electronic component. DETAILED DESCRIPTION
[0033] For the purpose of illustration, the structure and technical features of the present application are described in detail as follows, in which each drawing is only used to illustrate the structural relationship and related functions of the present application, and thus the size of each element in each drawing is not drawn according to the actual proportion and is not used to limit the present application.
[0034] REFERENCE Figure 1 The present application provides a fan-out wafer level package unit 1, which comprises a carrier plate 10, at least one die 20, a first dielectric layer 30, at least one conductive pillar 40, a second dielectric layer 50, a plurality of first routing lines 60, a first outer protective layer 70, a third dielectric layer 80, a plurality of second routing lines 90, and a second outer protective layer 100.
[0035] The carrier plate 10 has a first surface 11 and an opposite second surface 12, as shown in FIG. 1; wherein the carrier plate 10 has at least one first through hole 13 penetrating through the first surface 11 and the second surface 12, as shown in FIG. 2; wherein the carrier plate 10 comprises a silicon (Si) carrier plate, a glass carrier plate, or a ceramic carrier plate, but is not limited thereto, so as to facilitate diversified product manufacturing. Figure 2 Figure 4
[0036] Each die 20 is divided from a wafer, and each die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is fixed on the second surface 12 of the carrier plate 10, and the second surface 22 of each die 20 has a plurality of bumps 23, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as shown in FIG. 3. Figure 2
[0037] The first dielectric layer 30 is disposed on the second surface 12 of the carrier 10 and covers the dies 20. The first dielectric layer 30 has at least one first recess 31 (as shown in FIG. 1) and at least one second through hole 32 (as shown in FIG. 1). Each second through hole 32 is in communication with a corresponding first through hole 13 (as shown in FIG. 1). Each first through hole 13 and each second through hole 32 are formed by a through silicon via (TSV) technique, but not limited thereto, to simplify the manufacturing process and reduce the thickness of the package. The TSV technique is a common technique and will not be described herein. Figure 6 Figure 4 Figure 4
[0038] Each conductive pillar 40 is formed in each first through hole 13 and each second through hole 32 and exposed outside by each first through hole 13 and each second through hole 32 (as shown in FIG. 1). Figure 5 Figure 6
[0039] The second dielectric layer 50 is disposed on the first dielectric layer 30. The second dielectric layer 50 has a plurality of second recesses 51 (as shown in FIG. 1). Each first recess 31 is exposed outside by each second recess 51 (as shown in FIG. 1). Each conductive pillar 40 is exposed outside by each second recess 51 (as shown in FIG. 1). Figure 7 Figure 7 Figure 7
[0040] Each first conductive line 60 is formed by a metal paste 60a filled in each first recess 31 and each second recess 51. Each first conductive line 60 is electrically connected to each die pad 23 of each die 20 and each conductive pillar 40 (as shown in FIG. 1). Figure 9
[0041] The first outer layer 70 is disposed on the second dielectric layer 50 and each first conductive line 60. The first outer layer 70 has a plurality of first openings 71. At least one first opening 71 is located around the chip area 1a on the second surface 22 of each die 20 (as shown in FIG. 1). Each first conductive line 60 is exposed outside by each first opening 71 to form a first solder pad 61 in each first opening 71 (as shown in FIG. 1). Figure 10 Figure 10
[0042] The third dielectric layer 80 is disposed on the first surface 11 of the carrier 10. The third dielectric layer 80 has a plurality of third recesses 81 (as shown in FIG. 1). Each third recess 81 is in communication with a corresponding first through hole 13 (as shown in FIG. 1). Figure 11
[0043] Each second conductive line 90 is formed by filling the third groove 81 with metal paste 90a. Each second conductive line 90 is electrically connected to each conductive post 40, such as... Figure 13 As shown.
[0044] The second outer sheath 100 is disposed on the third dielectric layer 80, and the second outer sheath 100 has a plurality of second openings 101, such as Figure 14 As shown; each second conductive line 90 is exposed to the outside by each second opening 101, and a second solder pad 91 is formed within each second opening 101, as shown. Figure 14 As shown.
[0045] The bare die 20 can be electrically connected to the external circuitry via each die pad 23, each first conductive line 60, and each first solder pad 61 surrounding the chip region 1a on the second surface 22 of the bare die 20, thereby forming the fan-out wafer-level package unit 1, such as... Figure 15 As shown.
[0046] The bare die 20 can be connected to the external power supply sequentially via each die pad 23, each first conductive line 60, each conductive post 40, each second conductive line 90, and each second solder pad 91, such as... Figure 15 As shown.
[0047] The process of manufacturing this fan-out wafer-level packaging unit 1 may include the following steps, but is not limited thereto:
[0048] Step S1: Provide a carrier board 10, such as Figure 2 As shown; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12, as Figure 2 As shown.
[0049] Step S2: A plurality of bare dies 20, cleaved from at least one wafer, are spaced apart and disposed on the second surface 12 of the carrier substrate 10, such as... Figure 2 As shown; each die 20 has a first surface 21 and an opposite second surface 22. The first surface 21 of each die 20 is fixedly disposed on the second surface 12 of the carrier 10. The second surface 22 of each die 20 has a plurality of die pads 23, and the vertical chip region of the second surface 22 is defined as a chip region 1a, as shown. Figure 2 As shown.
[0050] Step S3: Using a technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple first conductive lines 60 are formed on the second surface 22 of each bare die 20: First, a first dielectric layer 30 is laid on the second surface 12 of the carrier board 10 and on each bare die 20, such as... Figure 3 As shown, then multiple first grooves 31 are formed horizontally on the first dielectric layer 30 (e.g.,Figure 6 a plurality of first through holes 13 downwardly penetrating the carrier board 10 and a plurality of second through holes 32 downwardly penetrating the first dielectric layer 30 (as shown in FIG. 2), and exposing each of the die pads 23 of each of the dies 20 outwardly by each of the first grooves 31 (as shown in FIG. 3) and making each of the first through holes 13 communicate with each of the second through holes 32 (as shown in FIG. 4), and then forming a conductive pillar 40 in each of the first through holes 13 and each of the second through holes 32, and then laying a second dielectric layer 50 on the first dielectric layer 30 (as shown in FIG. 5), and then horizontally forming a plurality of second grooves 51 on the second dielectric layer 50 (as shown in FIG. 6), and then filling a metal paste 60a into each of the first grooves 31 and each of the second grooves 51, and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50 (as shown in FIG. 7), and finally grinding the metal paste 60a higher than the surface of the second dielectric layer 50 to make the surface of the metal paste 60a flush with the surface of the second dielectric layer 50 to form a plurality of the first conductive lines 60 (as shown in FIG. 8). Figure 4 Figure 6 Figure 4 Figure 5 Figure 7 Figure 7 Figure 8 Figure 9
[0051] Step S4: laying a first outer protective layer 70 on the second dielectric layer 50 (as shown in FIG. 9). Figure 10
[0052] Step S5: forming a plurality of first openings 71 on the first outer protective layer 70 and making at least one of the first openings 71 formed around the chip area la on the second face 22 of the die 20 so that each of the first conductive lines 60 can be exposed outwardly by each of the first openings 71 to form a first solder pad 61 in each of the first openings 71 (as shown in FIG. 10). Figure 10
[0053] Step S6: forming a plurality of second conductive lines 90 on the first face 11 of the carrier board 10 by using the technique of filling a metal paste into a groove and then grinding to form a conductive line: laying a third dielectric layer 80 on the first face 11 of the carrier board 10 (as shown in FIG. 11), and then horizontally forming a plurality of third grooves 81 on the third dielectric layer 80 and exposing each of the conductive pillars 40 in each of the first through holes 13 outwardly by each of the third grooves 81 (as shown in FIG. 12), and then filling a metal paste 90a into each of the third grooves 81 and the thickness of the metal paste 90a is higher than the surface of the third dielectric layer 80 (as shown in FIG. 13). Figure 11 Figure 11 Figure 12 As shown, the metal paste 90a above the surface of the third dielectric layer 80 is finally polished to make the surface of the metal paste 90a flush with the surface of the third dielectric layer 80 to form a plurality of the second conductive lines 90. Figure 13 As shown.
[0054] Step S7: A second protective layer 100 is laid on the third dielectric layer 80. Figure 14 As shown.
[0055] Step S8: A plurality of second openings 101 are formed in the second protective layer 100, and each second conductive line 90 is exposed outside through each second opening 101 to form a second solder pad 91 in each second opening 101. Figure 14 As shown.
[0056] Step S9: A separation operation is performed to separate a plurality of fan-out wafer level packaging units 1. Figure 1 As shown.
[0057] The processes of steps S3 and S6 in the process of manufacturing the above-mentioned fan-out wafer level packaging unit 1 can be regarded as key steps of manufacturing the redistribution layer (RDL) of the fan-out wafer level packaging unit 1. In step S3, the first conductive lines 60 on the second surface 22 of each bare die 20 are formed by the technique of filling the metal paste into the groove and then polishing to form the conductive lines. In step S6, the second conductive lines 90 on the first surface 11 of the carrier plate 10 are formed by the technique of filling the metal paste into the groove and then polishing to form the conductive lines. Since steps S3 and S6 are both processes that can be easily and precisely implemented, the processes are relatively simple, and the conductive lines in the redistribution layer (RDL) can be in the state of XY plane electrical extension and interconnection, and the finished fan-out wafer level packaging unit 1 can still maintain or achieve a certain degree of lightness, thinness and smallness.
[0058] Referring to Figure 9 The metal paste 60a constituting each first conductive line 60 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity and low temperature sintering, but since the nano-silver paste material is a common material, it will not be described here.
[0059] Referring to Figure 13 The metal paste 90a constituting each second conductive line 90 includes silver paste, nano-silver paste, copper paste or nano-copper paste, but is not limited thereto.
[0060] Referring to Figure 2The first surface 21 of each die 20 is further disposed on the carrier 10 by a die attach film (DAF) 110, but not limited.
[0061] Referring to Figure 15 A tin ball 120 is further disposed on each first opening 71, but not limited, and the tin ball 120 can be electrically connected to the first pad 61 in each first opening 71.
[0062] Referring to Figure 1 The fan-out wafer level package unit 1 can be electrically connected to a printed circuit board (PCB) 2 by the tin ball 120, but not limited, to facilitate diversified applications of products.
[0063] Referring to Figure 15 A tin ball 120 is further disposed on each second opening 101, but not limited, and the tin ball 120 can be electrically connected to the second pad 91 in each second opening 101.
[0064] Referring to Figure 1 And Figure 16 The fan-out wafer level package unit 1 further has a plurality of electronic elements 3, but not limited, and each electronic element 3 can be electrically connected to the fan-out wafer level package unit 1 by the tin ball 120, to facilitate diversified applications of products.
[0065] Compared with the prior art fan-out wafer level package unit, the fan-out wafer level package unit 1 has the following advantages:
[0066] (1) The steps S3 and S6 in the process of manufacturing the fan-out wafer level package unit 1 of the present application are compared with the related art of manufacturing the prior art fan-out wafer level package unit. The fan-out wafer level package unit of the present application is manufactured by manufacturing the RDL in each lead line, so that each lead line in the RDL is in the state of XY plane electrical extension and interconnection, and also can maintain or achieve a certain degree of lightness, thinness and smallness. The steps are simplified and easy to implement precisely, which is especially beneficial to reduce the thickness of the package unit. Therefore, the manufacturing process of the present application is not only simplified and cost-saving, but also can effectively improve the use efficiency and reliability of the fan-out wafer level package unit 1.
[0067] (2) The process of manufacturing the various conductive lines of the utility model is to use the technology of filling metal paste into the groove and then grinding the conductive lines to form multiple first conductive lines 60 on the second face 22 of each bare die 20, and to use the technology of filling metal paste into the groove and then grinding the conductive lines to form multiple second conductive lines 90 on the first face 11 of the carrier plate 10, thus the utility model can effectively solve the problem of high manufacturing cost and environmental unfriendliness in the process of manufacturing various conductive lines in the existing fan-out packaging technology.
[0068] (3) The fan-out wafer level packaging unit 1 of the utility model has various conductive columns 40 arranged inside, so that each bare die 20 in the fan-out wafer level packaging unit 1 can be electrically connected to the outside through the opposite two faces of the fan-out wafer level packaging unit 1, and the bare die in the fan-out wafer level packaging unit can be electrically connected to the outside through the opposite two faces of the packaging unit without increasing the overall thickness, thus meeting the demand of light, thin, short and small design of the whole electronic product and increasing the market competitiveness of the product.
[0069] The above is only the preferred embodiment of the utility model, which is only illustrative but not restrictive for the utility model; those skilled in the art understand that many changes, modifications and even equivalent changes can be made to the utility model within the spirit and scope defined by the claims of the utility model, but all will fall within the protection scope of the utility model.
Claims
1. A fan-out wafer level package unit, characterized by, The fan-out wafer level package unit comprises: a carrier plate having a first surface and an opposite second surface, wherein the carrier plate has at least a first through hole penetrating the first surface and the second surface; at least a die, each of the die being separated from a wafer, each of the die having a first surface and an opposite second surface, the first surface of each of the die being fixed on the second surface of the carrier plate, the second surface of each of the die having a plurality of die pads, and a vertical chip region of the second surface being defined as a chip region; a first dielectric layer disposed on the second surface of the carrier plate and covering each of the die, the first dielectric layer having at least a first recess extending horizontally and at least a second through hole; wherein each of the second through hole is in communication with each of the first through hole correspondingly; at least a conductive post, each of the conductive post being formed in each of the first through hole and each of the second through hole, and exposed outside from each of the first through hole and each of the second through hole; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having a plurality of second recesses extending horizontally; wherein each of the first recess is exposed outside from the plurality of second recesses; wherein each of the conductive post is exposed outside from the plurality of second recesses; a plurality of first routing lines, each of the first routing line being composed of a metal paste filled in the plurality of first recesses and the plurality of second recesses, each of the first routing line being electrically connected with each of the die pad of each of the die and each of the conductive post respectively; a first outer protective layer disposed on the second dielectric layer and each of the first routing line, the first outer protective layer having a plurality of first openings and at least one of the first openings being located around the chip region on the second surface of the die; wherein each of the first routing line is exposed outside from the plurality of first openings to form a first solder pad in each of the first opening; a third dielectric layer disposed on the first surface of the carrier plate, the third dielectric layer having a plurality of third recesses extending horizontally, each of the third recess being in communication with each of the first through hole; a plurality of second routing lines, each of the second routing line being composed of a metal paste filled in the plurality of third recesses, each of the second routing line being electrically connected with each of the conductive post; and a second outer protective layer disposed on the third dielectric layer, the second outer protective layer having a plurality of second openings; wherein each of the second routing line is exposed outside from the plurality of second openings to form a second solder pad in each of the second opening; wherein the die can be electrically connected outside in sequence through each of the die pad, each of the first routing line and each of the first solder pad located around the chip region on the second surface of the die, so as to form the fan-out wafer level package unit; wherein the die can also be electrically connected outside in sequence through each of the die pad, each of the first routing line, each of the conductive post, each of the second routing line and each of the second solder pad.
2. The fan-out wafer level package unit of claim 1, wherein, The carrier plate comprises a silicon carrier plate, a glass carrier plate or a ceramic carrier plate.
3. The fan-out wafer level packaging unit of claim 1, wherein, The metal paste constituting each of the first routing line comprises a silver paste, a nano-silver paste, a copper paste or a nano-copper paste.
4. The fan-out wafer level packaging unit of claim 1, wherein, The metal paste of each second conductive line includes silver paste, nano-silver paste, copper paste, or nano-copper paste.
5. The fan-out wafer level packaging unit of claim 1, wherein, The first surface of each bare die is disposed on the carrier substrate by a die attach film.
6. The fan-out wafer level packaging unit of claim 1, wherein, Each first opening is provided with a solder ball, and each solder ball is electrically connected to the first pads in the first openings.
7. The fan-out wafer level package unit of claim 6, wherein, The fan-out wafer level package unit is electrically connected to a printed circuit board by the solder balls.
8. The fan-out wafer level package unit of claim 1, wherein, Each second opening is provided with a solder ball, and each solder ball is electrically connected to the second pads in the second openings.
9. The fan-out wafer level packaging unit of claim 8, wherein, The fan-out wafer level package unit further includes electronic elements, and each electronic element is electrically connected to the fan-out wafer level package unit by the solder balls.