Fan-out type wafer level packaging unit and package formed by stacking fan-out type wafer level packaging unit
By employing metal paste filling and grinding to form conductive lines in FOWLP packaging technology, combined with dielectric layers and conductive pillars, the high cost and environmental issues of conductive lines are solved, enabling a thin, light, and compact packaging unit design and multi-layer stacking, thus improving manufacturing efficiency and reliability.
Patent Information
- Application Number
- CN202422812458.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-11-18
AI Technical Summary
In existing FOWLP packaging technology, the fabrication cost of the redistribution layer's conductive lines is high and not environmentally friendly. At the same time, it is difficult to achieve package stacking and mass production while increasing performance or computing power.
The technology involves filling the grooves with metal paste and then grinding them to form the conductive lines. Combined with dielectric layers and conductive pillars, a fan-out wafer-level packaging unit is formed. Mass production is achieved by using a solder pad design with the same layout, and multiple packaging units are connected by solder balls.
It reduces the manufacturing cost of the conductive lines, simplifies the manufacturing process, improves the efficiency and reliability of the thin, light, and compact packaging unit, and supports the stacking of multiple packaging units, thereby enhancing the product's market competitiveness.
Smart Images
Figure CN223693117U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a package, in particular to a fan-out wafer level package unit and a package stacked by the same. BACKGROUND
[0002] In the FOWLP of advanced package, the redistribution layer (RDL) is the most critical, because the various conductive lines in the RDL can make the multiple pads on the bare die have the effect of XY plane electrical extension and interconnection, so that multiple pads can be formed around the bare die, which can effectively improve the design space and reliability of the various conductive lines, but how to make the various conductive lines in the RDL have the effect of XY plane electrical extension and interconnection while also maintaining or achieving a certain degree of thinness, lightness and smallness is the most critical in the manufacturing of the various conductive lines in the RDL.
[0003] However, the forming method of the various conductive lines in the RDL technology applied in the existing FOWLP packaging technology is made by using plating forming technology or electroplating forming technology, so that in addition to the relatively high material cost and manufacturing cost, the process in the existing technology also does not meet or is not conducive to the requirements of environmental protection.
[0004] In addition, when the FOWLP package unit needs to be stacked to increase performance or computing power, how to increase performance or computing power while easily stacking to form a package for mass production is also an important problem to be solved. UTILITY MODEL CONTENTS
[0005] The main purpose of the utility model is to provide a fan-out wafer level package unit and a package stacked by the same, which includes a carrier plate, at least one bare die, a first dielectric layer, at least one second conductive column, a second dielectric layer, a plurality of first conductive lines, a third dielectric layer and a plurality of metal protection layers; wherein each first conductive line can be formed by first filling metal paste into a groove and then grinding the conductive line, which is effective in solving the problem of high manufacturing cost and environmental unfriendliness in the existing fan-out package technology when manufacturing each conductive line; wherein the layout of each second pad on the first surface of the fan-out wafer level package unit is the same as that of each first pad on the second surface of the fan-out wafer level package unit, which is more conducive to mass production of products.
[0006] To achieve the above object, the utility model provides a fan-out wafer level package unit, the fan-out wafer level package unit includes a carrier plate, at least one bare crystal (Die), a first dielectric layer, at least one second conductive column, a second dielectric layer, a plurality of first lead lines, a third dielectric layer and a plurality of metal protection layers, wherein the carrier plate has a first surface and an opposite second surface, and the carrier plate has a plurality of first conductive columns penetrating the first surface and the second surface, wherein each bare crystal is divided from a wafer (Wafer), each bare crystal has a first surface and an opposite second surface, the first surface of each bare crystal is fixed on the second surface of the carrier plate, the second surface of each bare crystal has a plurality of crystal pads, and the vertical wafer area of the second surface is defined as a wafer area, wherein the first dielectric layer is arranged on the second surface of the carrier plate and covers each bare crystal, the first dielectric layer has at least one through hole, wherein each through hole is connected with each first conductive column correspondingly, wherein each second conductive column is formed in each through hole and electrically connected with each first conductive column, and each through hole is exposed outwardly, wherein the second dielectric layer is arranged on the first dielectric layer, the second dielectric layer has at least one groove extending horizontally, wherein each groove is connected with each second conductive column correspondingly, wherein each first lead line is composed of metal paste filled in each groove, wherein each first lead line is electrically connected with each second conductive column, wherein the third dielectric layer is arranged on the second dielectric layer and each first lead line, the third dielectric layer has at least one first opening, wherein each first lead line is exposed outwardly by each first opening to form a first solder pad in each first opening, wherein each metal protection layer is formed in each first opening, wherein each metal protection layer is electrically connected with each first lead line, wherein each first conductive column is exposed outwardly by the first surface of the carrier plate to form a second solder pad on the first surface of the carrier plate, wherein each bare crystal can be electrically connected outwardly in sequence through each crystal pad of the bare crystal, each first lead line, each second conductive column, each first conductive column and each second solder pad on the carrier plate, wherein each bare crystal can be electrically connected outwardly in sequence through each crystal pad of the bare crystal, each first lead line, each metal protection layer and each first solder pad around the wafer area on the second surface of the bare crystal, thereby forming the fan-out wafer level package unit.Wherein the fan-out wafer level package unit further has a first surface and a second surface, each of the second pads of the carrier board in the fan-out wafer level package unit is located on the first surface in the fan-out wafer level package unit, each of the first pads in each of the first openings in the fan-out wafer level package unit is located on the second surface in the fan-out wafer level package unit, and the layout of each of the second pads on the first surface of the fan-out wafer level package unit is the same as that of each of the first pads on the second surface of the fan-out wafer level package unit.
[0007] In a preferred embodiment of the present application, a fourth dielectric layer and a plurality of second conductive lines are further provided on the first surface of the carrier board by using a redistribution layer (RDL) technique, the fourth dielectric layer has at least one second opening formed in a horizontal direction, each of the second conductive lines is formed by a metal paste filled in each of the second openings, and each of the second conductive lines is electrically connected to each of the second pads.
[0008] In a preferred embodiment of the present application, a tin ball is further provided on each of the second conductive lines, and each of the tin balls is electrically connected to each of the first pads through each of the second conductive lines.
[0009] In a preferred embodiment of the present application, the carrier board includes a silicon (Si) carrier board, a glass carrier board or a ceramic carrier board, and the metal paste used in each of the first conductive lines includes silver paste, nano-silver paste, copper paste or nano-copper paste.
[0010] In a preferred embodiment of the present application, the thickness of the fan-out wafer level package unit is 200 um.
[0011] In a preferred embodiment of the present application, the metal paste used in each of the second conductive lines includes silver paste, nano-silver paste, copper paste or nano-copper paste.
[0012] In a preferred embodiment of the present application, the first surface of each of the dies is further provided on the carrier board by using a die attach film (DAF).
[0013] The utility model also provides a package stacked by a plurality of fan-out wafer level package units, the package includes at least two fan-out wafer level package units and at least one connecting circuit, wherein every two fan-out wafer level package units are stacked together to form a corresponding relationship between upper and lower, wherein every second pad of the fan-out wafer level package unit on the upper is formed corresponding relationship with every first pad of the fan-out wafer level package unit on the lower, wherein every connecting circuit is arranged between the fan-out wafer level package unit on the upper and the fan-out wafer level package unit on the lower, and is electrically connected with every second pad of the fan-out wafer level package unit on the upper and every first pad of the fan-out wafer level package unit on the lower, so that the fan-out wafer level package unit on the upper and the fan-out wafer level package unit on the lower can be electrically connected with each other through every connecting circuit.
[0014] In a preferred embodiment of the utility model, every bare chip in the fan-out wafer level package unit on the upper is same or different with the specification and function of every bare chip in the fan-out wafer level package unit on the lower.
[0015] In a preferred embodiment of the utility model, every connecting circuit is further tin ball. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 It is the plane schematic diagram of side view section of the utility model fan-out wafer level package unit use state.
[0017] Figure 2 It is the plane schematic diagram of side view section of the utility model carrier plate.
[0018] Figure 3 It is the schematic diagram of setting bare chip on the carrier plate in Figure 2 .
[0019] Figure 4 It is the schematic diagram of setting first dielectric layer on the bare chip in Figure 3 .
[0020] Figure 5 It is the schematic diagram of setting second conductive column on the first dielectric layer in Figure 4 .
[0021] Figure 6 It is the schematic diagram of setting second dielectric layer on the first dielectric layer in Figure 5 .
[0022] Figure 7 It is the schematic diagram of filling metal paste in the recess of second dielectric layer in Figure 6 .
[0023] Figure 8 It is the plane schematic diagram of side view section of the utility model fan-out wafer level package unit use state.Figure 7 A schematic view of grinding the metal paste higher than the surface of the second dielectric layer to form the first conductive connection line.
[0024] Figure 9 A schematic view of disposing a third dielectric layer on the second dielectric layer in Figure 8
[0025] Figure 10 A schematic view of disposing a metal protection layer in the opening of the third dielectric layer in Figure 9
[0026] Figure 11 A schematic view of disposing a fourth dielectric layer on the packaging unit of the utility model from the side.
[0027] Figure 12 A schematic view of filling the metal paste in the groove of the fourth dielectric layer in Figure 11
[0028] A schematic view of grinding the metal paste higher than the surface of the fourth dielectric layer to form the second conductive connection line. Figure 13 Figure 12 A schematic view of rotating the fan-out wafer level packaging unit in
[0029] Figure 14 Figure 13 A schematic view of rotating the fan-out wafer level packaging unit in
[0030] Figure 15 A schematic view of the packaging unit of the utility model from the side.
[0031] Figure 16 A schematic view of the packaging unit of the utility model from the side.
[0032] Mark 1 - fan-out wafer level packaging unit; 1a - wafer area; 1b - first surface; 1c - second surface; 10 - carrier plate; 11 - first surface; 12 - second surface; 13 - first conductive column; 14 - second solder pad; 20 - bare crystal; 21 - first surface; 22 - second surface; 23 - crystal pad; 30 - first dielectric layer; 31 - through hole; 40 - second conductive column; 50 - second dielectric layer; 51 - groove; 60 - first conductive connection line; 60a - metal paste; 61 - first solder pad; 70 - third dielectric layer; 71 - first opening; 80 - metal protection layer; 90 - fourth dielectric layer; 91 - second opening; 100 - second conductive connection line; 100a - metal paste; 110 - tin ball; 120 - wafer bonding film; 2 - packaging; 2a - connection line; 3 - circuit board. DETAILED DESCRIPTION
[0033] With the aid of the drawings, the structure and technical features of the present application will be described as follows, wherein the drawings are only used to illustrate the structural relationship and related functions of the present application, thus the size of each element in the drawings is not drawn according to the actual proportion and is not used to limit the present application.
[0034] Reference Figure 1 The present application provides a fan-out wafer level packaging unit 1, which comprises a carrier plate 10, at least one die 20, a first dielectric layer 30, at least one second conductive column 40, a second dielectric layer 50, a plurality of first conductive connection lines 60, a third dielectric layer 70 and a plurality of metal protective layers 80.
[0035] The carrier plate 10 has a first surface 11 and an opposite second surface 12, and the carrier plate 10 has a plurality of first conductive columns 13 penetrating the first surface 11 and the second surface 12, as shown in Figure 2 Each first conductive column 13 can be further disposed in each through hole on the carrier plate 10 after the carrier plate 10 is formed with a plurality of through holes on the carrier plate 10 by using a silicon drilling forming technique (TSV, Through Silicon Via), but this is not used to limit the present application.
[0036] Each die 20 is divided from a wafer, and each die 20 has a first surface 21 and an opposite second surface 22, and the first surface 21 of each die 20 is fixed on the second surface 12 of the carrier plate 10, and the second surface 22 of each die 20 has a plurality of die pads 23, and the vertical die area of the second surface 23 is defined as a die area 1a, as shown in Figure 3 .
[0037] The first dielectric layer 30 is disposed on the second surface 12 of the carrier plate 10 and covers each die 20, and the first dielectric layer 30 has at least one through hole 31, as shown in Figure 4 . Each through hole 31 is connected with each first conductive column 13, as shown in Figure 4 . Each through hole 31 can be formed by using a silicon drilling forming technique (TSV, Through Silicon Via), but this is not used to limit the present application.
[0038] Each second conductive column 40 is formed in each through hole 31 and is electrically connected with each first conductive column 13, and is exposed outside from each through hole 31, as shown in Figure 5 .
[0039] The second dielectric layer 50 is disposed on the first dielectric layer 30, and the second dielectric layer 50 has at least one recess 51 formed in the horizontal direction, as shown in Figure 6As shown; each groove 51 is correspondingly connected to each second conductive post 40, as... Figure 6 As shown.
[0040] Each first conductive line 60 is formed by filling the grooves 51 with metal paste 60a, such as Figure 8 As shown; each of the first conductive lines 60 is electrically connected to each of the second conductive posts 40, as... Figure 8 As shown.
[0041] The third dielectric layer 70 is disposed on the second dielectric layer 50 and each of the first conductive lines 60, and the third dielectric layer 70 has at least one first opening 71, such as Figure 9 As shown; each first conductive line 60 is exposed to the outside by each first opening 71, and a first solder pad 61 is formed in each first opening 71, such as... Figure 10 As shown; in Figure 10 In the embodiment shown, the fan-out wafer-level packaging unit 1 has four of the first bonding pads 61, but this is not a limitation.
[0042] Each metal protective layer 80 is formed within each first opening 71, such as Figure 10 As shown; each metal protective layer 80 is electrically connected to each first conductive line 60, such as... Figure 10 As shown, this is beneficial for protecting each first conductor line 60 and increasing structural strength.
[0043] Each first conductive post 13 is exposed to the outside by the first surface 11 of the carrier plate 10, and a second solder pad 14 is formed on the first surface 11 of the carrier plate 10, such as... Figure 10 As shown; in Figure 10 In the embodiment shown, the fan-out wafer-level packaging unit 1 has four second pads 14, but this is not a limitation.
[0044] Each bare die 20 can be sequentially connected to the external power supply via its respective die pad 23, each first conductive line 60, each second conductive post 40, each first conductive post 13, and each second solder pad 14 located on the carrier board 10, such as... Figure 10 As shown.
[0045] Each bare die 20 can be electrically connected to the external circuitry via its respective die pads 23, first conductive lines 60, metal protective layers 80, and first bonding pads 61 surrounding the wafer region 1a on the second surface 22 of each bare die 20, thereby forming the fan-out wafer-level package unit 1, as shown below. Figure 10 As shown.
[0046] The fan-out wafer-level packaging unit 1 further has a first surface 1b and a second surface 1c, such as Figure 10As shown in FIG. 1A; wherein each second pad 14 of the carrier 10 in the fan-out wafer level package unit 1 is located on the first surface lb in the fan-out wafer level package unit 1, as shown in FIG. 1B. Figure 10 As shown in FIG. 1A; wherein each first pad 61 in each first opening 71 in the fan-out wafer level package unit 1 is located on the second surface lc in the fan-out wafer level package unit 1, as shown in FIG. 1C. Figure 10 As shown in FIG. 1A; wherein the layout of each second pad 14 on the first surface lb of the fan-out wafer level package unit 1 is identical to the layout of each first pad 61 on the second surface lc of the fan-out wafer level package unit 1, as shown in FIG. 1D. Figure 10
[0047] The process of manufacturing the fan-out wafer level package unit 1 can include, but not limited to, the following steps:
[0048] Step S1: providing a carrier 10, as shown in FIG. 1A; wherein the carrier 10 has a first surface 11 and an opposite second surface 12, and the carrier 10 has a plurality of first conductive pillars 13 penetrating through the first surface 11 and the second surface 12, as shown in FIG. 1B. Figure 2 Figure 2 As shown in FIG. 1A; wherein each first conductive pillar 13 is externally exposed from the first surface 11 of the carrier 10, and a second pad 14 is formed on the first surface 11 of the carrier 10, as shown in FIG. 1C. Figure 10
[0049] Step S2: spacing a plurality of dies 20, which are separated from at least one wafer, on the carrier 10, as shown in FIG. 1D; wherein each die 20 has a first surface 21 and an opposite second surface 22, the first surface 21 of each die 20 is fixed on the second surface 12 of the carrier 10, the second surface 22 of each die 20 has a plurality of pads 23, and the vertical die area of the second surface 23 is defined as a die area la, as shown in FIG. 1E. Figure 3 Figure 3
[0050] Step S3: disposing a first dielectric layer 30 on the second surface 12 of the carrier 10 and on each die 20, and the first dielectric layer 30 covers each die 20, then forming a plurality of through holes 31 penetrating through the first dielectric layer 30 on the first dielectric layer 30, as shown in FIG. 1F, and then forming a second conductive pillar 40 in each through hole 31, as shown in FIG. 1G. Figure 4 Figure 5
[0051] Step S4: forming a plurality of first routing lines 60 on the second surface 22 of each die 20 by using the technique of filling metal paste into the groove and then grinding the routing lines: first, a second dielectric layer 50 is disposed on the second surface 12 of the carrier wafer 10, then a plurality of grooves 51 are formed horizontally on the second dielectric layer 50, and each second conductive pillar 40 is exposed outside from each groove 51, as shown in Figure 6 , metal paste 60a is filled into each groove 51, and the thickness of the metal paste 60a is higher than the surface of the second dielectric layer 50, as shown in Figure 7 , and finally the metal paste 60a higher than the surface of the second dielectric layer 50 is ground to make the surface of the metal paste 60a flush with the surface of the second dielectric layer 50 to form a plurality of the first routing lines 60, as shown in Figure 8 .
[0052] Step S5: a third dielectric layer 70 is disposed on the second dielectric layer 50, and a plurality of first openings 71 are formed horizontally on the third dielectric layer 70 to expose each first routing line 60 outside from each first opening 71, and finally a metal protection layer 80 is formed in each first opening 71; wherein each first routing line 60 forms a first solder pad 61 in each first opening 71, as shown in Figure 9 ; wherein each metal protection layer 80 is electrically connected to each first routing line 60; and
[0053] Step S6: performing a separation operation to separate a plurality of fan-out wafer level packaging units 1.
[0054] The process of step S4 in the process of manufacturing the fan-out wafer level packaging unit 1 can be considered as a key step of manufacturing the redistribution layer (RDL) of the fan-out wafer level packaging unit 1, which is to form a plurality of routing lines on a dielectric layer by using the technique of filling metal paste into the groove and then grinding the routing lines. Since step S4 is a process that is easy to implement precisely, the process of the fan-out wafer level packaging unit 1 is simplified, so that each first routing line 60 in the redistribution layer (RDL) can have XY plane electrical extension and interconnection, and the finished fan-out wafer level packaging unit 1 can still maintain or achieve a certain degree of lightness, thinness and smallness.
[0055] Reference Figure 13 and Figure 14A fourth dielectric layer 90 and a plurality of second conductive lines 100 are further disposed on the first surface 11 of the carrier 10 by using a redistribution layer (RDL) technique, but not limited to, to increase the structural strength of the product as the outermost protective layer; the fourth dielectric layer 90 has at least one second opening 91 formed in a horizontal direction; each second conductive line 100 is formed by a metal paste 100a filled in each second opening 91; and each second conductive line 100 is electrically connected to each second solder pad 14.
[0056] The process of manufacturing the second conductive lines 100 can further include the following steps, but not limited to:
[0057] Step S101: a fourth dielectric layer 90 is first disposed on the first surface 11 of the carrier 10, then a plurality of second openings 91 are formed in a horizontal direction on the fourth dielectric layer 90, and each second solder pad 14 is exposed externally through each second opening 91, as shown in Figure 11 .
[0058] Step S102: a metal paste 100a is filled in each second opening 91, and the thickness of the metal paste 100a is higher than the surface of the fourth dielectric layer 90, as shown in Figure 12 .
[0059] Step S103: finally, the metal paste 100a higher than the surface of the fourth dielectric layer 90 is polished, so that the surface of the metal paste 100a is flush with the surface of the fourth dielectric layer 90 to form a plurality of second conductive lines 100, as shown in Figure 13 .
[0060] Referring to Figure 1 , a tin ball 110 is further disposed on each second conductive line 100, but not limited to, and each tin ball 110 is electrically connected to each first solder pad 61 through each second conductive line 100.
[0061] Referring to Figure 1 , the fan-out wafer level package unit 1 is disposed on a printed circuit board (PCB) 3 by using each tin ball 110 for electrical connection, but not limited to.
[0062] Referring to Figure 2 , the carrier 10 includes a silicon (Si) carrier, a glass carrier, or a ceramic carrier, but not limited to, to facilitate diversified manufacturing.
[0063] Referring to Figure 8The metal paste 60a used by each first conductive connection 60 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto. The nano-silver paste material has the characteristics of low cost, high conductivity, and low-temperature sintering, but since the nano-silver paste material is a common material, further description is omitted.
[0064] Referring to Figure 1 The thickness of the fan-out wafer level package unit 1 is 200 um, but is not limited thereto.
[0065] Referring to Figure 13 The metal paste 100a used by each second conductive connection 100 includes silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto.
[0066] Referring to Figure 3 The first surface 21 of each die 20 is further disposed on the carrier 10 by a die attach film (DAF) 120, but is not limited thereto.
[0067] Referring to Figure 15 and Figure 16 The fan-out wafer level package unit 1 can be stacked in multiple to form a package 2, which includes at least two fan-out wafer level package units 1 and at least one connection line 2a.
[0068] Each fan-out wafer level package unit 1 is stacked together in a top-bottom corresponding relationship as shown in Figure 15 and Figure 16 The second pads 14 of the top fan-out wafer level package unit 1 form a corresponding relationship with the first pads 61 of the bottom fan-out wafer level package unit 1 as shown in Figure 15 and Figure 16 In the embodiment shown in Figure 15 and Figure 16 The package 2 has three fan-out wafer level package units 1, but is not limited thereto.
[0069] Each connection line 2a is disposed between the top fan-out wafer level package unit 1 and the bottom fan-out wafer level package unit 1, and is electrically connected to the second pads 14 of the top fan-out wafer level package unit 1 and the first pads 61 of the bottom fan-out wafer level package unit 1, so that the top fan-out wafer level package unit 1 and the bottom fan-out wafer level package unit 1 can be electrically connected to each other via the connection line 2a as shown in Figure 15 and Figure 16
[0070] Referring to Figure 15 and Figure 16 The dies 20 in the above fan-out wafer level package unit 1 can be the same as or different from the dies 20 in the below fan-out wafer level package unit 1 in terms of specifications and functions.
[0071] Referring to Figure 15 and Figure 16 , each connection line 2a is a solder ball, but is not limited.
[0072] Referring to Figure 10 and Figure 10 , the package 2 can be disposed on a printed circuit board (PCB) 3 by using the solder balls 110 for electrical connection, but is not limited.
[0073] Compared with the existing fan-out wafer level package technology, the package 2 has the following advantages.
[0074] (1) The fan-out wafer level package unit 1 can be manufactured by the process of step S4. Compared with the related manufacturing technology of the existing fan-out wafer level package unit, the fan-out wafer level package unit 1 can make the connection lines in the RDL produce XY plane electrical extension and interconnection, while also maintaining or achieving a certain degree of thinness, smallness and lightness. The steps are simple and easy to implement precisely, especially beneficial to reducing the thickness of the package unit. Therefore, the process of manufacturing the utility model not only can be simplified to save costs, but also can effectively improve the use efficiency and reliability of the fan-out wafer level package unit 1.
[0075] (2) The fan-out wafer level package unit 1 of the utility model, such as the process of step S4, is manufactured by using the technology of filling metal paste into the groove and then grinding the connection lines to form multiple connection lines on the dielectric layer, rather than using the existing plating or electroplating technology. Therefore, the utility model can effectively solve the problem of high manufacturing cost and environmental pollution in the existing fan-out package technology when manufacturing the connection lines.
[0076] (3) The second solder pads 14 of the carrier board 10 in the fan-out wafer level package unit 1 are located on the first surface 1b of the fan-out wafer level package unit 1, as shown in Figure 10 ; wherein the first solder pads 61 in the first openings 71 in the fan-out wafer level package unit 1 are located on the second surface 1c of the fan-out wafer level package unit 1, as shown in Figure 15As shown in the figure; wherein the layout of each second solder pad 14 on the first surface 1b of the fan-out wafer level packaging unit 1 is the same as that of each first solder pad 61 on the second surface 1c of the fan-out wafer level packaging unit 1, such as Figure 16 As shown in the figure, which is more helpful for manufacturing and mass production of products.
[0077] (4) The fan-out wafer level packaging unit 1 of the utility model can be stacked in multiple to form a package 2, which comprises at least two fan-out wafer level packaging units 1 and at least one connection line 2a; wherein each two fan-out wafer level packaging units 1 are stacked together in a corresponding relationship of upper and lower, such as Figure 15 and Figure 16 As shown in the figure; wherein each second solder pad 14 of the upper fan-out wafer level packaging unit 1 is in a corresponding relationship with each first solder pad 61 of the lower fan-out wafer level packaging unit 1, such as and As shown in the figure, which provides products with higher performance or more functions, and increases the market competitiveness of products.
[0078] The above is only the preferred embodiment of the utility model, which is only illustrative but not restrictive for the utility model; those skilled in the art understand that many changes, modifications, and even equivalent changes can be made to it within the spirit and scope defined by the claims of the utility model, but all will fall within the protection scope of the utility model.
Claims
1. A fan-out wafer level package unit, characterized by, Comprising: a carrier board having a first surface and an opposite second surface, and the carrier board having a plurality of first conductive posts penetrating through the first surface and the second surface; at least one die, each of the dies being singulated from a wafer, each of the dies having a first surface and an opposite second surface, the first surface of each of the dies being fixed on the second surface of the carrier board, the second surface of each of the dies having a plurality of die pads, and a vertical die region of the second surface being defined as a die region; a first dielectric layer disposed on the second surface of the carrier board and covering each of the dies, the first dielectric layer having at least one through-hole; wherein each of the through-holes is connected with each of the first conductive posts correspondingly; at least one second conductive post, each of the second conductive posts being formed in each of the through-holes and electrically connected with each of the first conductive posts, and each of the second conductive posts being exposed outside from each of the through-holes; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer having at least one groove formed horizontally; wherein each of the grooves is connected with each of the second conductive posts correspondingly; a plurality of first conductive lines, each of the first conductive lines being composed of a metal paste filled in each of the grooves; wherein each of the first conductive lines is electrically connected with each of the second conductive posts; a third dielectric layer disposed on the second dielectric layer and each of the first conductive lines, the third dielectric layer having at least one first opening; wherein each of the first conductive lines forms a first solder pad in each of the first openings by being exposed outside from each of the first openings; and a plurality of metal protection layers, each of the metal protection layers being formed in each of the first openings; wherein each of the metal protection layers is electrically connected with each of the first conductive lines; wherein each of the first conductive posts is exposed outside from the first surface of the carrier board, and a second solder pad is formed on the first surface of the carrier board; wherein each of the dies can be electrically connected outside in sequence via each of the die pads of the dies, each of the first conductive lines, each of the second conductive posts, each of the first conductive posts, and each of the second solder pads on the carrier board; wherein each of the dies can be electrically connected outside in sequence via each of the die pads of the dies, each of the first conductive lines, each of the metal protection layers, and each of the first solder pads around the die region on the second surface of each of the dies, so as to form the fan-out wafer level package unit; wherein the fan-out wafer level package unit further has a first surface and a second surface; wherein each of the second solder pads of the carrier board in the fan-out wafer level package unit is further on the first surface in the fan-out wafer level package unit; wherein each of the first solder pads in each of the first openings in the fan-out wafer level package unit is further on the second surface in the fan-out wafer level package unit; and wherein the layout of each of the second solder pads on the first surface of the fan-out wafer level package unit is the same as the layout of each of the first solder pads on the second surface of the fan-out wafer level package unit.
2. The fan-out wafer level package unit of claim 1, wherein, A fourth dielectric layer and a plurality of second conductive via lines are further formed on the first surface of the carrier substrate by using a redistribution layer technique; wherein the fourth dielectric layer has at least one second opening formed in a horizontal direction; each of the second conductive via lines is formed by a metal paste filled in each of the second openings; and each of the second conductive via lines is electrically connected to each of the second solder pads.
3. The fan-out wafer level packaging unit of claim 2, wherein, Each of the second conductive via lines further has a solder ball formed thereon, and each of the solder balls is electrically connected to each of the first solder pads through each of the second conductive via lines.
4. The fan-out wafer level packaging unit of claim 1, wherein, The carrier substrate is a silicon carrier substrate, a glass carrier substrate or a ceramic carrier substrate; and the metal paste used in each of the first conductive via lines is a silver paste, a nano-silver paste, a copper paste or a nano-copper paste.
5. The fan-out wafer level packaging unit of claim 1, wherein, The thickness of the fan-out wafer level package unit is 200 um.
6. The fan-out wafer level package unit of claim 2, wherein, The metal paste used in each of the second conductive via lines is a silver paste, a nano-silver paste, a copper paste or a nano-copper paste.
7. The fan-out wafer level package unit of claim 1, wherein, The first surface of each of the dies is attached to the carrier substrate by using a die attach film.
8. A package stacked by a plurality of fan-out wafer level package units, characterized in that, The fan-out wafer level package unit comprises: at least two fan-out wafer level package units, each of the fan-out wafer level package units is the fan-out wafer level package unit as claimed in any one of claims 1 to 7, and each of the two fan-out wafer level package units is stacked together in a top-bottom corresponding relationship; wherein each of the second solder pads of the top fan-out wafer level package unit is in a corresponding relationship with each of the first solder pads of the bottom fan-out wafer level package unit; and at least one connection line, each of the connection lines is arranged between the top fan-out wafer level package unit and the bottom fan-out wafer level package unit, and is electrically connected to each of the second solder pads of the top fan-out wafer level package unit and each of the first solder pads of the bottom fan-out wafer level package unit, so that the top fan-out wafer level package unit and the bottom fan-out wafer level package unit can be electrically connected to each other through each of the connection lines.
9. The package of claim 8, wherein, Each of the dies in the top fan-out wafer level package unit is identical or different in specification and function to each of the dies in the bottom fan-out wafer level package unit.
10. The package of claim 8, wherein, Each of the connection lines is a solder ball.