Improved redistribution circuit structure of wafer package

Abstract

The utility model provides an improved redistribution circuit structure of a wafer package, the wafer package comprises a wafer, a plurality of redistribution circuits and a plurality of nickel-gold layers, and each redistribution circuit is formed on the surface of the wafer in a manner of extending in the horizontal direction by utilizing a redistribution layer manufacturing process. And each nickel-gold layer is plated and formed on the surface of each redistribution circuit by utilizing a chemical nickel-gold process, each nickel-gold layer consists of a nickel layer and a gold layer, and the gold layer is positioned on the nickel layer, so that the problems that the nickel-gold layer is non-uniform in thickness and the process is complicated due to the fact that the nickel-gold layer is manufactured by adopting an electroplating process in the conventional wafer packaging are solved. In addition, each redistribution circuit can enable a plurality of crystal pads on the wafer to generate XY plane electrical extension and interconnection effects, so that a plurality of dispersed crystal pads can be formed around the wafer, and therefore, the design space and reliability of wafer packaging can be effectively improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of improved wafer packaging's circuit structure, especially a kind of improved wafer packaging's rewiring circuit structure. BACKGROUND

[0002] A kind of wafer packaging of existing, the wafer packaging includes wafer, multiple rewiring lines and multiple nickel-gold layers, each rewiring line is formed on the surface of the wafer using rewiring layer technique, each nickel-gold layer is formed on the surface of each rewiring line using electroplating technique. Since each nickel-gold layer of the wafer packaging is formed using electroplating technique, the thickness of nickel-gold layer is uneven, and the problem of complex process is generated.

[0003] In addition, the production mode of electroplating is relatively energy-consuming, which is not conducive to environmental protection and does not meet the manufacturing trend of green and environmentally friendly manufacturing industry, making it difficult for the manufacturing end to demonstrate social responsibility. Therefore, a wafer packaging that does not use electroplating technique to form nickel-gold layer is urgently needed by the relevant industry. SUMMARY

[0004] The main purpose of the utility model is to provide an improved wafer packaging rewiring circuit structure, which includes wafer, multiple rewiring lines and multiple nickel-gold layers, each rewiring line is formed on the surface of the wafer using horizontal direction extension of rewiring layer process, each nickel-gold layer is formed on the surface of each rewiring line using chemical nickel-gold process, each nickel-gold layer is composed of a nickel layer and a gold layer, and the gold layer is located on the nickel layer. This effectively solves the problem of uneven thickness of nickel-gold layer and complex process caused by using electroplating process to make nickel-gold layer in existing wafer packaging. In addition, each rewiring line can make multiple pads on the wafer have XY plane electrical extension and interconnection effect to form multiple pads around the wafer. This can effectively improve the design space and reliability of wafer packaging.

[0005] To achieve the above object, the utility model provides an improved re -distribution line structure of wafer package, the wafer package includes a wafer, a plurality of re -distribution lines and a plurality of nickel gold layers, wherein the surface of the wafer has a plurality of pads, wherein each re -distribution line is formed on the surface of the wafer by using a re -distribution layer process horizontally, and each re -distribution line has a surface, wherein the surface of the wafer includes at least one dielectric layer formed by the re -distribution layer process, each dielectric layer has a plurality of grooves formed horizontally, and each groove is used for exposing each pad of the wafer, wherein each re -distribution line is formed in each groove by metal material and is electrically connected with each pad, wherein each nickel gold layer is arranged on the surface of each re -distribution line in each groove, each nickel gold layer is composed of a nickel layer and a gold layer, and the gold layer of each nickel gold layer is located on the nickel layer, wherein the wafer is electrically connected outwardly in sequence through each pad, each re -distribution line and each nickel gold layer, characterized in that:

[0006] Each nickel gold layer is plated on the surface of each re -distribution line in each groove by using a chemical nickel gold process.

[0007] The improved re -distribution line structure of wafer package, wherein each re -distribution line is formed by copper or aluminum material.

[0008] The improved re -distribution line structure of wafer package, wherein the wafer further includes a first protective layer, and the side surface of each pad is surrounded by the first protective layer.

[0009] The improved re -distribution line structure of wafer package, wherein the wafer further includes a second protective layer, the second protective layer is arranged on the first protective layer, and the second protective layer has an opening for exposing each pad outwardly.

[0010] An improved re -distribution line structure of wafer package, the wafer package includes a wafer, a plurality of re -distribution lines and a plurality of nickel gold layers, wherein the surface of the wafer has a plurality of pads, wherein each re -distribution line is formed on the surface of the wafer by using a re -distribution layer process horizontally, and each re -distribution line has a surface and opposite two side surfaces, wherein each re -distribution line is electrically connected with each pad, wherein each nickel gold layer is arranged on the surface and the two side surfaces of each re -distribution line, each nickel gold layer is composed of a nickel layer and a gold layer, and the gold layer of each nickel gold layer is located on the nickel layer, wherein the wafer is electrically connected outwardly in sequence through each pad, each re -distribution line and each nickel gold layer, characterized in that:

[0011] Each nickel gold layer is plated on the surface and the two side surfaces of each re -distribution line by using a chemical nickel gold process.

[0012] The improved wafer package re-wiring structure, wherein each of the re-wiring lines is formed by copper or aluminum material.

[0013] The improved wafer package re-wiring structure, wherein the wafer further comprises a first protective layer, and the side of each of the pads is surrounded by the first protective layer.

[0014] The improved wafer package re-wiring structure, wherein the wafer further comprises a second protective layer, and the second protective layer is arranged on the first protective layer; wherein the second protective layer has an opening for each of the pads to be exposed.

[0015] The wafer package of the present application can effectively improve the design space and reliability. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a plane schematic diagram of a side view cross section of an embodiment of the wafer package of the present application.

[0017] Figure 2 is Figure 1 a cross section schematic diagram of a direction.

[0018] Figure 3 is a plane schematic diagram of a side view cross section of the groove formed on the dielectric layer of the present application.

[0019] Figure 4 is a plane schematic diagram of a side view cross section of another embodiment of the wafer package of the present application.

[0020] Figure 5 is Figure 4 a cross section schematic diagram of a direction.

[0021] Figure 6 is a plane schematic diagram of a side view cross section of the re-wiring line formed in the groove on the dielectric layer of the present application.

[0022] Figure 7 is a schematic diagram of removing the dielectric layer of Figure 6 completely.

[0023] Figure 8 is a plane schematic diagram of a side view cross section of another embodiment of the wafer package of the present application.

[0024] Figure 9 is a schematic diagram of removing the dielectric layer around the re-wiring line of Figure 6 completely.

[0025] Explanation of reference numerals: 1 - wafer package; 10 - wafer; 11 - die pad; 12 - first protective layer; 13 - second protective layer; 131 - opening; 20 - redistribution line; 21 - dielectric layer; 22 - groove; 23 - surface; 24 - side surface; 30 - nickel-gold layer; 31 - nickel layer; 32 - gold layer. DETAILED DESCRIPTION

[0026] The structure and technical features of the present application will be described in detail below with reference to the accompanying drawings, in which the drawings are used to illustrate the structural relationship and related functions of the present application, and thus the sizes of the elements in the drawings are not drawn to scale and are not intended to limit the present application.

[0027] Please refer to Figure 6 , Figure 1 and Figure 4 , the present application provides an improved wafer package redistribution line structure, which comprises a wafer 10, a plurality of redistribution lines 20 and a plurality of nickel-gold layers 30; wherein the surface of the wafer 10 has a plurality of die pads 11; wherein each of the redistribution lines 20 is formed horizontally on the surface of the wafer 10 by a redistribution layer (RDL, Redistribution Layer) process; wherein each of the redistribution lines 20 is electrically connected to each of the die pads 11; wherein each of the nickel-gold layers 30 is formed on each of the redistribution lines 20 by an electroless nickel immersion gold (ENIG, Electroless nickel immersion gold) process, each of the nickel-gold layers 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each of the nickel-gold layers 30 is located on the nickel layer 31 (as shown in Figure 8 and Figure 2 ) to prevent oxidation of the nickel layer 31; wherein the wafer 10 is electrically connected externally in sequence through each of the die pads 11, each of the redistribution lines 20 and each of the nickel-gold layers 30. The nickel-gold layer 30 formed by the electroless nickel immersion gold process is more uniform and flat than the nickel-gold layer formed by the electroplating process. In the embodiments of the present application, each of the die pads 11, each of the redistribution lines 20 and each of the nickel-gold layers 30 is only drawn as one representative for easy reading and explanation, but is not intended to limit the present application.

[0028] Please refer to Figure 5 , Figure 1 and Figure 4 , each of the redistribution lines 20 is further formed of copper (Cu) or aluminum (Al) metal material, but is not limited, to facilitate diversified manufacturing.

[0029] Please refer to Figure 8 , Figure 1 and Figure 4As shown, the wafer 10 further comprises a first protective layer 12 but not limited, the side of each of the pads 11 is surrounded by the first protective layer 12, which helps to increase the structural strength.

[0030] As shown in Figure 8 , Figure 1 and Figure 4 , the wafer 10 further comprises a second protective layer 13 but not limited, the second protective layer 13 is arranged on the first protective layer 12; wherein the second protective layer 13 has an opening 131 for each of the pads 11 to be exposed, which helps to increase the structural strength.

[0031] According to the different shapes of each of the redistribution lines 20 and each of the nickel-gold layers 30 in the wafer package 1 of the present application, and whether the surface of the wafer 10 has a dielectric layer, the wafer package 1 of the present application can be further divided into three embodiments but not limited, which are described as follows:

[0032] As shown in Figure 8 , the wafer package 1 is the first embodiment of the present application, wherein each of the redistribution lines 20 has a surface 23; wherein the surface of the wafer 10 further comprises at least one dielectric layer 21 formed by the redistribution layer process, each of the dielectric layers 21 has a plurality of grooves 22 formed in the horizontal direction, each of the grooves 22 is for each of the pads 11 of the wafer 10 to be exposed; wherein each of the redistribution lines 20 is further formed in each of the grooves 22 by a metal material and is electrically connected to each of the pads 11; wherein each of the nickel-gold layers 30 is arranged on the surface 23 of each of the redistribution lines 20 in each of the grooves 22.

[0033] The manufacturing method of the wafer package 1 (first embodiment) comprises the following steps:

[0034] Step S1: providing a wafer package 1 (as shown in Figure 1 ); wherein the wafer package 1 has a wafer 10, the surface of the wafer 10 has a plurality of redistribution lines 20 formed in the horizontal direction by a redistribution layer (RDL, Redistribution Layer) process, and each of the redistribution lines 20 is electrically connected to a plurality of pads 11 on the surface of the wafer 10 (as shown in Figure 3 ); wherein the forming method of each of the redistribution lines 20 further comprises the following steps: first, forming a dielectric layer 21 on the surface of the wafer 10, then forming a plurality of grooves 22 in the horizontal direction on each of the dielectric layers 21, and finally forming each of the redistribution lines 20 in each of the grooves 22 by a metal material (as shown in Figure 3 ); wherein each of the grooves 22 is for each of the pads 11 to be exposed, so that each of the redistribution lines 20 can be electrically connected to each of the pads 11 (as shown in Figure 3each of the redistribution lines 20 has a surface 23 (as shown in FIG. 1) and two opposite side surfaces 24 (as shown in FIG. 1); wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20. Figure 3

[0035] Step S2: forming a plurality of nickel-gold layers 30 on the surface 23 of each of the redistribution lines 20 in each of the grooves 22 by electroless nickel immersion gold (ENIG) process (as shown in FIG. 2); wherein each of the nickel-gold layers 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each of the nickel-gold layers 30 is disposed on the nickel layer 31 (as shown in FIG. 2). Figure 3 Figure 1

[0036] In the embodiment shown in FIG. 1, the redistribution lines 20 are formed by the following steps: Figure 2 In the second embodiment of the present application, each of the redistribution lines 20 has a surface 23 and two opposite side surfaces 24; wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20.

[0037] The manufacturing method of the wafer package 1 (the second embodiment) includes the following steps:

[0038] Step S1: providing a wafer package 1 (as shown in FIG. 1); wherein the wafer package 1 has a wafer 10, and the wafer 10 has a surface with a plurality of redistribution lines 20 formed thereon by redistribution layer (RDL) process in horizontal direction, and each of the redistribution lines 20 is electrically connected with a plurality of pads 11 on the surface of the wafer 10 (as shown in FIG. 1). Figure 8 Figure 6 Figure 6 Figure 6 Figure 6 each of the redistribution lines 20 has a surface 23 (as shown in FIG. 1) and two opposite side surfaces 24 (as shown in FIG. 1); wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20.

[0039] Step S2: removing the dielectric layer 21 around each of the redistribution lines 20, so that the two side surfaces 24 of each of the redistribution lines 20 are exposed (as shown in FIG. 3). Figure 6

[0040] ​​​​​​​​Step S3: forming a plurality of nickel-gold layers 30 (as shown in Figure 9 ) on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20 by using an electroless nickel immersion gold (ENIG) process.

[0041] In Figure 8 , the embodiment shown is a third embodiment of the present application, each of the redistribution lines 20 has a surface 23 and two opposite side surfaces 24; wherein each of the nickel-gold layers 30 is disposed on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20.

[0042] The manufacturing method of the wafer package 1 (third embodiment) comprises the following steps:

[0043] Step S1: providing a wafer package 1 (as shown in Figure 4 ); wherein the wafer package 1 has a wafer 10, the wafer 10 has a surface, and a plurality of redistribution lines 20 are horizontally formed on the surface of the wafer 10 by using a redistribution layer (RDL) process, and each of the redistribution lines 20 is electrically connected to a plurality of pads 11 on the surface of the wafer 10 (as shown in Figure 6 ); wherein each of the redistribution lines 20 is further formed by first forming a dielectric layer 21 on the surface of the wafer 10, then horizontally forming a plurality of grooves 22 on each of the dielectric layers 21, and finally forming each of the redistribution lines 20 in each of the grooves 22 by using a metal material (as shown in Figure 6 ); wherein each of the grooves 22 is used for exposing each of the pads 11 to the outside, so that each of the redistribution lines 20 can be electrically connected to each of the pads 11 (as shown in Figure 6 ); wherein each of the redistribution lines 20 has a surface 23 (as shown in Figure 6 ).

[0044] Step S2: removing each of the dielectric layers 21 around each of the redistribution lines 20, so that two side surfaces 24 (as shown in Figure 6 ) of each of the redistribution lines 20 are exposed to the outside, and each of the dielectric layers 21 is further completely removed from the surface 23 of the wafer 10.

[0045] Step S3: forming a plurality of nickel-gold layers 30 (as shown in Figure 7 ) on the surface 23 and the two side surfaces 24 of each of the redistribution lines 20 by using an electroless nickel immersion gold (ENIG) process.

[0046] Compared with the existing wafer package, the wafer package 1 of the present application has the following advantages:

[0047] (1) The nickel-gold layers 30 of this invention are plated and formed on the redistribution circuits 20 using an electroless nickel-gold (ENIG) process. Each nickel-gold layer 30 is composed of a nickel (Ni) layer 31 and a gold (Au) layer 32, and the gold layer 32 of each nickel-gold layer 30 is located on the nickel layer 31 (e.g., Figure 8 and Figure 2 As shown, this effectively solves the problems of uneven nickel-gold layer thickness and complex processes in existing chip packaging, which use electroplating to produce the nickel-gold layer. This not only improves product reliability but also saves manufacturing costs. In addition, the chemical nickel-gold process is more energy-efficient and environmentally friendly than the existing electroplating method used in chip packaging, which aligns with the manufacturing trend towards green and environmentally friendly practices.

[0048] (2) Each of the redistribution lines 20 is formed on the surface of the chip 10 by extending horizontally using a redistribution layer (RDL) process. Since each of the redistribution lines 20 is a process that is easy to implement precisely, the process is relatively simple, which is sufficient to enable each of the redistribution lines 20 to generate XY plane electrical extension and interconnection, while also enabling the finished chip package 1 to maintain or achieve a certain degree of thinness and small size.

[0049] (3) Each of the nickel-gold layers 30 in this utility model is a metal stacked structure with a certain thickness (e.g., Figure 5 and Figure 2 Figure 5 As shown), this can enhance the structural strength of each of the redistributed circuits 20. If the chip package 1 chooses to generate electrical connections to the outside through wire bonding process, each of the nickel-gold layers 30 can help withstand the positive pressure generated from the wire bonding operation or the formation of solder joints, so that each of the redistributed circuits 20 is not easily damaged by the positive pressure.

[0050] The above description is only a preferred embodiment of the present utility model and is illustrative only, not restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made to the present utility model within the spirit and scope defined therein, but all of these will fall within the protection scope of the present utility model.

Claims

1. An improved re-distribution structure of a wafer package, the wafer package comprising a wafer, a plurality of re-distribution lines and a plurality of nickel-gold layers; wherein the wafer has a plurality of pads on a surface thereof; wherein each of the re-distribution lines is horizontally formed on the surface of the wafer by a re-distribution layer process, and each of the re-distribution lines has a surface; wherein the surface of the wafer comprises at least one dielectric layer formed by the re-distribution layer process, each of the dielectric layers has a plurality of grooves horizontally formed thereon, and each of the grooves is for exposing each of the pads of the wafer; wherein each of the re-distribution lines is formed of a metal material in each of the grooves and electrically connected to each of the pads; wherein each of the nickel-gold layers is disposed on the surface of each of the re-distribution lines in each of the grooves, each of the nickel-gold layers is composed of a nickel layer and a gold layer, and the gold layer of each of the nickel-gold layers is on the nickel layer; wherein the wafer is electrically connected to the outside in sequence via each of the pads, each of the re-distribution lines and each of the nickel-gold layers; characterized in that: each of the nickel-gold layers is plated on the surface of each of the re-distribution lines in each of the grooves by a chemical nickel-gold process.

2. The modified wafer-level package redistribution structure of claim 1, wherein: each of the re-distribution lines is formed of copper or aluminum material.

3. The modified wafer-level package redistribution structure of claim 1, wherein: the wafer further comprises a first protective layer, and sides of each of the pads are surrounded by the first protective layer.

4. The modified wafer-level package redistribution structure of claim 3, wherein: the wafer further comprises a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for exposing each of the pads to the outside.

5. An improved redistribution structure for wafer level packaging, the wafer level packaging comprising a wafer, a plurality of redistribution lines and a plurality of nickel-gold layers; wherein: the wafer has a plurality of pads on a surface thereof; wherein each of the re-distribution lines is horizontally formed on the surface of the wafer by a re-distribution layer process, and each of the re-distribution lines has a surface and two opposite sides; wherein each of the re-distribution lines is electrically connected to each of the pads; wherein each of the nickel-gold layers is disposed on the surface and the two sides of each of the re-distribution lines, each of the nickel-gold layers is composed of a nickel layer and a gold layer, and the gold layer of each of the nickel-gold layers is on the nickel layer; wherein the wafer is electrically connected to the outside in sequence via each of the pads, each of the re-distribution lines and each of the nickel-gold layers; characterized in that: each of the nickel-gold layers is plated on the surface and the two sides of each of the re-distribution lines by a chemical nickel-gold process.

6. The modified wafer-level package redistribution structure of claim 5, wherein: each of the re-distribution lines is formed of copper or aluminum material.

7. The modified wafer-level package redistribution structure of claim 5, wherein: the wafer further comprises a first protective layer, and sides of each of the pads are surrounded by the first protective layer.

8. The modified wafer-level package redistribution structure of claim 7, wherein: the wafer further comprises a second protective layer disposed on the first protective layer; wherein the second protective layer has an opening for exposing each of the pads to the outside.

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