Time delay circuit, circuit board assembly and electronic equipment
By using the gate capacitor charging and discharging process of an inverter in the delay circuit, combined with the control of a current source and a PMOS inverting transistor, the miniaturization and cost reduction of the delay circuit are achieved, solving the problems of large size and high cost of RC delay circuits, and improving the reliability and signal quality of the delay circuit.
Patent Information
- Application Number
- CN202423003043.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2025-12-19
- Estimated Expiration
- 2034-12-05
AI Technical Summary
Existing RC delay circuits cannot meet the requirements of miniaturization and cost reduction, resulting in larger chip size and increased cost.
A delay circuit design is adopted, which includes a first switching module, a second switching module and a first inverter. The delay is achieved by utilizing the charging and discharging process of the inverter's gate capacitor, eliminating the need for capacitors and resistors. The delay time is adjusted by controlling the width-to-length ratio of the current source and the PMOS inverting transistor.
It significantly reduces the size of the delay circuit in the chip, lowers the cost, and makes the delay time controllable, thereby improving the reliability and signal quality of the delay circuit.
Smart Images
Figure CN223693892U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of circuit, in particular to a delay circuit, a circuit board assembly and an electronic device. BACKGROUND
[0002] At present, with the development of high-speed mixed signal circuits, the timing of signals increasingly has a crucial impact on the overall system, therefore, when setting the circuit, a number of delay circuits are often added to generate or compensate for the delay difference between paths to achieve specific performance requirements. With the continuous development of integrated circuit technology, the requirements for small size and low cost of delay circuits are also increasingly high, therefore, it is increasingly important to set a delay circuit with small area and low cost.
[0003] The related art often uses RC (Resistance-Capacitance) delay circuits, but the current RC delay circuit still cannot meet the increasingly high requirements for small size and low cost of delay circuits. CONTENT OF THE INVENTION
[0004] The purpose of the embodiments of the present application is to provide a delay circuit, a circuit board assembly and an electronic device, thereby reducing the volume occupied by the delay circuit in the chip and reducing the cost.
[0005] To solve the above technical problems, the embodiments of the present application provide a delay circuit, comprising: a first switch module, a second switch module, a first inverter, a power consumption module; the control end of the first switch module is configured to receive an initial clock signal, and the control end of the second switch module is configured to receive an enable signal; the input end of the first switch module is connected to a power supply, the output end of the first switch module is connected to the input end of the second switch module, and the output end of the second switch module is grounded; the output end of the first switch module is also connected to the input end of the first inverter; the input end of the first inverter is also connected to the input end of the power consumption module; and the output end of the first inverter is configured to output a first delay clock signal.
[0006] The embodiments of the present application also provide a circuit board assembly, comprising: the above delay circuit.
[0007] The embodiments of the present application also provide an electronic device, comprising: the above circuit board assembly.
[0008] In some embodiments, the delay circuit further comprises a first shaping module; the input end of the first shaping module is connected to the output end of the first inverter, and the first shaping module is configured to perform shaping processing on the first delay clock signal to obtain a target delay clock signal and output the target delay clock signal.
[0009] In some embodiments, the first shaping module comprises a second inverter and a third inverter; an input end of the second inverter serves as an input end of the first shaping module, an output end of the second inverter is connected to an input end of the third inverter, and an output end of the third inverter serves as an output end of the first shaping module.
[0010] In some embodiments, the delay circuit further comprises a second shaping module; a control end of the second shaping module is connected to an output end of the first inverter, an input end of the second shaping module is connected to an input end of the first inverter, and an output end of the second shaping module is grounded.
[0011] In some embodiments, the second shaping module is an NMOS tube; a gate of the NMOS tube serves as the control end of the second shaping module, a drain of the NMOS tube serves as the input end of the second shaping module, and a source of the NMOS tube serves as the output end of the second shaping module.
[0012] In some embodiments, the power consumption module comprises a current source, a fourth switch module and a fifth switch module.
[0013] An input end of the current source is connected to a power supply, an output end of the current source is connected to an input end of the fourth switch module, the output end of the current source is also connected to a control end of the fourth switch module, the control end of the fourth switch module is also connected to a control end of the fifth switch module; an output end of the fourth switch module is grounded, an input end of the fifth switch module serves as an input end of the power consumption module, and an output end of the fifth switch module is grounded.
[0014] In some embodiments, the first switch module is a PMOS inverter.
[0015] In some embodiments, the second switch module is an NMOS tube.
[0016] The embodiments of the present disclosure have at least the following advantages:
[0017] In the delay circuit, when the initial clock signal received by the delay circuit is switched from a high level to a low level or from a low level to a high level, the first inverter is used to realize the delay of the initial clock signal by using the charging and discharging process of the gate capacitance of the first inverter, and the whole circuit does not need to be provided with a capacitor and a resistor. Compared with the RC delay circuit in the related art, the volume of the whole circuit in the chip is greatly reduced, and the cost is also reduced. Moreover, the rising edge delay time and the falling edge delay time of the delay circuit of the present embodiment are controllable, and the reliability of the delay circuit is high. BRIEF DESCRIPTION OF DRAWINGS
[0018] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which are shown by way of example and not limitation in the figures are not necessarily drawn to scale unless otherwise specifically noted. Figures in the drawings are illustrative of like elements of the embodiments and it will be appreciated that elements prefixed by identical reference numerals in the figures are intended to represent identical or like elements of the embodiments, unless otherwise specifically noted. The figures in the drawings do not limit the scope of the embodiments.
[0019] Figure 1 is a circuit structure schematic diagram of a delay circuit according to an embodiment of the present application;
[0020] Figure 2 is a circuit structure schematic diagram of a first inverter according to an embodiment of the present application;
[0021] Figure 3 is a circuit structure schematic diagram of a power consumption unit according to an embodiment of the present application;
[0022] Figure 4 is a circuit structure schematic diagram of a delay circuit according to an embodiment of the present application. DETAILED DESCRIPTION
[0023] As can be known from the background, the current RC delay circuit cannot meet the increasingly high requirements for miniaturization and low cost of the delay circuit.
[0024] It is found through analysis that the RC delay circuit is formed by the combination of a capacitor and a resistor, and a single capacitor or a single resistor occupies a large area in a chip, thereby causing the RC delay circuit to occupy a large volume in the chip, resulting in an increase in the cost of the chip.
[0025] The present application improves a delay circuit, which comprises a first switch module, a second switch module, a first inverter, and a power consumption module. The control end of the first switch module is configured to receive an initial clock signal, and the control end of the second switch module is configured to receive an enable signal. The input end of the first switch module is connected to a power supply, the output end of the first switch module is connected to the input end of the second switch module, and the output end of the second switch module is grounded. The output end of the first switch module is also connected to the input end of the first inverter. The input end of the first inverter is also connected to the input end of the power consumption module. The output end of the first inverter is configured to output a first delay clock signal.
[0026] The present application sets a first inverter in the delay circuit. When the initial clock signal received by the delay circuit is switched from a high level to a low level or from a low level to a high level, the delay of the initial clock signal is realized by the charging and discharging process of the gate capacitance of the first inverter. The entire circuit does not need to be provided with a capacitor and a resistor. Compared with the RC delay circuit in the related art, the volume of the entire circuit in the chip is greatly reduced, and the cost is also reduced. Moreover, the rising edge and falling edge delay time of the delay circuit of the present application are controllable, and the reliability of the delay circuit is high.
[0027] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation modes of the present application, and the embodiments can be combined and referenced with each other under the premise of no contradiction.
[0028] An embodiment of the present application relates to a delay circuit, and a specific circuit structure schematic diagram is as shown in the figure Figure 1 The delay circuit comprises a first switch module 101, a second switch module 102, a first inverter INV1 and a power consumption module 103.
[0029] Specifically, a control end of the first switch module 101 is configured to receive an initial clock signal CLK0, and a control end of the second switch module 102 is configured to receive an enable signal; an input end of the first switch module 101 is connected to a power supply, an output end of the first switch module 101 is connected to an input end of the second switch module 102, and an output end of the second switch module 102 is grounded; the output end of the first switch module 101 is further connected to an input end of the first inverter INV1; the input end of the first inverter INV1 is further connected to an input end of the power consumption module 103; and an output end of the first inverter INV1 is configured to output a first delay clock signal CLK1.
[0030] Specifically, the first switch module 101 in the embodiment is configured to be turned on at a low level and turned off at a high level, and the second switch module 102 can be configured to be turned on when the enable signal is received, wherein the enable signal can be a high-level signal or a low-level signal, and the embodiment does not make specific limitation. In an embodiment, the second switch module 102 is an NMOS tube N1, and the second switch module 102, i.e. the NMOS tube N1, is turned on when the enable signal is a high-level signal.
[0031] Specifically, the initial clock signal CLK0 is a square wave signal; when the initial clock signal CLK0 is at a low level, the second switch module 102 is turned on under the control of the enable signal, the control end of the first switch module 101 is at a low level, the first switch module 101 is turned on, the input end voltage of the first inverter INV1 is at a high level, and the first inverter INV1 inverts the high level to obtain the first delay clock signal CLK1 at a low level; when the initial clock signal CLK0 is at a high level, the control end of the first switch module 101 is at a high level, the first switch module 101 is turned off, and the input end voltage of the first inverter INV1 is at a low level. The first inverter INV1 inverts the low level to obtain the first delay clock signal CLK1 at a high level; thereby realizing the synchronization of the first delay clock signal CLK1 output by the first inverter INV1 and the initial clock signal CLK0 through this mode.
[0032] Specifically, the structure diagram of the first inverter of the embodiment is as shown in Figure 2 , which includes a PMOS tube M P , an NMOS tube M N , the gate of the PMOS tube M P and the gate of the NMOS tube M N together as the input end of the first inverter INV1, the source of the PMOS tube M P connected to the power supply, the drain of the PMOS tube M P connected to the drain of the NMOS tube M N , the source of the NMOS tube M N grounded, and a node A between the drain of the PMOS tube M P and the drain of the NMOS tube M N , which outputs the first delay clock signal CLK1 as the output end of the first inverter INV1.
[0033] Since the gate of the PMOS tube M P and the gate of the NMOS tube M N form a capacitor structure similar to a capacitor, when the initial clock signal CLK0 changes from a low level to a high level, i.e., the voltage at the input end of the first inverter INV1 changes from a high level to a low level, the voltage will not suddenly decrease due to the existence of the gate capacitor. Therefore, the embodiment connects a power module 103 to the input end of the first inverter INV1, which consumes the charge of the gate capacitor through the power module 103, so that the first inverter INV1 finally realizes signal inversion and achieves the delay function.
[0034] Specifically, when the initial clock signal CLK0 input to the first switch module 101 is converted from low level to high level, the first switch module 101 is turned off, and the input end of the first inverter INV1 is a low level signal; due to the existence of the gate capacitance of the first inverter INV1, the voltage of the input end of the first inverter INV1 will not suddenly decrease, and the charge stored by the gate capacitance is discharged by a power consumption unit (such as a current mirror circuit), the discharging speed of which is controlled by a current source in the current mirror, and the current of the current source is related to the amount of charge stored by the gate capacitance. When the charge of the gate capacitance at Ready is reduced to below the threshold voltage, the first inverter INV1 works to convert the low level signal into the first delay clock signal CLK1 of high level. Referring to the formula CV=It, wherein C is the amount of charge of the gate capacitance of the first inverter INV1, V is the voltage value of the input end of the first inverter INV1, I is the discharging current value of the current source, and t is the discharging time, i.e. the delay time. Among them, C and V are both fixed values determined by the circuit devices in the delay circuit, and can be obtained according to the configuration information of the delay circuit. It can be seen that the delay time of the rising edge of the first delay clock signal CLK1 output by the first inverter INV1 is inversely proportional to the current of the current source. Therefore, the delay time of the rising edge of the delay circuit can be controlled by controlling the current of the current source in the embodiment.
[0035] Specifically, when the initial clock signal CLK0 input to the first switch module 101 is converted from high level to low level, the first switch module 101 is turned on, and the input end of the first inverter INV1 is a high level signal; due to the existence of the gate capacitance of the first inverter INV1, the voltage at Ready will not suddenly rise, and the charge at Ready is charged by the current flowing through the first switch module 101. The first switch module 101 in the embodiment is a PMOS inverter P1, and the current flowing through the first switch module 101, i.e. the PMOS inverter P1, is controlled by the width-length ratio of the PMOS inverter P1. Referring to the formula I=1 / 2μCoxW / L(Vgs-Vth)2, Cox is the oxide layer thickness of the PMOS inverter P1, W / L is the width-length ratio of the PMOS inverter P1, Vgs is the gate-source voltage of the PMOS inverter P1, and Vth is the threshold value of the conduction voltage. When the charge at Ready rises above the threshold voltage of the gate capacitance, the first inverter INV1 works to convert the high level signal into a low level signal. Therefore, the delay time of the falling edge of the first delay clock signal CLK1 output by the first inverter INV1 can be controlled by controlling the width-length ratio of the PMOS inverter P1, thereby controlling the current of the PMOS inverter P1.
[0036] Specifically, the gate of the PMOS inverted transistor P1 is the control terminal of the first switching module 101, the source of P1 is the input terminal of the first switching module 101, and the drain of P1 is the output terminal of the first switching module 101. In this embodiment, by setting the first switching module 101 as the PMOS inverted transistor P1, since the inverted transistor has the characteristic of low current, under the same charge of the gate capacitor, the smaller the current, the longer the delay time, which can make the delay circuit achieve a better delay effect.
[0037] like Figure 3 The diagram shows the circuit structure of the power consumption unit. This embodiment uses a current mirror as an example for illustration. The power consumption module 103 includes: a current source I, a fourth switch module 1031, and a fifth switch module 1032. The input terminal of the current source I is connected to the power supply, and the output terminal of the current source I is connected to the input terminal of the fourth switch module 1031. The output terminal of the current source I is also connected to the control terminal of the fourth switch module 1031, and the control terminal of the fourth switch module 1031 is also connected to the control terminal of the fifth switch module. The output terminal of the fourth switch module 1031 is grounded, and the input terminal of the fifth switch module 1032 serves as the input terminal of the power consumption module 103. It receives the first delayed clock signal CLK1 through the Ready point, and the output terminal of the fifth switch module 1032 is grounded.
[0038] In this module, the fourth switch module 1031 is an NMOS transistor N2, and the fifth switch module 1032 is an NMOS transistor N3. The gate of NMOS transistor N2 is the control terminal of the fourth switch module 1031, the drain of NMOS transistor N2 is the input terminal of the fourth switch module 1031, and the source of NMOS transistor N2 is the output terminal of the fourth switch module 1031. The gate of NMOS transistor N3 is the control terminal of the fifth switch module 1032, the drain of NMOS transistor N3 is the input terminal of the fifth switch module 1032, and the source of NMOS transistor N3 is the output terminal of the fifth switch module 1032.
[0039] In this embodiment, the fifth switch module 1032 in the current mirror, namely the NMOS transistor N3, consumes the charge in the gate capacitor. The consumption rate can be controlled by controlling the current magnitude of the current source I, thereby making the delay time of the rising edge of the delay circuit controllable.
[0040] In this embodiment, a first inverter INV1 is set in the delay circuit. When the initial clock signal CLK0 received by the delay circuit switches from high level to low level or from low level to high level, the charging and discharging process of the gate capacitor of the first inverter INV1 is used to delay the initial clock signal CLK0. The entire circuit does not require capacitors and resistors. Compared with the RC delay circuit in related technologies, the volume occupied by the entire circuit in the chip is greatly reduced, which also reduces the cost. Furthermore, the delay time of the rising edge and falling edge of the delay circuit in this embodiment can be controlled, and the reliability of the delay circuit is high.
[0041] Another embodiment of this application relates to a delay circuit. The difference between this embodiment and the previous embodiment is that the delay circuit in this embodiment further includes a first shaping module and a second shaping module. A schematic diagram of the specific circuit structure of the delay circuit in this embodiment is shown below. Figure 4 As shown, the delay circuit includes: a first switch module 101, a second switch module 102, a first inverter INV1, a power supply module 103, a first shaping module 104, and a second shaping module 105.
[0042] Specifically, the control terminal of the first switch module 101 is configured to receive the initial clock signal CLK0, and the control terminal of the second switch module 102 is configured to receive the enable signal; the input terminal of the first switch module 101 is connected to the power supply, the output terminal of the first switch module 101 is connected to the input terminal of the second switch module 102, and the output terminal of the second switch module 102 is grounded; the output terminal of the first switch module 101 is also connected to the input terminal of the first inverter INV1; the input terminal of the first inverter INV1 is also connected to the input terminal of the power module 103; the output terminal of the first inverter INV1 is configured to output the first delayed clock signal CLK1.
[0043] Specifically, the input terminal of the first shaping module 104 is connected to the output terminal of the first inverter INV1. The first shaping module 104 is configured to shape the first delayed clock signal CLK1 to obtain the target delayed clock signal CLK, and output the target delayed clock signal CLK.
[0044] like Figure 4 As shown, the first shaping module 104 in this embodiment includes a second inverter INV2 and a third inverter INV3. The input terminal of the second inverter INV2 serves as the input terminal of the first shaping module 104, the output terminal of the second inverter INV2 is connected to the input terminal of the third inverter INV3, and the output terminal of the third inverter INV3 serves as the output terminal of the first shaping module 104. The circuit structures of the second inverter INV2 and the third inverter INV3 are largely the same as the circuit structure of the first inverter INV1, and will not be described again here to avoid repetition.
[0045] Specifically, the initial clock signal CLK0 is a square wave signal, and the initial clock signal CLK0 may encounter problems such as attenuation, amplitude reduction, or capacitive load during transmission, which will cause the leading edge of the pulse signal to become irregular and no longer an ideal rectangular pulse. Therefore, the first shaping module 104, i.e., the second inverter INV2 and the third inverter INV3, is arranged at the output end of the first inverter INV1, the first delay clock signal CLK1 output by the first inverter INV1 is shaped by the second inverter INV2 and the third inverter INV3, the amplitude, frequency, and phase characteristics of the first delay clock signal CLK1 are adjusted, the target delay clock signal CLK output by the first shaping module 104 is restored to a regular square wave signal, and thus the quality and accuracy of the signal are improved.
[0046] Specifically, the second inverter INV2 receives the first delay clock signal CLK1, inverts the first delay clock signal CLK1 to obtain the second delay clock signal CLK2, and the third inverter INV3 receives the second delay clock signal CLK2, inverts the second delay clock signal CLK2 to obtain the target delay clock signal CLK. After two inversions, the phase of the target delay clock signal CLK is consistent with that of the first delay clock signal CLK1. For example, when the first delay clock signal CLK1 is at a high level, the second delay clock signal CLK2 is inverted to a low level by the second inverter INV2, and the target delay clock signal CLK is inverted to a high level by the third inverter INV3. When the first delay clock signal CLK1 is at a low level, the second delay clock signal CLK2 is inverted to a high level by the second inverter INV2, and the target delay clock signal CLK is inverted to a low level by the third inverter INV3. Thus, the phase of the target delay clock signal CLK is consistent with that of the first delay clock signal CLK1. Moreover, the time occupied by the second inverter INV2 and the third inverter INV3 during signal inversion can be ignored, the signal shaping of the delay circuit is realized, and the accuracy of the rising edge and falling edge delay time of the delay circuit is ensured.
[0047] Specifically, the control end of the second shaping module 105 is connected to the output end of the first inverter INV1, the input end of the second shaping module 105 is connected to the input end of the first inverter INV1, and the output end of the second shaping module 105 is grounded.
[0048] As Figure 4As shown, the second shaping module 105 in this embodiment is an NMOS tube N4, the gate of the NMOS tube N4 is used as the control end of the second shaping module 105, is used for connecting the output end of the first inverter INV1, the drain of the NMOS tube N4 is used as the input end of the second shaping module 105, is used for connecting the input end of the first inverter INV1, that is, the Ready point, and the source of the NMOS tube N4 is used as the output end of the second shaping module 105, and is used for grounding.
[0049] Specifically, when the first delay clock signal CLK1 is high, the NMOS tube N4 is turned on, the signal at the input end of the first inverter INV1 is pulled low, so that the initial clock signal CLK0 at the input of the first inverter INV1 is closer to 0, and the first delay clock signal CLK1 obtained after the first inverter INV1 inverts the initial clock signal CLK0 is closer to 1, thereby improving the accuracy of the obtained first delay clock signal CLK1. It should be noted that when the first delay clock signal CLK1 is low, the NMOS tube N4 is turned off, and the NMOS tube N4 does not work.
[0050] In this embodiment, the first delay clock signal CLK1 is shaped, so that the waveform of the final output target delay clock signal CLK is more regular, the quality and accuracy of the output signal of the delay circuit are improved, and the accuracy of the rising edge and falling edge delay time is also ensured.
[0051] In another aspect, the present application also provides a circuit board assembly, comprising the delay circuit according to any one of the above embodiments.
[0052] It can be found that the present embodiment is a circuit board assembly embodiment corresponding to the circuit embodiment, and the present embodiment can be implemented in cooperation with the circuit embodiment. The related technical details mentioned in the circuit embodiment are still valid in the present embodiment. In order to reduce repetition, they will not be described here. Correspondingly, the related technical details mentioned in the present embodiment can also be applied to the circuit embodiment.
[0053] In addition, in order to highlight the innovative part of the present application, some units that are not closely related to solving the technical problems proposed in the present application are not introduced in the present embodiment, but this does not mean that there are no other units in the present embodiment.
[0054] In another aspect, the present application also provides an electronic device, comprising the circuit board assembly according to the above embodiment.
[0055] The division of the above various components is only for the purpose of clear description, and when implemented, it can be combined into one component or some components can be split and decomposed into multiple components, as long as the same logical relationship is included, which is within the protection scope of the present application.
[0056] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and various changes can be made in form and details in actual application without departing from the spirit and scope of the present application.
Claims
1. A delay circuit, characterized by, Comprising: a first switch module, a second switch module, a first inverter, a power consumption module; a control end of the first switch module is configured to receive an initial clock signal, a control end of the second switch module is configured to receive an enable signal; an input end of the first switch module is connected to a power supply, an output end of the first switch module is connected to an input end of the second switch module, and an output end of the second switch module is grounded; an output end of the first switch module is also connected to an input end of the first inverter; an input end of the first inverter is also connected to an input end of the power consumption module; and an output end of the first inverter is configured to output a first delay clock signal.
2. The delay circuit of claim 1, wherein The delay circuit further comprises a first shaping module; an input end of the first shaping module is connected to an output end of the first inverter, and the first shaping module is configured to perform shaping processing on the first delay clock signal to obtain a target delay clock signal and output the target delay clock signal.
3. The delay circuit of claim 2, wherein The first shaping module comprises a second inverter and a third inverter. An input end of the second inverter serves as an input end of the first shaping module, an output end of the second inverter is connected to an input end of the third inverter, and an output end of the third inverter serves as an output end of the first shaping module.
4. The delay circuit according to any one of claims 1 to 3, characterized by The delay circuit further comprises a second shaping module. A control end of the second shaping module is connected to an output end of the first inverter, an input end of the second shaping module is connected to an input end of the first inverter, and an output end of the second shaping module is grounded.
5. The delay circuit of claim 4, wherein, The second shaping module is an NMOS tube, a gate of the NMOS tube serves as a control end of the second shaping module, a drain of the NMOS tube serves as an input end of the second shaping module, and a source of the NMOS tube serves as an output end of the second shaping module.
6. The delay circuit according to any one of claims 1 to 3, characterized by The power consumption module comprises a current source, a fourth switch module, and a fifth switch module. An input end of the current source is connected to a power supply, an output end of the current source is connected to an input end of the fourth switch module, the output end of the current source is also connected to a control end of the fourth switch module, the control end of the fourth switch module is also connected to a control end of the fifth switch module; an output end of the fourth switch module is grounded, an input end of the fifth switch module serves as an input end of the power consumption module, and an output end of the fifth switch module is grounded.
7. The delay circuit of claim 1, wherein The first switch module is a PMOS inverter.
8. The delay circuit of claim 4, wherein, The second switch module is an NMOS tube.
9. A circuit board assembly, characterized by The delay circuit comprises any one of claims 1 to 8.
10. An electronic device, comprising: Comprising: The circuit board assembly of claim 9.