MOS device with higher grid protection effect

Abstract

The utility model discloses an MOS device with a higher grid protection effect, and relates to the technical field of semiconductors. A layer of high-K dielectric material with a higher dielectric constant than SiO2 is prepared on the top surface of a SiC Drift layer of a JFET (Junction Field Effect Transistor) region, the materials comprise Al2O3, TiO2, ZrO2, HfO2 and the like, and the high-dielectric constant material is more difficult to be subjected to electric breakdown, so that the gate oxide strength of a SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device can be better improved, and the long-term stable use of the device is improved. In order to prevent the conduction performance of the device from becoming poor after the gate pole is opened, the SiO2 gate oxide layer is arranged above the channel region, so that the conduction performance of the device is not influenced too much, and the gate oxide strength of the device is improved at the same time.

Description

TECHNICAL FIELD

[0001] The utility model relates to a semiconductor technical field especially relates to a MOS device of higher gate protection effect. BACKGROUND

[0002] With the development of society and the innovation of technology, the requirement of electronic components is more and more strict in many fields such as automobile and photovoltaic energy storage. The traditional Si-based power device almost occupies all the scenes of these application fields, but at present, the Si-based power device is difficult to meet the application demand of these rapid development. In order to solve this bottleneck, the third generation of wide band gap semiconductor power device represented by SiC can make the system have higher transmission energy efficiency due to its excellent performance, so it is considered as the core product in the future in the fields of high voltage, high temperature and high frequency application.

[0003] Compared with Si MOSFET and Si IGBT, SiC MOSFET can have good static conduction and dynamic switching performance at the same time due to the advantages of device structure and material itself, and is popular in the 800V electrical architecture platform of new energy automobile and the high-power application scene of photovoltaic, and has begun to replace Si-based device in a large area. However, SiC MOSFET also has disadvantages. The gate oxide layer of SiC MOSFET is formed by direct growth through oxidation, but due to the C element in the material, the SiO2 oxide layer interface state density is large and the defects are many, which is difficult to withstand high electric field intensity. If the design is not proper, it is easy to cause the gate oxide layer to break down and fail in the use process, which is also a big problem that has been plagued SiC MOSFET. Therefore, how to improve the gate oxide strength of SiC MOSFET is a technical problem to be solved in this case. SUMMARY

[0004] In view of the above problems, the utility model provides a MOS device of higher gate protection effect which does not excessively affect the conduction performance of the device and improves the gate oxide strength of the device.

[0005] The technical scheme of the utility model is:

[0006] A MOS device of higher gate protection effect comprises SiC Sub layer, SiC Drift layer, ohmic contact alloy layer and front electrode metal layer arranged from bottom to top.

[0007] The SiC Drift layer is provided with:

[0008] P-body region, provided with a pair, respectively extended from the top surface of the SiC Drift layer downward;

[0009] NP region, provided with a pair of regions respectively extending downward from the top surface of the P-body region and having a spacing with the bottom surface of the P-body region;

[0010] PP region, provided with a pair of regions respectively extending downward from the top surface of the P-body region and connected with the NP region;

[0011] Gate oxide layer, provided with a pair of regions respectively located on the top surface of the SiC Drift layer, P-body region and NP region;

[0012] High-K dielectric, provided on the top surface of a pair of the gate oxide layer, and the bottom surface of the middle region is connected with the SiC Drift layer;

[0013] Poly layer, provided on the top surface of the gate oxide layer and high-K dielectric;

[0014] Isolation dielectric layer, provided on the Poly layer and extending downward to connect with the NP region.

[0015] The thickness of the SiC Sub layer is 120um-450um, and the thickness of the SiC Drift layer is 5um-15um.

[0016] Specifically, the depth of the P-body region is 0.5um-2um.

[0017] Specifically, the depth of the NP region is 0.2um-1.5um, and the doping concentration is 1E18-5E19cm -2 .

[0018] Specifically, the depth of the PP region is 0.2um-2um, and the doping concentration is 1E18-5E19cm -2 .

[0019] Specifically, the thickness of the gate oxide layer is 40nm-60um.

[0020] Specifically, the high-K dielectric material is Al2O3, TiO2, ZrO2 or HfO2.

[0021] This invention addresses the issue of gate oxide breakdown at the top surface of the JFET region in planar SiC MOSFET devices. It addresses this by fabricating a high-k dielectric material with a higher dielectric constant than SiO2 on the top surface of the SiC drift layer in the JFET region. These materials include Al2O3, TiO2, ZrO2, and HfO2. Since high-k dielectric materials are less prone to electrical breakdown, they significantly improve the gate oxide strength of the SiC MOSFET device, thereby enhancing its long-term stability. To prevent a decline in conduction performance after gate turn-on, a SiO2 gate oxide layer is placed above the channel region, which neither excessively affects the device's conduction performance nor compromises its gate oxide strength. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the structure of the SiC MOSFET of this utility model;

[0023] Figure 2 This is a structural schematic diagram of step S100 of this utility model;

[0024] Figure 3 This is a structural schematic diagram of step S200 of this utility model;

[0025] Figure 4 This is a structural schematic diagram of step S300 of this utility model;

[0026] Figure 5 This is a structural schematic diagram of step S400 of this utility model;

[0027] Figure 6 This is a structural schematic diagram of step S600 of this utility model;

[0028] Figure 7 This is a structural schematic diagram of step S700 of this utility model;

[0029] Figure 8 This is a structural schematic diagram of step S800 of this utility model;

[0030] Figure 9 This is a structural schematic diagram of step S900 of this utility model;

[0031] Figure 10 This is a structural schematic diagram of step S1000 of this utility model;

[0032] Figure 11 This is a structural schematic diagram of step S1100 of this utility model;

[0033] Fig. 1 is SiC Sub, 2 is SiC Drift, 3 is P-body region, 4 is NP region, 5 is PP region, 6 is gate oxide layer, 7 is high-K dielectric, 8 is Poly layer, 9 is isolation dielectric layer, 10 is ohmic contact alloy layer, 11 is front electrode metal layer. DETAILED DESCRIPTION

[0034] The utility model will be explained in detail below in combination with specific actual cases. The examples of the embodiments are shown in the drawings, and the illustrative embodiments of the utility model and the description thereof are only used to explain the utility model and do not limit the utility model.

[0035] A MOS device with higher gate protection effect, comprising the following steps:

[0036] S100, a SiC Drift layer 2 is formed on the top surface of the SiC Sub layer 1 by epitaxial deposition;

[0037] The thickness of the SiC Sub layer 1 in step S100 is 120um-450um, and the thickness of the SiC Drift layer 2 is 5um-15um.

[0038] S200, a P-body region 3 is formed on the top surface of the SiC Drift layer 2 by Al ion implantation;

[0039] The depth of the P-body region 3 in step S200 is 0.5um-2um, and the doping concentration is 1E17-5E18cm -2 .

[0040] S300, an NP region 4 is formed on the top surface of the P-body region 3 by N ion implantation;

[0041] The depth of the NP region 4 in step S300 is 0.2um-1.5um, and the doping concentration is 1E18-5E19cm -2 .

[0042] S400, a PP region 5 connected with the NP region 4 is formed on the top surface of the P-body region 3 by Al ion implantation;

[0043] The depth of the PP region 5 in step S400 is 0.2um-2um, and the doping concentration is 1E18-5E19cm -2 .

[0044] S500, the P-body region 3, the NP region 4 and the PP region 5 implantation region are activated by high-temperature annealing to form;

[0045] The high-temperature annealing condition in step S500 is 1600℃-1900℃.

[0046] S600, forming a gate oxide layer 6 on the top surface of the SiC Drift layer 2, the P-body region 3 and the NP region 4 by dry oxygen oxidation growth;

[0047] The thickness of the gate oxide layer 6 in step S600 is 40nm-60um.

[0048] S700, forming a high-K dielectric layer 7 (a material with a dielectric constant higher than that of the gate oxide layer 6) on the top surface of the SiC Drift layer 2 and the gate oxide layer 6 in the JFET region by deposition;

[0049] The material of the high-K dielectric layer 7 in step S700 is mainly metal oxide or alloy, such as Al2O3, TiO2, ZrO2 or HfO2, etc.

[0050] S800, forming a Poly layer 8 on the top surface of the gate oxide layer 6 and the high-K dielectric layer 7 by polysilicon deposition;

[0051] S900, forming an isolation dielectric layer 9 on the top surface of the NP region 4 and the Poly layer 8 by oxide deposition;

[0052] S1000, forming an ohmic contact alloy layer 10 on the top surface of the NP region 4 and the PP region 5 by Ni metal sputtering or deposition and then thermal annealing;

[0053] The thickness of the Ni metal in step S1000 is 0.3um-1um.

[0054] S1100, forming a front electrode metal layer 11 on the top surface of the isolation dielectric layer 9 and the ohmic contact alloy layer 10 by Ti and AlCu metal sputtering;

[0055] The thickness of the Ti metal in step S1100 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0056] A MOS device with higher gate protection, comprising a SiC Sub layer 1, a SiC Drift layer 2, an ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top;

[0057] The SiC Drift layer 2 is provided with:

[0058] A P-body region 3, provided with a pair, respectively extending downward from the top surface of the SiC Drift layer 2; a pair of P-body regions 3 form a JFET region between them;

[0059] An NP region 4, provided with a pair, respectively extending downward from the top surface of the P-body region 3, and provided with a spacing between the bottom surface of the P-body region 3;

[0060] PP region 5, provided with a pair, respectively from the top surface of the P-body region 3 downwardly extending, and the NP region 4 is connected; the bottom surface of the PP region 5 and the bottom surface of the P-body region 3 are provided with a spacing;

[0061] Gate oxide layer 6, provided with a pair, respectively located on the top surface of the SiC Drift layer 2, P-body region 3 and NP region 4;

[0062] High-K dielectric 7, provided on the top surface of a pair of the gate oxide layer 6, wherein the bottom surface of the middle region is connected with the SiC Drift layer 2;

[0063] Poly layer 8, provided on the top surface of the gate oxide layer 6 and high-K dielectric 7; the top edge is provided with a groove, because the middle bottom of the Poly layer 8 is high-K dielectric, the high-K dielectric is deposited to form, the thickness is thicker than the gate oxide layer 6, so the bottom of the Poly layer 8 is high in the middle and narrow on both sides, resulting in that the Poly layer 8 also forms a shape of high in the middle and narrow on both sides after deposition.

[0064] Isolation dielectric layer 9, provided on the Poly layer 8, and the side portion extends downwardly and is connected with the NP region 4.

[0065] The isolation dielectric layer 9 is connected with the front electrode metal layer 11 and the ohmic contact alloy layer 10 respectively on the outside, and is connected with the gate oxide layer 6 and the Poly layer 8 respectively on the inside.

[0066] The bottom surface of the ohmic contact alloy layer 10 is connected with the NP region 4 and the PP region 5 respectively.

[0067] The utility model discloses a layer of high-K dielectric material with higher dielectric constant than SiO2 is prepared on the top surface of the device JFET region SiC Drift layer, because the high dielectric constant material is more difficult to be subjected to electric breakdown, therefore high-K dielectric can better improve the gate oxide strength of the device. But because high-K dielectric cannot grow directly by oxidation like SiO2, can only be prepared by deposition, and in order to avoid the deterioration of the conduction performance of the device after the gate is opened, therefore still grows a layer of SiO2 gate oxide layer above the channel region, so that the conduction performance of the device is not affected too much, and the gate oxide strength of the device is improved.

Claims

1. A MOS device with higher gate protection, characterized in that, The SiC Sub layer (1), the SiC Drift layer (2), the ohmic contact alloy layer (10) and the front electrode metal layer (11) are sequentially arranged from bottom to top. The SiC Drift layer (2) is provided with: A pair of P-body regions (3) respectively extending downward from the top surface of the SiC Drift layer (2); A pair of NP regions (4) respectively extending downward from the top surface of the P-body region (3) and spaced apart from the bottom surface of the P-body region (3); A pair of PP regions (5) respectively extending downward from the top surface of the P-body region (3) and connected with the NP region (4); A pair of gate oxide layers (6) respectively located on the top surface of the SiC Drift layer (2), the P-body region (3) and the NP region (4); A high-K dielectric (7) provided on the top surface of the pair of gate oxide layers (6), wherein the bottom surface of the middle region is connected with the SiC Drift layer (2); A Poly layer (8) provided on the top surface of the gate oxide layer (6) and the high-K dielectric (7); An isolation dielectric layer (9) provided on the Poly layer (8) and extending downward on the side to be connected with the NP region (4); The thickness of the SiC Sub layer (1) is 120um-450um, and the thickness of the SiC Drift layer (2) is 5um-15um.

2. The MOS device with higher gate protection according to claim 1, wherein, The depth of the P-body region (3) is 0.5um-2um.

3. The MOS device with higher gate protection of claim 1, wherein, The thickness of the gate oxide layer (6) is 40nm-60um.

4. A MOS device with enhanced gate protection according to claim 1, characterized in that, The material of the high-K dielectric (7) is Al2O3, TiO2, ZrO2 or HfO2.

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