Mask for deposition

Abstract

A mask for deposition is provided. The mask for deposition includes: a mask frame having a cell opening; and a film including an inorganic layer disposed on the mask frame and a metal layer disposed on the inorganic layer. The film has a plurality of pixel openings communicating with the cell openings, and each of the pixel openings includes a first opening penetrating the metal layer and a second opening penetrating the inorganic material layer. The second opening portion has a width that increases toward the unit opening portion.

Description

TECHNICAL FIELD

[0001] The utility model relates to a deposition mask. BACKGROUND

[0002] Wearable devices are being developed that are developed in a glasses or helmet form and focus on a user's eye at a close distance. For example, the wearable device can be an HMD (head mounted display) device or AR glasses. These wearable devices can provide a user with an AR (augmented reality) screen or a VR (virtual reality) screen.

[0003] In the case of a wearable device such as an HMD device or AR glasses, in order for a user to be able to use it for a long time without experiencing dizziness, a display specification of approximately 3000 PPI (pixels per inch) or more is required, and for this reason, OLEDoS (Organic Light Emitting Diode on Silicon) technology, which is a small-sized organic light emitting display device with high resolution, is being developed. The OLEDoS technology is a technology that arranges an organic light emitting diode (OLED) on a semiconductor wafer on which a CMOS (Complementary Metal Oxide Semiconductor) element is arranged.

[0004] In order to manufacture a display panel with high resolution of approximately 3000 PPI or more, a deposition mask with high resolution is required. For example, the deposition mask can be manufactured by forming a membrane having a plurality of pixel opening portions on a substrate such as a silicon wafer, and partially etching the substrate to form a cell opening portion that exposes the pixel opening portion. The pixel opening portion of the membrane can be formed by an anisotropic etching process, and can have a lower width adjacent to the cell opening portion and an upper width wider than the lower width. In this case, in a deposition process for forming a light emitting layer of a display panel, the lower width of the pixel opening portion opposite to the deposition source can become narrower than the upper width of the pixel opening portion adjacent to the backplane substrate, and thus there is a problem in that the loss of a deposited substance can increase in the deposition process, and at the same time, the thickness and size of the light emitting layer become non-uniform. SUMMARY

[0005] TECHNICAL PROBLEM

[0006] The deposition mask and a method of manufacturing the same according to the present application provide a deposition mask having a structure in which a lower portion of a pixel opening portion is wider than an upper portion of the pixel opening portion.

[0007] The technical problems of the present application are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those skilled in the art from the following description.

[0008] Solution

[0009] The deposition mask according to an embodiment for solving the above technical problems can include a mask frame having a cell opening portion, and a film including an inorganic layer disposed on the mask frame and a metal layer disposed on the inorganic layer. The film can have a plurality of pixel opening portions communicating with the cell opening portion, each of the pixel opening portions can include a first opening portion penetrating the metal layer and a second opening portion penetrating the inorganic layer, and the second opening portion can have a width that increases toward the cell opening portion.

[0010] An inner side surface of the second opening portion can have a slope of about 30° to about 85° or so.

[0011] The film can have a thickness of about 0.1 μm to about 3.0 μm or so, and the metal layer can have a thickness of about 10 nm to about 100 nm or so.

[0012] A surface roughness (Ra) of the metal layer can be about 0.1 nm to about 1.0 nm or so.

[0013] The inorganic layer can include silicon nitride, and the metal layer can include chromium, tungsten, titanium, tantalum, or aluminum.

[0014] A portion of the inorganic layer located between the pixel opening portions can have a cross-sectional shape of an inverted trapezoidal form.

[0015] The inorganic layer can have a residual tensile stress, and the metal layer can have a residual compressive stress that is less than the residual tensile stress of the inorganic layer.

[0016] The deposition mask according to an embodiment for solving the above technical problems can include a mask frame having a cell opening portion and including a rim region defining the cell opening portion, and a film including a cell region disposed on the cell opening portion and a mesh region disposed on the rim region. The cell region can have a plurality of pixel opening portions communicating with the cell opening portion, and a thickness of the cell region can be less than a thickness of the mesh region.

[0017] The film can include an inorganic layer disposed on the mask frame. In this case, a portion of the inorganic layer located between the pixel opening portions can have a cross-sectional shape of an inverted triangular form. Each of the pixel opening portions can penetrate the inorganic layer and have a width that increases toward the cell opening portion. The inorganic layer can have a surface roughness (Ra) of about 0.1 nm to about 1.0 nm or so.

[0018] The film can include an inorganic layer disposed on the mask frame and a metal layer disposed on the inorganic layer. In this case, each of the pixel opening portions can include a first opening portion that penetrates the metal layer and a second opening portion that penetrates the inorganic layer, and the second opening portion can have a width that increases toward the cell opening portion.

[0019] A method of manufacturing a deposition mask according to an embodiment for solving the above technical problem can include: a step of forming an inorganic layer on a substrate; a step of forming a metal layer on the inorganic layer; a step of patterning the metal layer to form a plurality of first opening portions that expose the inorganic layer; a step of irradiating an ion beam onto the metal layer and the inorganic layer to form a plurality of second opening portions that expose the substrate; and a step of patterning the substrate to form a cell opening portion that communicates with the second opening portion, the second opening portion can be formed to have a width that increases toward the cell opening portion.

[0020] The inorganic layer can include silicon nitride, and the metal layer can include chromium, tungsten, titanium, tantalum, or aluminum.

[0021] The second opening portion can be formed by an ion beam etching process, a reactive ion beam etching process, or a chemical-assisted ion beam etching process.

[0022] The second opening portion can be formed to have an inclination of 30° to 85° on an inner side surface of each of the second opening portions.

[0023] The method of manufacturing the deposition mask can further include a step of removing the metal layer after the second opening portion is formed.

[0024] The method of manufacturing the deposition mask can further include a step of irradiating an ion beam onto the inorganic layer to improve a surface roughness of the inorganic layer after the inorganic layer is formed.

[0025] In the step of forming the second opening portion, a cavity connected to the second opening portion can be formed between the substrate and the inorganic layer by irradiation of the ion beam.

[0026] The specifics of other embodiments are included in the detailed description and drawings.

[0027] Advantages

[0028] According to the embodiment of the utility model as described above, the pixel opening part can have a width that increases toward the unit part opening, so the loss of the deposited substance in the deposition process of forming the light-emitting layer on the backplane substrate can be reduced, and the thickness and size of the light-emitting layer can be uniformly controlled.

[0029] The effects according to the embodiments are not limited to what is exemplified above, and more diverse effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a disassembled perspective view for illustrating a display device.

[0031] Figure 2 is a block diagram for illustrating Figure 1 the display device shown in FIG. 1.

[0032] Figure 3 is an equivalent circuit diagram for illustrating Figure 2 an example of the first sub-pixel shown in FIG. 1.

[0033] Figure 4 is a schematic plan view for illustrating Figure 1 an example of the display panel shown in FIG. 1.

[0034] Figure 5 is a schematic plan view for illustrating Figure 4 an example of the display region shown in FIG. 1.

[0035] Figure 6 is a schematic plan view for illustrating Figure 4 another example of the display region shown in FIG. 1.

[0036] Figure 7 is a cross-sectional view for illustrating Figure 5 an example of the display panel obtained along the line I-I' of FIG. 1.

[0037] Figure 8 is a schematic perspective view for illustrating a head-mounted display device.

[0038] Figure 9 is a schematic disassembled perspective view for illustrating Figure 8 an example of the head-mounted display device shown in FIG. 1.

[0039] Figure 10 is a schematic perspective view for illustrating another example of the head-mounted display device.

[0040] Figure 11is a schematic plan view for explaining a deposition mask according to an embodiment of the present application.

[0041] Figure 12 is a schematic plan view for explaining Figure 11 the unit region and the grid region shown in FIG. 2.

[0042] Figure 13 is a schematic cross-sectional view taken along Figure 12 the line II-II' shown in FIG. 2.

[0043] Figure 14 is a schematic cross-sectional view for explaining a deposition mask according to another embodiment of the present application.

[0044] Figure 15 is a schematic cross-sectional view for explaining a deposition mask according to still another embodiment of the present application.

[0045] Figure 16 is a schematic cross-sectional view for explaining a deposition mask according to still another embodiment of the present application.

[0046] Figure 17 is a schematic view for explaining a deposition apparatus including Figures 11 to 13 the deposition mask shown in FIG. 1.

[0047] Figures 18 to 24 is a schematic cross-sectional view for explaining a manufacturing method of a deposition mask according to still another embodiment of the present application.

[0048] Figure 25 and Figure 26 is a schematic cross-sectional view for explaining a manufacturing method of a deposition mask according to still another embodiment of the present application.

[0049] BRIEF DESCRIPTION OF THE DRAWINGS

[0050] 2000: deposition mask 2010: substrate

[0051] 2100: mask frame 2102: unit opening portion

[0052] 2104: rim region 2200: film

[0053] 2202: unit region 2204: grid region

[0054] 2210: inorganic layer 2220: metal layer

[0055] 2230: pixel opening portion 2232: first opening portion

[0056] 2234: second opening portion 2300: back surface inorganic layer

[0057] 2310: Back surface inorganic pattern layer Detailed Implementation

[0058] The advantages and features of this utility model, as well as the methods for achieving these advantages and features, will be described with reference to the following appendix. Figure 1 The invention becomes clear from the detailed description of the embodiments. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms that differ from each other. These embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the invention of its scope, and the present invention is defined only by the scope of the claims.

[0059] The term "on" when referring to an element or layer encompasses all cases where it is directly on top of another element or between another element or layer. Throughout this specification, the same reference numerals refer to the same constituent elements. The shapes, sizes, proportions, angles, quantities, etc., disclosed in the drawings used to illustrate embodiments are exemplary, and therefore, the present invention is not limited to what is shown.

[0060] Although terms like "first," "second," etc., are used to describe various constituent elements, these constituent elements are clearly not limited by these terms. These terms are only used to distinguish one constituent element from another. Therefore, the first constituent element mentioned below can obviously also be a second constituent element within the technical concept of this utility model.

[0061] The various features of the various embodiments of this utility model can be partially or completely combined or integrated with each other, and can be linked and driven in various ways in terms of technology. Furthermore, each embodiment can be implemented independently or jointly due to their related relationships.

[0062] The specific embodiments will now be described with reference to the accompanying drawings.

[0063] Figure 1 It is an exploded perspective view used to illustrate a display device. Figure 2 It is used for explanation Figure 1 Block diagram of the display device shown.

[0064] Reference Figure 1 and Figure 2The display device 10 can be a device that displays a dynamic image or a static image. The display device 10 can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet PC, a mobile communication terminal, an electronic notebook, an electronic book, a PMP, a navigator, a UMPC, or the like. For example, the display device 10 can be applied as a display portion of a television, a notebook, a monitor, a billboard, an IoT device. In addition, the display device 10 can be applied to a smart watch, a watch phone, a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0065] The display device 10 can include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit 400, and a power supply circuit 500.

[0066] The display panel 100 can be configured in a planar form similar to a quadrangle. For example, the display panel 100 can have a planar form similar to a quadrangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, an angle at which the short side in the first direction DR1 intersects the long side in the second direction DR2 can be formed in a circular shape to have a predetermined curvature or in a right angle. The planar form of the display panel 100 is not limited to a quadrangle, and can be formed similarly to other polygons, a circle, or an ellipse. The planar form of the display device 10 can follow the planar form of the display panel 100, but embodiments of the present specification are not limited thereto.

[0067] The display panel 100 can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driving portion 610, an emission driving portion 620, and a data driving portion 700. As shown in FIG. 1, the display panel 100 can be divided into a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed. Figure 3

[0068] ​A plurality of pixels PX can be arranged in the display region DAA. The plurality of pixels PX can be arranged in a matrix form along the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of light emission control lines EL can extend in the first direction DR1 and be arranged in the second direction DR2. A plurality of data lines DL can extend in the second direction DR2 and be arranged in the first direction DR1.

[0069] The plurality of scan lines SL can include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of light emission control lines EL can include a plurality of first light emission control lines EL1 and a plurality of second light emission control lines EL2.

[0070] The plurality of pixels PX can include a plurality of sub-pixels SP1, SP2, SP3. The plurality of sub-pixels SP1, SP2, SP3 can include a plurality of pixel transistors (refer to Figure 7 ). The plurality of pixel transistors can be formed by a semiconductor process and can be arranged in a semiconductor substrate SSUB (refer to Figure 7 ). For example, the plurality of pixel transistors of the data driving portion 700 can be formed by a CMOS (Complementary Metal Oxide Semiconductor) process, but embodiments of the present specification are not limited thereto.

[0071] Each of the plurality of sub-pixels SP1, SP2, SP3 can be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first light emission control lines EL1, any one of the plurality of second light emission control lines EL2, and any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, SP3 can receive a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and cause the light emitting element to emit light according to the data voltage.

[0072] The scan driving portion 610, the light emission driving portion 620, and the data driving portion 700 can be arranged in the non-display region NDA.

[0073] The scan driving portion 610 can include a plurality of scan transistors, and the light emission driving portion 620 can include a plurality of light emission transistors. The plurality of scan transistors and the plurality of light emission transistors can be formed in a semiconductor process and formed in a semiconductor substrate SSUB (refer to Figure 7For example, the plurality of scanning transistors and the plurality of light emitting transistors can be formed by a CMOS process, but embodiments of the present specification are not limited thereto.

[0074] The scan driving portion 610 can include a write scan signal output portion 611, a control scan signal output portion 612, and a bias scan signal output portion 613. Each of the write scan signal output portion 611, the control scan signal output portion 612, and the bias scan signal output portion 613 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output portion 611 can generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, thereby sequentially outputting the write scan signal to the write scan lines GWL. The control scan signal output portion 612 can generate a control scan signal according to the scan timing control signal SCS, thereby sequentially outputting the control scan signal to the control scan lines GCL. The bias scan signal output portion 613 can generate a bias scan signal according to the scan timing control signal SCS, thereby sequentially outputting the bias scan signal to the bias scan lines GBL.

[0075] The light emitting driving portion 620 includes a first light emitting control driving portion 621 and a second light emitting control driving portion 622. Each of the first light emitting control driving portion 621 and the second light emitting control driving portion 622 can receive a light emission timing control signal ECS from the timing control circuit 400. The first light emitting control driving portion 621 can generate a first light emitting control signal according to the light emission timing control signal ECS, thereby sequentially outputting the first light emitting control signal to the first light emitting control lines EL1. The second light emitting control driving portion 622 can generate a second light emitting control signal according to the light emission timing control signal ECS, thereby sequentially outputting the second light emitting control signal to the second light emitting control lines EL2.

[0076] The data driving portion 700 can include a plurality of data transistors, which can be formed in a semiconductor process and formed on a semiconductor substrate SSUB (refer to FIG. 1). Figure 4 For example, the plurality of data transistors can be formed by a CMOS process, but embodiments of the present specification are not limited thereto.

[0077] The data driving portion 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driving portion 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS to output to the data lines DL. In this case, the sub-pixels SP1, SP2, SP3 can be selected according to the write scan signal of the scan driving portion 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, SP3.

[0078] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, the back surface. The heat dissipation layer 200 serves to release heat generated in the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0079] The circuit board 300 can be electrically connected to the first pad portion PDA1 of the display panel 100 (see reference) using a conductive adhesive component such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (refer to) Figure 1 Circuit board 300 can be a flexible printed circuit board or a flexible film made of a flexible material. Figure 4 Although the example shows the circuit board 300 unfolded, the circuit board 300 can be bent. In this case, one end of the circuit board 300 can be disposed on the back surface of the display panel 100 and / or the back surface of the heat dissipation layer 200. The other end of the circuit board 300 can be connected to the first pad portion PDA1 of the display panel 100 (see reference) using a conductive adhesive member. Figure 4 Multiple first pads PD1 (refer to) Figure 3 One end of circuit board 300 can be the opposite end of the other end of circuit board 300.

[0080] The timing control circuit 400 can receive digital video data DATA and timing signals from an external source. Based on the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver unit 610 and the light emission timing control signal ECS to the light emission driver unit 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver unit 700.

[0081] The power supply circuit 500 can generate a plurality of panel driving voltages according to an external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and thereby supply the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT to the display panel 100. Descriptions for the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be made below in connection with Figure 7 .

[0082] The timing control circuit 400 and the power supply circuit 500 can be formed as integrated circuits (ICs) to be attached to a surface of the circuit board 300, respectively. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Also, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0083] As another example, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similar to the scan driving part 610, the emission driving part 620, and the data driving part 700. In this case, the timing control circuit 400 can include a plurality of timing transistors, and the power supply circuit 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed in a semiconductor process, and formed on a semiconductor substrate SSUB (refer to FIG. 1). For example, the plurality of timing transistors and the plurality of power transistors can be formed by a CMOS process, but embodiments of the present specification are not limited thereto. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed between the data driving part 700 and the first pad part PDA1 (refer to FIG. 1). Figure 4 Figure 3

[0084] Figure 2 is an equivalent circuit diagram for explaining an example of the first sub-pixel shown in FIG. 1. Figure 3

[0085] Refer to FIG. 1. Figure 3 ​​​The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first light emission control line EL1, the second light emission control line EL2, and the data line DL. Further, the first sub-pixel SP1 can be connected to the first drive voltage line VSL to which the first drive voltage VSS corresponding to a low potential voltage is applied, the second drive voltage line VDL to which the second drive voltage VDD corresponding to a high potential voltage is applied, and the third drive voltage line VIL to which the third drive voltage VINT corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. At this time, the first drive voltage VSS can be a voltage lower than the third drive voltage VINT. The second drive voltage VDD can be a voltage higher than the third drive voltage VINT.

[0086] The first sub-pixel SP1 can include a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0087] The light emitting element LE emits light as a drive current flows in a channel of the first transistor T1. An amount of light emission of the light emitting element LE can be proportional to the drive current. The light emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but embodiments of the present specification are not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0088] The first transistor T1 can be a drive transistor that controls a source-drain current (hereinafter referred to as a "drive current") flowing between a source electrode and a drain electrode according to a voltage applied to a gate electrode. The first transistor T1 can include a gate electrode connected to the first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0089] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL, thereby connecting one electrode of the first capacitor CP1 to the data line DL. Accordingly, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 can include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0090] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a write control signal of the control scan line GCL, thereby connecting the first node N1 to the second node N2. Accordingly, the first transistor T1 can operate like a diode when the gate electrode and the drain electrode of the first transistor T1 are connected. The third transistor T3 can include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0091] The fourth transistor T4 can be turned on between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first light emitting control signal of the first light emitting control line EL1, thereby connecting the second node N2 to the third node N3. Accordingly, the driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 can include a gate electrode connected to the first light emitting control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0092] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by a bias scan signal of the bias scan line GBL, thereby connecting the third node N3 to the third driving voltage line VIL. Accordingly, the first electrode of the light emitting element LE can be applied with the third driving voltage VINT of the third driving voltage line VIL. The fifth transistor T5 can include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0093] The sixth transistor T6 can be arranged between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second light emission control signal of the second light emission control line EL2, thereby connecting the source electrode of the first transistor T1 to the second drive voltage line VDL. Thus, the second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 can include a gate electrode connected to the second light emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0094] The first capacitor CP1 can be arranged between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 can include one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0095] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 can include one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second drive voltage line VDL.

[0096] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0097] Each of the first transistor T1 to the sixth transistor T6 can be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but embodiments of the present specification are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, in the first transistor T1 to the sixth transistor T6, each of a part of the transistors can be a P-type MOSFET, and each of the remaining transistors can be an N-type MOSFET.

[0098] In Figure 3 Although it is exemplified that the first sub-pixel SP1 includes the six transistors T1 to T6 and the two capacitors C1, C2 in the equivalent circuit diagram of FIG. 1, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to Figure 3The number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to those shown in the equivalent circuit diagram. Figure 3 The number of transistors and the number of capacitors of the second sub-pixel SP2 and the third sub-pixel SP3 are not limited to those shown in the equivalent circuit diagram.

[0099] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in conjunction with Figure 4 The description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 is omitted in the present specification.

[0100] Figure 1 is a schematic plan view of an example of the display panel shown in Figure 4

[0101] Referring to Figure 4 The display region DAA of the display panel 100 can include a plurality of pixels PX arranged in a matrix form. The non-display region NDA of the display panel 100 can include a scan driving portion 610, a light-emitting driving portion 620, a data driving portion 700, a first pad portion PDA1, and a second pad portion PDA2.

[0102] The scan driving portion 610 can be disposed at a first side of the display region DAA, and the light-emitting driving portion 620 can be disposed at a second side of the display region DAA. For example, the scan driving portion 610 can be disposed at one side of the display region DAA in a first direction DR1, and the light-emitting driving portion 620 can be disposed at the other side of the display region DAA in the first direction DR1. That is, as shown in Figure 4 The scan driving portion 610 can be disposed at a first side of the display region DAA, and the light-emitting driving portion 620 can be disposed at a second side of the display region DAA. For example, the scan driving portion 610 can be disposed at one side of the display region DAA in a first direction DR1, and the light-emitting driving portion 620 can be disposed at the other side of the display region DAA in the first direction DR1. That is, as shown in

[0103] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 through conductive adhesive members. The first pad portion PDA1 can be disposed at a third side of the display region DAA. For example, the first pad portion PDA1 can be disposed at one side of the display region DAA in a second direction DR2. The first pad portion PDA1 can be disposed outside the data driving portion 700 in the second direction DR2. That is, as shown in Figure 4 The first pad portion PDA1 can be disposed closer to an edge of the display panel 100 than the data driving portion 700.

[0104] ​The second pad section PDA2 may include multiple second pads PD2, which are equivalent to inspection pads for checking whether the display panel 100 is functioning properly. The multiple second pads PD2 may be connected to a fixture or probe during the inspection process, or connected to an inspection circuit board. The inspection circuit board may be a rigid printed circuit board or a flexible printed circuit board with a flexible material.

[0105] The second pad portion PDA2 can be arranged on the fourth side of the display area DAA. For example, the second pad portion PDA2 can be arranged on the other side of the display area DAA in the second direction DR2. The second pad portion PDA2 can be arranged on the outside of the second distribution circuit 720 in the second direction DR2. That is, as... Figure 4 As shown, the second pad portion PDA2 can be arranged closer to the edge of the display panel 100 than the second distribution circuit 720.

[0106] The first distribution circuit 710 distributes the data voltage applied through the first pad portion PDA1 to multiple data lines DL. For example, the first distribution circuit 710 can distribute the data voltage applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL, thus reducing the number of multiple first pads PD1. The first distribution circuit 710 can be arranged on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be arranged on one side of the display area DAA in the second direction DR2. That is, as Figure 4 As shown, the first distribution circuit 710 can be arranged on the lower side of the display area DAA.

[0107] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan drive unit 610, the light emission drive unit 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each pixel PX in the display area DAA. The second distribution circuit 720 can be arranged on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be arranged on the other side of the display area DAA in the second direction DR2. That is, as... Figure 5 As shown, the second distribution circuit 720 can be arranged on the upper side of the display area DAA.

[0108] Figure 4 It is used for explanation Figure 6 A schematic floor plan of an example of the display area shown. Figure 4 It is used for explanation Figure 5 A schematic floor plan of another example of the display area shown.

[0109] Referring to Figure 7 Each of the plurality of pixels PX can include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can include light emitting areas EA1, EA2, EA3, respectively. For example, the first sub-pixel SP1 can include a first light emitting area EA1, the second sub-pixel SP2 can include a second light emitting area EA2, and the third sub-pixel SP3 can include a third light emitting area EA3.

[0110] Each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can be an area defined by a pixel defining film PDL (refer to Figure 7 ). For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can be an area defined by a first pixel defining film PDL1 (refer to Figure 6 ).

[0111] A length of the third light emitting area EA3 in the first direction DR1 can be less than a length of the first light emitting area EA1 in the first direction DR1 and a length of the second light emitting area EA2 in the first direction DR1. The length of the first light emitting area EA1 in the first direction DR1 can be substantially the same as the length of the second light emitting area EA2 in the first direction DR1.

[0112] A length of the third light emitting area EA3 in the second direction DR2 can be longer than a length of the first light emitting area EA1 in the second direction DR2 and a length of the second light emitting area EA2 in the second direction DR2. The length of the first light emitting area EA1 in the second direction DR2 can be longer than the length of the second light emitting area EA2 in the second direction DR2.

[0113] In each of the plurality of pixels PX, the first light emitting area EA1 and the second light emitting area EA2 can be adjacent in the second direction DR2. Also, the first light emitting area EA1 and the third light emitting area EA3 can be adjacent in the first direction DR1. Also, the second light emitting area EA2 and the third light emitting area EA3 can be adjacent in the first direction DR1. Areas of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can be different from each other.

[0114] The first light emitting region EA1 can emit light of a first color, the second light emitting region EA2 can emit light of a second color, and the third light emitting region EA3 can emit light of a third color. Here, the light of the first color can be light of a red color band, the light of the second color can be light of a green color band, and the light of the third color can be light of a blue color band. For example, the blue color band can refer to a band in which a main peak wavelength of light is included in a band of approximately 370 nm to 460 nm, the green color band can refer to a band in which a main peak wavelength of light is included in a band of approximately 480 nm to 560 nm, and the red color band can refer to a band in which a main peak wavelength of light is included in a band of approximately 600 nm to 750 nm.

[0115] As another example, as illustrated in FIG. 1B, the first light emitting region EA1, the second light emitting region EA2, and the third light emitting region EA3 can be arranged in a hexagonal structure having a planar form of a hexagon. In this case, the first light emitting region EA1 and the second light emitting region EA2 can be adjacent in a first direction DR1, the second light emitting region EA2 and the third light emitting region EA3 can be adjacent in a first diagonal direction DD1, and the first light emitting region EA1 and the third light emitting region EA3 can be adjacent in a second diagonal direction DD2. Figure 5

[0116] In Figure 6 and Figure 5 , although it is illustrated that each of the plurality of pixels PX includes three light emitting regions EA1, EA2, and EA3, it is not limited thereto. That is, each of the plurality of pixels PX can include four light emitting regions. Further, each of the light emitting regions EA1, EA2, and EA3 can have a planar form of a polygon, a circle, an ellipse, or a special shape, which is different from that illustrated in Figure 6 and Figure 5 .

[0117] The arrangement of the light emitting regions EA1, EA2, and EA3 of the plurality of pixels PX is not limited to the arrangement illustrated in Figure 6 and Figure 7 . For example, the light emitting regions of the plurality of pixels PX can be arranged in a stripe structure in which the light emitting regions are arranged in the first direction DR1, a PenTile structure in which the light emitting regions have a diamond arrangement, or the like.

[0118] Figure 5 is a cross-sectional view for explaining an example of a display panel obtained along the I-I' line of Figure 7 .

[0119] Referring to Figure 3 ​The display panel 100 can include a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an adhesive layer APL, a cover layer CVL, and a polarizing plate POL.

[0120] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be junction Figure 4 The first to sixth transistors T1 to T6 are described.

[0121] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type impurity. A plurality of well regions WA can be arranged on an upper surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type impurity. The second type impurity can be different from the aforementioned first type impurity. For example, when the first type impurity is a p-type impurity, the second type impurity can be an n-type impurity. Alternatively, when the first type impurity is an n-type impurity, the second type impurity can be a p-type impurity.

[0122] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH arranged between the source region SA and the drain region DA.

[0123] A lower insulating film BINS can be arranged between the gate electrode GE and the well region WA. A side surface insulating film SINS can be arranged on a side surface of the gate electrode GE. The side surface insulating film SINS can be arranged on the lower insulating film BINS.

[0124] Each of the source region SA and the drain region DA can be a region doped with a first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be arranged on one side of the gate electrode GE, and the drain region DA can be arranged on the other side of the gate electrode GE.

[0125] Each of the plurality of well regions WA can further include a first low-concentration impurity region LDD1 arranged between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 arranged between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA. By the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, a distance between the source region SA and the drain region DA can be increased. Thus, since a length of the channel region CH of each of the pixel transistors PTR can be increased, punch-through and hot carrier phenomena due to a short channel can be prevented.

[0126] The first semiconductor insulating film SINS1 can be arranged on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed of an inorganic film of a silicon carbon nitride (SiCN) or a silicon oxide (SiO x ) type, but embodiments of the present specification are not limited thereto.

[0127] The second semiconductor insulating film SINS2 can be arranged on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed of an inorganic film of a silicon oxide (SiO x ) type, but embodiments of the present specification are not limited thereto.

[0128] The plurality of contact terminals CTE can be arranged on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a contact plug penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

[0129] A third semiconductor insulating film SINS3 can be arranged on a side surface of each of the plurality of contact terminals CTE. An upper surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed of an inorganic film of a silicon oxide (SiO x ) type, but embodiments of the present specification are not limited thereto.

[0130] The semiconductor substrate Ssub can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors can be arranged on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that is not bent, and the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0131] The light emitting element back plate EBP can include a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9. The plurality of insulating films INS1 to INS9 can be used to electrically insulate between the plurality of conductive layers ML1 to ML8.

[0132] The first conductive layer ML1 to the eighth conductive layer ML8 are connected to the plurality of contact terminals CTE exposed from the semiconductor back plate SBP, and function to realize Figure 7 the circuit of the first sub-pixel SP1 illustrated. For example, in a case where only the first transistor T1 to the sixth transistor T6 are formed on the semiconductor back plate SBP, the connection of the first transistor T1 to the sixth transistor T6 and the first capacitor C1 and the second capacitor C2 can be realized by the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4 and the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode AND of the light emitting element LE can also be realized by the first conductive layer ML1 to the eighth conductive layer ML8.

[0133] The first insulating film INS1 can be arranged on the semiconductor back plate SBP. Each of the first vias VA1 can be connected to the contact terminal CTE exposed from the semiconductor back plate SBP through the first insulating film INS1. Each of the first conductive layer ML1 can be arranged on the first insulating film INS1 and connected to the first via VA1.

[0134] The second insulating film INS2 can be arranged on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can be connected to the first conductive layer ML1 through the second insulating film INS2. Each of the second conductive layer ML2 can be arranged on the second insulating film INS2 and connected to the second via VA2.

[0135] The third insulating film INS3 can be arranged on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can be connected to the second conductive layer ML2 through the third insulating film INS3. Each of the third conductive layer ML3 can be arranged on the third insulating film INS3 and connected to the third via VA3.

[0136] The fourth insulating film INS4 can be arranged on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 can be connected to the third conductive layer ML3 through the fourth insulating film INS4. Each of the fourth conductive layers ML4 can be arranged on the fourth insulating film INS4 and connected to the fourth via VA4.

[0137] The fifth insulating film INS5 can be arranged on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 can be connected to the fourth conductive layer ML4 through the fifth insulating film INS5. Each of the fifth conductive layers ML5 can be arranged on the fifth insulating film INS5 and connected to the fifth via VA5.

[0138] The sixth insulating film INS6 can be arranged on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 can be connected to the fifth conductive layer ML5 through the sixth insulating film INS6. Each of the sixth conductive layers ML6 can be arranged on the sixth insulating film INS6 and connected to the sixth via VA6.

[0139] The seventh insulating film INS7 can be arranged on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 can be connected to the sixth conductive layer ML6 through the seventh insulating film INS7. Each of the seventh conductive layers ML7 can be arranged on the seventh insulating film INS7 and connected to the seventh via VA7.

[0140] The eighth insulating film INS8 can be arranged on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 can be connected to the seventh conductive layer ML7 through the eighth insulating film INS8. Each of the eighth conductive layers ML8 can be arranged on the eighth insulating film INS8 and connected to the eighth via VA8.

[0141] The first to eighth conductive layers ML1 to ML8 can be composed of substantially the same substance. The first to eighth conductive layers ML1 to ML8 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first to eighth vias VA1 to VA8 can be composed of substantially the same substance. The first to eighth vias VA1 to VA8 can be composed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first to eighth insulating films INS1 to INS8 can be formed of an inorganic film of a silicon oxide (SiO x ) class, but embodiments of the present specification are not limited thereto.

[0142] Each of the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. Each of the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be about 10 nm to about 100 nm, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be about 10 nm to about 50 nm, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 can be about 10 nm to about 50 nm. Each of the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be about 10 nm to about 50 nm. Each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 can be about 10 nm to about 50 nm.

[0143] Each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than each of the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. Each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be greater than each of the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, each of the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be about 10 nm to about 50 nm. Each of the thickness of the seventh via VA7 and the thickness of the eighth via VA8 can be about 10 nm to about 50 nm.

[0144] The ninth insulating film INS9 can be arranged on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of an inorganic film of a silicon oxide (SiO x ) class, but embodiments of the present specification are not limited thereto.

[0145] Each of the ninth vias VA9 can be connected to the eighth conductive layer ML8 through the ninth insulating film INS9. The ninth via VA9 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. The thickness of the ninth via VA9 can be about 100 nm to 1,000 nm.

[0146] The display element layer EML can be arranged on the light emitting element back plate EBP. The display element layer EML can include a reflective electrode layer RL, a tenth insulating film INS10, a tenth via VA10, a light emitting element LE, and a pixel definition film PDL. The light emitting element LE can include a first electrode AND, a light emitting stack ES, and a second electrode CAT, respectively.

[0147] The reflective electrode layer RL can be arranged on the ninth insulating film INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, RL4, a first step layer STPL1, and a second step layer STPL2. For example, as shown in FIG. 1, the reflective electrode layer RL can include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4. Figure 8

[0148] Each of the first reflective electrode RL1 can be arranged on the ninth insulating film INS9 and connected to the ninth via VA9. The first reflective electrode RL1 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. For example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0149] Each of the second reflective electrode RL2 can be arranged on the first reflective electrode RL1. The second reflective electrode RL2 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. For example, the second reflective electrode RL2 can include aluminum (Al).

[0150] ​In the second sub-pixel SP2 and the third sub-pixel SP3, the first step layer STPL1 can be disposed on the second reflective electrode RL2. In the first sub-pixel SP1, the first step layer STPL1 can not be disposed on the second reflective electrode RL2.

[0151] In the third sub-pixel SP3, the second step layer STPL2 can be disposed on the first step layer STPL1. In the first sub-pixel SP1, the second step layer STPL2 can not be disposed on the second reflective electrode RL2. Further, in the second sub-pixel SP2, the second step layer STPL2 can not be disposed on the first step layer STPL1.

[0152] The thickness of the first step layer STPL1 can be set by considering the wavelength of the light of the second color and the distance from the light-emitting stack ES to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the second color emitted from the light-emitting stack ES of the second sub-pixel SP2. The thickness of the second step layer STPL2 can be set by considering the wavelength of the light of the third color and the distance from the light-emitting stack ES to the fourth reflective electrode RL4, so as to facilitate reflection of the light of the third color emitted from the light-emitting stack ES of the third sub-pixel SP3.

[0153] The first step layer STPL1 and the second step layer STPL2 can be formed of an inorganic film of a carbon silicon nitride (SiCN) or a silicon oxide (SiO x ) class, but embodiments of the present specification are not limited thereto.

[0154] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the second sub-pixel SP2, the third reflective electrode RL3 can be disposed on the first step layer STPL1 and the second reflective electrode RL2. In the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the second step layer STPL2 and the second reflective electrode RL2. The third reflective electrode RL3 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. For example, the third reflective electrode RL3 can include titanium nitride (TiN).

[0155] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 can be omitted.

[0156] Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 can be a layer that reflects light from the light emitting stack ES. The fourth reflective electrode RL4 can include a metal having a high reflectance to facilitate reflection of light. Also, since the fourth reflective electrode RL4 is an electrode that substantially reflects light from the light emitting element LE, the thickness of the fourth reflective electrode RL4 can be greater than the thickness of the first reflective electrode RL1, the thickness of the second reflective electrode RL2, and the thickness of the third reflective electrode RL3. The fourth reflective electrode RL4 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the fourth reflective electrode RL4 can include aluminum (Al) or titanium (Ti).

[0157] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9 and the fourth reflective electrode RL4. The tenth insulating film INS10 can be an optical auxiliary layer through which light reflected at the reflective electrode layer RL from light emitted from the light emitting element LE passes. The tenth insulating film INS10 can be formed of an inorganic film of a silicon oxide (SiO x ) class, but embodiments of the present specification are not limited thereto.

[0158] Each of the tenth vias VA10 can be connected to the reflective electrode layer RL through the tenth insulating film INS10. The tenth via VA10 can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0159] In order for a resonance distance of light emitted from the light emitting element LE to match in at least any one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the tenth via VA10 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be different. For example, the thickness of the tenth via VA10 in the third sub-pixel SP3 can be less than the thickness of the tenth via VA10 in each of the first sub-pixel SP1 and the second sub-pixel SP2. Also, the thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the first sub-pixel SP1. That is, the distance between the light emitting stack ES and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0160] In summary, in order to adjust the distance between the light-emitting stack ES and the reflective electrode layer RL according to the principal wavelength of light emitted from the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the first step layer STPL1 and the second step layer STPL2 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 and the thickness of each of the first step layer STPL1 and the second step layer STPL2 can be set.

[0161] The first electrode AND of each of the light-emitting elements LE can be arranged on the tenth insulating film INS10 and connected to the tenth via hole VA10. The first electrode AND of each of the light-emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE can be composed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the first electrode AND of each of the light-emitting elements LE can be titanium nitride (TiN).

[0162] The pixel definition film PDL can be arranged on a part of the region of the first electrode AND of each of the light-emitting elements LE and the tenth insulating film INS10. The pixel definition film PDL can cover the edge of the first electrode AND of each of the light-emitting elements LE. The pixel definition film PDL functions to divide the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. That is, the pixel definition film PDL can have an opening that partially exposes the first electrode AND of each of the light-emitting elements LE.

[0163] The first light-emitting region EA1 can be defined as a region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the first sub-pixel SP1. The second light-emitting region EA2 can be defined as a region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the second sub-pixel SP2. The third light-emitting region EA3 can be defined as a region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked to emit light in the third sub-pixel SP3.

[0164] The pixel definition film PDL can include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 can be arranged on the first electrode AND and the tenth insulating film INS10 of each of the light emitting elements LE, the second pixel definition film PDL2 can be arranged on the first pixel definition film PDL1, and the third pixel definition film PDL3 can be arranged on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can be formed of an inorganic film of a silicon oxide (SiO x ) class, but embodiments of the present specification are not limited thereto. Each of a thickness of the first pixel definition film PDL1, a thickness of the second pixel definition film PDL2, and a thickness of the third pixel definition film PDL3 can be about 100 nm to 300 nm.

[0165] When the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, a height of the one pixel definition film becomes high, and thus the first encapsulation inorganic film TFE1 can be disconnected due to step coverage. The step coverage refers to a ratio of a degree to which a thin film is coated on an inclined portion to a degree to which the thin film is coated on a flat portion. The lower the step coverage, the higher the possibility that the thin film is disconnected at the inclined portion.

[0166] Therefore, in order to prevent the first encapsulation inorganic film TFE1 from being disconnected due to the step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having steps in a stepped form. For example, a width of an opening of the first pixel definition film PDL1 can be smaller than a width of an opening of the second pixel definition film PDL2, and a width of an opening of the second pixel definition film PDL2 can be smaller than a width of an opening of the third pixel definition film PDL3.

[0167] The light emitting stack ES can include a first light emitting stack ES1 disposed within the first light emitting area EA1, a second light emitting stack ES2 disposed within the second light emitting area EA2, and a third light emitting stack ES3 disposed within the third light emitting area EA3. Although not shown in detail, the first light emitting stack ES1 can include a hole injection layer (HIL), a hole transport layer (HTL), a first light emitting layer (EML1), an electron transport layer (ETL), and an electron injection layer (EIL), the second light emitting stack ES2 can include a hole injection layer (HIL), a hole transport layer (HTL), a second light emitting layer (EML2), an electron transport layer (ETL), and an electron injection layer (EIL), and the third light emitting stack ES3 can include a hole injection layer (HIL), a hole transport layer (HTL), a third light emitting layer (EML3), an electron transport layer (ETL), and an electron injection layer (EIL).

[0168] For example, the hole injection layer (HIL) can be disposed on the first electrode AND exposed through the opening of the pixel defining film PDL, the inner surface of the opening of the pixel defining film PDL, and the upper surface of the pixel defining film PDL. The hole transport layer (HTL) can be disposed on the hole injection layer (HIL).

[0169] The first light emitting layer (EML1), the second light emitting layer (EML2), and the third light emitting layer (EML3) can be respectively disposed within the opening of the pixel defining film PDL on the hole transport layer (HTL). The first light emitting layer (EML1) can be disposed within the opening of the pixel defining film PDL in the first light emitting area EA1, and can emit light of a first color, for example, red light. The second light emitting layer (EML2) can be disposed within the opening of the pixel defining film PDL in the second light emitting area EA2, and can emit light of a second color, for example, green light. The third light emitting layer (EML3) can be disposed within the opening of the pixel defining film PDL in the third light emitting area EA3, and can emit light of a third color, for example, blue light.

[0170] The electron transport layer (ETL) can be disposed on the first light emitting layer (EML1), the second light emitting layer (EML2), and the third light emitting layer (EML3), and the hole transport layer (HTL), and the electron injection layer (EIL) can be disposed on the electron transport layer (ETL).

[0171] As another example, although not shown, a plurality of trenches (not shown) can be arranged between the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The trenches can have a ring shape surrounding the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively, and can be formed to penetrate the pixel definition film PDL. A hole injection layer (HIL) and a hole transport layer (HTL) formed on the first electrode AND of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 can be insulated from each other by the trenches.

[0172] As still another example, the first light emitting stack ES1, the second light emitting stack ES2, and the third light emitting stack ES3 can be arranged within the openings of the pixel definition film PDL, and can not be arranged on the pixel definition film PDL. In this case, the first light emitting stack ES1, the second light emitting stack ES2, and the third light emitting stack ES3 can be insulated from each other by the pixel definition film PDL.

[0173] The second electrode CAT can be arranged on the first light emitting stack ES1, the second light emitting stack ES2, and the third light emitting stack ES3. The second electrode CAT can be formed of a transparent conductive material (TCO, Transparent Conductive Material) such as ITO, IZO, or the like, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag), which is capable of transmitting light. When the second electrode CAT is formed of the semi-transmissive conductive material, light emission efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be increased due to micro cavity.

[0174] The encapsulation layer TFE can be arranged on the display element layer EML. To prevent oxygen or moisture from penetrating into the display element layer EML, the encapsulation layer TFE can include at least one inorganic film TFE1, TFE2. For example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0175] The first encapsulation inorganic film TFE1 can be arranged on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed as a multi-film in which one or more inorganic films of silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ) are alternately stacked. The first encapsulation inorganic film TFE1 can be formed by a chemical evaporation deposition (CVD) process.

[0176] A second encapsulation inorganic film TFE2 can be disposed on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but embodiments of the present specification are not limited thereto. The second encapsulation inorganic film TFE2 can be formed through an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0177] The adhesive layer APL can be a layer for improving the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The adhesive layer APL can be an organic film of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0178] The cover layer CVL can be disposed on the adhesive layer APL. The cover layer CVL can be a glass substrate or a polymer resin such as a resin. When the cover layer CVL is a glass substrate, the cover layer CVL can be attached on the adhesive layer APL and can function as an encapsulation substrate. When the cover layer CVL is a polymer resin such as a resin, the cover layer CVL can be directly coated on the adhesive layer APL.

[0179] The polarizing plate POL can be disposed on the cover layer CVL. The polarizing plate POL can be a structure for preventing a decrease in visibility due to reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate, but embodiments of the present specification are not limited thereto.

[0180] Figure 9 is a schematic perspective view for explaining a head-mounted display device. Figure 8 is a schematic exploded perspective view for explaining an example of the head-mounted display device shown in Figure 8 .

[0181] Referring to Figure 9 and Figure 1 , the head-mounted display device 1000 according to an embodiment can include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eye lens 1210, a second eye lens 1220, a head mounting band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0182] The first display device 10_1 can provide an image to the left eye of the user, and the second display device 10_2 can provide an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figure 2 and Figure 8 The first display device 10_1 and the second display device 10_2 are substantially the same as the display device 10 described above, so the description of the first display device 10_1 and the second display device 10_2 is omitted.

[0183] The first optical member 1510 can be disposed between the first display device 10_1 and the first eye lens 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eye lens 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0184] The intermediate frame 1400 can be disposed between the first display device 10_1 and the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 functions to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0185] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA, and can transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connector.

[0186] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0187] The display device housing 1100 functions to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed to cover one side of the display device housing 1100. The housing cover 1200 can include the first eye lens 1210 disposed for the left eye of the user and the second eye lens 1220 disposed for the right eye of the user. Figure 9 andFigure 10 Although the first eye lens 1210 and the second eye lens 1220 are separately arranged as an example, embodiments of the present specification are not limited thereto. The first eye lens 1210 and the second eye lens 1220 can be combined into one.

[0188] The first eye lens 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eye lens 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can see the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eye lens 1210, and can see the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eye lens 1220.

[0189] The head mounting band 1300 functions to fix the display device housing 1100 to the head of the user to be able to maintain the state in which the first eye lens 1210 and the second eye lens 1220 of the housing cover 1200 are arranged to the left eye and the right eye of the user, respectively. When the display device housing 1100 is implemented to be small and light, the head-mounted display device 1000 can be provided in a glasses form as Figure 10 indicated.

[0190] In addition, the head-mounted display device 1000 can further have a battery for supplying a power source, an external memory slot capable of housing an external memory, and an external connection port for receiving an image source and a wireless communication module. The external connection port can be a universal serial bus (USB) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0191] Figure 10 is a schematic perspective view for explaining another example of a head-mounted display device.

[0192] Referring to Figure 10 , the head-mounted display device 1000_1 can be a display device in a glasses form in which the display device housing 1200_1 is implemented to be small and light. The head-mounted display device 1000_1 can have a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, glasses frame legs 1040, 1050, an optical member 1060, an optical path conversion member 1070, and the display device housing 1200_1.

[0193] The display device housing portion 1200_1 can include the display device 10_3, the optical member 1060, and the optical path conversion member 1070. An image displayed by the display device 10_3 can be enlarged by the optical member 1060, and the optical path is converted by the optical path conversion member 1070, so that the image is provided to the right eye of the user through the right-eye lens 1020. Thus, the user can view an augmented reality image in which a virtual image displayed by the display device 10_3 is synthesized with a real image seen through the right-eye lens 1020 through the right eye.

[0194] In Figure 11 , although the display device housing portion 1200_1 is illustrated as being arranged at the right end of the support frame 1030, embodiments of the present specification are not limited thereto. For example, the display device housing portion 1200_1 can be arranged at the left end of the support frame 1030, in which case an image of the display device 10_3 can be provided to the left eye of the user. As another example, the display device housing portion 1200_1 can be arranged at both the left end and the right end of the support frame 1030, in which case the user can view an image displayed by the display device 10_3 through both the left eye and the right eye.

[0195] Figure 12 is a schematic plan view for explaining a deposition mask according to an embodiment of the present application. Figure 11 is a schematic plan view for explaining Figure 13 a unit region and a grid region illustrated in FIG. 1. Figure 12 is a schematic cross-sectional view taken along Figures 11 to 13 line II-II' illustrated in FIG. 1.

[0196] Referring to Figure 7 , the deposition mask 2000 according to an embodiment of the present application can be used as a shadow mask in a deposition process for forming a light-emitting layer of a light-emitting stack ES (refer to Figure 11 ).

[0197] The deposition mask 2000 can include a mask frame 2100 and a film 2200 arranged on the mask frame 2100. The mask frame 2100 can include a unit opening portion 2102 having a rim region 2104 defining the unit opening portion 2102. The film 2200 can include a unit region 2202 arranged on the unit opening portion 2102 and a grid region 2204 arranged on the rim region 2104.

[0198] For example, as Figure 13As shown, the film 2200 can include a plurality of unit regions 2202 arranged in a matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, and a grid region 2204 arranged between the unit regions 2202. For example, the second direction DR2 can be a direction perpendicular to the first direction DR1. However, since the number and arrangement direction of the unit regions 2202 can be variously changed, the scope of the present application is not limited thereto.

[0199] The mask frame 2100 can have a plurality of unit opening portions 2102 respectively exposing the unit regions 2202 of the film 2200, and can include a rim region 2104 defining the unit opening portions 2102. The rim region 2104 of the mask frame 2100 can be configured to surround the unit opening portions 2102, and the grid region 2204 of the film 2200 can be configured to surround the unit regions 2202. The unit regions 2202 of the film 2200 can be respectively arranged on the unit opening portions 2102 of the mask frame 2100, and the grid region 2204 of the film 2200 can be arranged on the rim region 2104 of the mask frame 2100.

[0200] The film 2200 can include an inorganic layer 2210 arranged on the mask frame 2100 and a metal layer 2220 arranged on the inorganic layer 2210. Each of the unit regions 2202 of the film 2200 can have a plurality of pixel opening portions 2230. The plurality of pixel opening portions 2230 can be formed to penetrate each of the unit regions 2202. That is, as shown, the pixel opening portions 2230 of the film 2200 can be connected to the unit opening portions 2102 of the mask frame 2100 through the metal layer 2220 and the inorganic layer 2210. The unit opening portions 2102 of the mask frame 2100 and the pixel opening portions 2230 of the film 2200 can function as a path for providing a light emitting substance to an anode electrode of the back panel substrate 3002 in a deposition process for forming a light emitting layer on the back panel substrate 3002 (refer to FIG. 3). Figure 17 Figure 12 Figure 18 As shown, the pixel opening portions 2230 of the film 2200 can be arranged in a matrix form along the first direction DR1 and the second direction DR2.

[0201] ​​A rear surface inorganic pattern layer 2310 can be disposed on the rear surface of the mask frame 2100, which is opposite to the front surface of the mask frame 2100 on which the film 2200 is disposed. The rear surface inorganic pattern layer 2310 can be used as an etching mask in the etching process for forming the unit opening 2102, and can be made of the same material as the inorganic layer 2210 of the film 2200. For example, the inorganic layer 2210 of the film 2200 and the rear surface inorganic pattern layer 2310 can be formed simultaneously by a thermal chemical vapor deposition (TCVD) process.

[0202] According to one embodiment of the present invention, a substrate such as a silicon wafer 2010 (see reference 2010) can be used. Figure 13 As a mask frame 2100, the inorganic layer 2210 of the film 2200 may include silicon nitride (SiN). That is, the inorganic layer 2210 of the film 2200 and the rear surface inorganic pattern layer 2310 may include silicon nitride formed on the front and rear surfaces of the substrate 2010 by a TCVD process. The metal layer 2220 of the film 2200 may include at least one of a metal such as chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), or a nitride or oxide of said metal. For example, the metal layer 2220 of the film 2200 may be formed on the inorganic layer 2210 by a chemical vapor deposition process or a physical vapor deposition process.

[0203] According to one embodiment of the present invention, each of the pixel openings 2230 of the film 2200 may include a first opening 2232 penetrating the metal layer 2220 and a second opening 2234 penetrating the inorganic layer 2210. Specifically, as... Figure 19As shown, the second opening part 2234 can have a width that increases toward the cell opening part 2102. Specifically, the second opening part 2234 can have a width that gradually expands toward the cell opening part 2102, and can be formed by an anisotropic etching process using an ion beam. For example, the second opening part 2234 can be formed by an Ion Beam Etching (IBE) process, a Reactive Ion Beam Etching (RIBE) process, or a Chemically Assisted Ion Beam Etching (CAIBE) process. In the IBE process, a sputtering gas such as argon (Ar) gas can be used, and in the RIBE process or the CAIBE process, a reaction gas for chemical reaction with the inorganic layer 2210 (for example, a reaction gas such as CF4, CF4 / O2, CHF3, CF3Br, HBr, or the like) can be used together with the sputtering gas. However, since the kinds of the sputtering gas and the reaction gas can be variously changed, the scope of the present application will not be limited to the above kinds.

[0204] In particular, the second opening part 2234 can be formed by the anisotropic etching process to have an inclination θ of about 30° to about 85° or so on the inner side surface of the second opening part 2234. The inclination θ of the inner side surface of the second opening part 2234 can be determined by an incident angle of an ion beam irradiated onto the metal layer 2220 and the inorganic layer 2210 in the anisotropic etching process. In this case, the metal layer 2220 of the film 2200 can function as an etching mask in the anisotropic etching process.

[0205] For example, in a case where a photoresist pattern 2020 (refer to FIG. 2) that exposes a portion where a pixel opening part 2230 is to be formed is formed on the metal layer 2220, the second opening part 2234 can be formed by etching the inorganic layer 2210 using the photoresist pattern 2020 as an etching mask. Figure 13) After being formed on the metal layer 2220, an anisotropic etching process (for example, a reactive ion etching (RIE) process) using the photoresist pattern 2020 as an etching mask can be performed, whereby a plurality of first opening portions 2232 exposing the inorganic layer 2210 through the metal layer 2220 can be formed. After the first opening portions 2232 are formed, the photoresist pattern 2020 can be removed by a lift-off and / or an ashing process. Subsequently, an anisotropic etching process using an ion beam can be performed, and thus a second opening portion 2234 exposing the substrate 2010 can be formed. In this case, the metal layer 2220 having the first opening portion 2232 can be used as an etching mask, and the ion beam can be irradiated onto the metal layer 2220 and the inorganic layer 2210 exposed by the first opening portion 2232. An incident angle of the ion beam can be adjusted by an inclination of a chuck (not shown) on which the substrate 2010 is placed, and an inclination θ of an inner side surface of each of the second opening portions 2234 can be determined by the incident angle of the ion beam.

[0206] According to an embodiment of the present disclosure, the film 2200 can have a thickness of about 0.1 μm to about 3.0 μm, and a thickness ratio between the metal layer 2220 and the inorganic layer 2210 can be adjusted to about 1:2 to about 1:20. For example, an initial thickness of the metal layer 2220 can be about 0.1 μm to about 1 μm, and a final thickness of the metal layer 2220 can be about 10 nm to about 100 nm. Specifically, in the anisotropic etching process using the ion beam, the metal layer 2220 can be partially removed, and after the anisotropic etching process is performed, the thickness of the metal layer 2220 can be reduced to about 10 nm to about 100 nm. In this case, the initial thickness of the metal layer 2220 can be appropriately determined based on an etching selectivity ratio of the anisotropic etching process.

[0207] As a result, the second opening portion 2234 of the film 2200 can have an increased width toward the cell opening portion 2102 of the mask frame 2100 by the anisotropic etching process using the ion beam, as shown in FIG. 22B. Figure 17 As shown in FIG. 22B, a portion of the inorganic layer 2210 located between the pixel opening portions 2230 can have a cross-sectional shape in the form of an inverted trapezoid. Accordingly, in a deposition process for forming a light emitting layer on the backplane substrate 3002, a deposition source 3110 (refer to FIG. 31) can be reduced, and thus a deposition process can be performed using a plurality of deposition sources 3110. Figure 14) loss of the light emitting substance provided. Specifically, in the deposition process, the first opening portion 2232 and the second opening portion 2234 can function as a supply path of the light emitting substance, and in particular, the second opening portion 2234 can function as an inlet of the supply path. Therefore, in the deposition process, the amount of the light emitting substance blocked by the deposition mask 2000 can be significantly reduced, and in turn, the size and thickness of the light emitting layer can be more uniformly and precisely controlled.

[0208] On the other hand, in the anisotropic etching process using the ion beam, the surface roughness (Ra) of the metal layer 2220 can be significantly improved by the ion beam. The surface roughness (Ra) of the metal layer 2220 can be improved to about 0.1 nm to about 1.0 nm or so by irradiation of the ion beam, whereby in the deposition process, the deposition mask 2000 can be sufficiently attached to the backplane substrate 3002.

[0209] According to an embodiment of the present application, in order to reduce the bending of the unit area 2202 (hereinafter, referred to as "cell warpage"), the inorganic layer 2210 of the film 2200 can be formed to have a residual tensile stress. In this case, considering the overall bending (hereinafter, referred to as "global warpage") of the deposition mask 2000, the inorganic layer 2210 of the film 2200 can be formed to have a relatively small residual tensile stress. For example, the inorganic layer 2210 of the film 2200 can be formed to have a residual tensile stress of about 200 MPa to about 500 MPa or so by a TCVD process.

[0210] However, when the inorganic layer 2210 and the back surface inorganic pattern layer 2310 are disposed on the front surface and the back surface of the mask frame 2100, respectively, the area of the inorganic layer 2210 and the area of the back surface inorganic pattern layer 2310 can be different from each other, and thus, the force applied to the mask frame 2100 from the inorganic layer 2210 and the force applied to the mask frame 2100 from the back surface inorganic pattern layer 2310 can be different from each other. As a result, after the deposition mask 2000 is manufactured, the deposition mask 2000 can be globally warped due to the difference in the forces.

[0211] According to an embodiment of the present application, the metal layer 2220 of the film 2200 can be used to improve the tensile strength of the cell region 2202. In particular, to compensate for the difference in the forces, the metal layer 2220 of the film 2200 can be formed to have a residual compressive stress. In particular, to compensate for the difference in the forces, the metal layer 2220 of the film 2200 can have a residual compressive stress that is less than the residual tensile stress of the inorganic layer 2210. For example, the metal layer 2220 of the film 2200 can be formed to have a residual compressive stress of about -400 MPa to about -100 MPa. As a result, the cell warping of the cell region 2202 can be improved by the residual tensile stress of the inorganic layer 2210, and the global warping of the deposition mask 2000 can be improved by the residual compressive stress of the metal layer 2220.

[0212] On the other hand, although not shown, a front surface oxide layer (not shown) can be disposed between the mask frame 2100 and the inorganic layer 2210, and a back surface oxide layer (not shown) can be disposed between the mask frame 2100 and the back surface inorganic pattern layer 2310. The front surface oxide layer and the back surface oxide layer can include silicon oxide, and can have a residual compressive stress that is less than the residual tensile stress of the inorganic layer 2210 to improve the global warping of the deposition mask 2000. For example, the front surface oxide layer and the back surface oxide layer can have a residual compressive stress of about -400 MPa to about -100 MPa.

[0213] Figure 14 is a schematic cross-sectional view for explaining a deposition mask according to another embodiment of the present application.

[0214] Referring to Figures 11 to 13 , a deposition mask 2002 according to another embodiment of the present application can include a mask frame 2100 and a film 2200 disposed on the mask frame 2100. The mask frame 2100 can have a cell opening portion 2102, and can include a rim region 2104 that defines the cell opening portion 2102. The film 2200 can include a cell region 2202 disposed on the cell opening portion 2102 and a mesh region 2204 disposed on the rim region 2104.

[0215] A substrate 2010 such as a silicon wafer can be used as the mask frame 2100, and an inorganic layer 2210 formed on the substrate 2010 can be used as the film 2200. For example, the mask frame 2100 can have a plurality of unit opening portions 2102, and the film 2200 can include unit regions 2202 arranged on the unit opening portions 2102, respectively. The unit regions 2202 of the film 2200 can have pixel opening portions 2230 that communicate with the unit opening portions 2102 of the mask frame 2100, and each of the pixel opening portions 2230 can have a width that increases toward the unit opening portions 2102. For example, an inner side surface of each of the pixel opening portions 2230 can have an inclination θ of about 30° to about 85° or so, and a portion of the inorganic layer 2210 located between the pixel opening portions 2230 can have a cross-sectional shape in the form of an inverted trapezoid.

[0216] The deposition mask 2002 according to the present embodiment can have a structure in which the metal layer 2220 arranged on the inorganic layer 2210 is removed, in comparison with the deposition mask 2000 that has been described with reference to Figures 11 to 13 The deposition mask 2002 according to the present embodiment can have a structure substantially identical to the deposition mask 2000 that has been described with reference to Figure 15 The metal layer 2220 can be removed by an etching process after forming second opening portions 2234 that function as the pixel opening portions 2230 through the inorganic layer 2210. Therefore, further description will be omitted with respect to the remaining constituent elements other than the inorganic layer 2210.

[0217] According to the present embodiment, the inorganic layer 2210 can have a surface roughness (Ra) of about 0.1 nm to about 1.0 nm or so. For example, after forming the inorganic layer 2210 on the substrate 2010, an ion beam milling (IBM) process using an ion beam is performed, so that the surface roughness (Ra) of the inorganic layer 2210 can be improved to about 0.1 nm to about 1.0 nm or so. For example, during the IBM process, an ion beam including argon ions can be irradiated onto the inorganic layer 2210, and the surface roughness (Ra) of the inorganic layer 2210 can be improved by the ion beam. In this case, the metal layer 2220 can be formed on the inorganic layer 2210 after the IBM process is performed.

[0218] Figure 15 is a schematic cross-sectional view for describing a deposition mask according to still another embodiment of the present application.

[0219] With reference to Figure 15According to another embodiment of the present application, a deposition mask 2004 can include a mask frame 2100 and a film 2200 disposed on the mask frame 2100. The mask frame 2100 can have a plurality of unit opening portions 2102, and can include a plurality of rim regions 2104 defining the unit opening portions 2102. The film 2200 can include a plurality of unit regions 2202 disposed on the unit opening portions 2102 and a plurality of grid regions 2204 disposed on the rim regions 2104.

[0220] For example, the film 2200 can include a plurality of unit regions 2202 and a plurality of grid regions 2204 defining the unit regions 2202. The mask frame 2100 can have a plurality of unit opening portions 2102 respectively exposing the unit regions 2202 of the film 2200, and can include a plurality of rim regions 2104 defining the unit opening portions 2102. The rim regions 2104 of the mask frame 2100 can be configured to surround the unit opening portions 2102, and the grid regions 2204 of the film 2200 can be configured to surround the unit regions 2202. The unit regions 2202 of the film 2200 can be respectively disposed on the unit opening portions 2102 of the mask frame 2100, and the grid regions 2204 of the film 2200 can be disposed on the rim regions 2104 of the mask frame 2100.

[0221] The film 2200 can include an inorganic layer 2212 disposed on the mask frame 2100 and a metal layer 2220 disposed on the inorganic layer 2212. Each of the unit regions 2202 of the film 2200 can have a plurality of pixel opening portions 2230. The plurality of pixel opening portions 2230 can be formed through each of the unit regions 2202. That is, as shown in FIG. 2B, the pixel opening portions 2230 of the film 2200 can be connected to the unit opening portions 2102 of the mask frame 2100 through the metal layer 2220 and the inorganic layer 2212. Figure 15

[0222] A back surface inorganic pattern layer 2310 can be disposed on a back surface of the mask frame 2100. The back surface inorganic pattern layer 2310 can be used as an etching mask in an etching process for forming the unit opening portions 2102, and can be composed of the same substance as the inorganic layer 2212 of the film 2200. For example, the inorganic layer 2212 of the film 2200 and the back surface inorganic pattern layer 2310 can be simultaneously formed by a TCVD process.

[0223] ​According to the present embodiment, the substrate 2010 such as a silicon wafer can be used as the mask frame 2100, and the inorganic layer 2212 of the film 2200 can include silicon nitride (SiN). That is, the inorganic layer 2212 of the film 2200 and the back surface inorganic pattern layer 2310 can include silicon nitride formed on the front surface and the back surface of the substrate 2010 by a TCVD process. The metal layer 2220 of the film 2200 can include at least one of metals such as chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), etc., or nitrides or oxides of the metals. For example, the metal layer 2220 of the film 2200 can be formed on the inorganic layer 2212 by a chemical vapor deposition process or a physical vapor deposition process.

[0224] According to the present embodiment, each of the pixel opening portions 2230 of the film 2200 can include a first opening portion 2232 that penetrates the metal layer 2220 and a second opening portion 2234 that penetrates the inorganic layer 2212. In particular, as shown in FIG. 22B, the second opening portion 2234 can have a width that increases toward the unit opening portion 2102. Specifically, the second opening portion 2234 can have a width that gradually expands toward the unit opening portion 2102, and can be formed by an anisotropic etching process using an ion beam. For example, the second opening portion 2234 can be formed by an IBE process, an RIBE process, or a CAIBE process. Figure 15

[0225] The second opening portion 2234 can be formed by the anisotropic etching process to have an inclination θ of about 30° to about 85° or so on an inner side surface of the second opening portion 2234. The inclination θ of the inner side surface of the second opening portion 2234 can be determined by an incident angle of an ion beam irradiated onto the metal layer 2220 and the inorganic layer 2212 in the anisotropic etching process. In this case, the metal layer 2220 of the film 2200 can function as an etching mask in the anisotropic etching process.

[0226] ​For example, after forming a photoresist pattern 2020, which exposes the portion where the pixel opening part 2230 is to be formed, on the metal layer 2220, an anisotropic etching process (for example, an RIE process) using the photoresist pattern 2020 as an etching mask can be performed, whereby a plurality of first opening parts 2232, which expose the inorganic layer 2212 through the metal layer 2220, can be formed. After forming the first opening parts 2232, the photoresist pattern 2020 can be removed by a peeling and / or ashing process. Subsequently, an anisotropic etching process using an ion beam can be performed, whereby second opening parts 2234, which expose the substrate 2010, can be formed. In this case, the metal layer 2220 having the first opening parts 2232 can serve as an etching mask, and the ion beam can be irradiated onto the metal layer 2220 and the inorganic layer 2212 exposed by the first opening parts 2232. The incident angle of the ion beam can be adjusted by the inclination of a chuck (not shown) on which the substrate 2010 is placed, and the inclination θ of the inner side surface of each of the second opening parts 2234 can be determined by the incident angle of the ion beam.

[0227] In particular, according to the present embodiment, as shown in FIG. 22, the thickness Thl of the cell region 2202 can be smaller than the thickness Th2 of the grid region 2204. For example, when the incident angle of the ion beam in the anisotropic etching process is increased, the inclination θ of the inner side surface of the second opening part 2234 can be decreased, and thus the lower surface portion of the inorganic layer 2212 can be removed by the ion beam. In this case, the inner side surfaces of the second opening parts 2234 adjacent to each other can be connected to each other, and thus, as shown in FIG. 22, a portion of the inorganic layer 2212 located between the second opening parts 2234 can have a cross-sectional shape in the form of an inverted triangle. As a result, the thickness Thl of the cell region 2202 can be decreased, and thus, the thickness Thl of the cell region 2202 can become smaller than the thickness Th2 of the grid region 2204. Figure 15 Figure 16 In particular, according to the present embodiment, as shown in FIG. 22, the thickness Thl of the cell region 2202 can be smaller than the thickness Th2 of the grid region 2204. For example, when the incident angle of the ion beam in the anisotropic etching process is increased, the inclination θ of the inner side surface of the second opening part 2234 can be decreased, and thus the lower surface portion of the inorganic layer 2212 can be removed by the ion beam. In this case, the inner side surfaces of the second opening parts 2234 adjacent to each other can be connected to each other, and thus, as shown in FIG. 22, a portion of the inorganic layer 2212 located between the second opening parts 2234 can have a cross-sectional shape in the form of an inverted triangle. As a result, the thickness Thl of the cell region 2202 can be decreased, and thus, the thickness Thl of the cell region 2202 can become smaller than the thickness Th2 of the grid region 2204.

[0228] According to the present embodiment, the grid region 2204 of the film 2200 can have a thickness Th2 of about 0.1 μm to about 3.0 μm or so, and the metal layer 2220 can have a thickness of about 10 nm to about 100 nm or so. In this case, the cell region 2202 of the film 2200 can have a thickness Thl smaller than the thickness Th2 of the grid region 2204 and larger than the thickness of the metal layer 2220.

[0229] Figure 16 is a schematic cross-sectional view for illustrating a deposition mask according to still another embodiment of the present application.

[0230] Referring to FIG. 21, Figure 15 ​According to a further embodiment of the present application, a deposition mask 2006 can include a mask frame 2100 and a film 2200 disposed on the mask frame 2100. The mask frame 2100 can have a unit opening portion 2102 and can include a rim region 2104 defining the unit opening portion 2102. The film 2200 can include a unit region 2202 disposed on the unit opening portion 2102 and a mesh region 2204 disposed on the rim region 2104.

[0231] A substrate 2010 such as a silicon wafer can be used as the mask frame 2100, and an inorganic layer 2212 formed on the substrate 2010 can be used as the film 2200. For example, the mask frame 2100 can have a plurality of unit opening portions 2102, and the film 2200 can include unit regions 2202 disposed on the unit opening portions 2102, respectively. The unit regions 2202 of the film 2200 can have pixel opening portions 2230 in communication with the unit opening portions 2102 of the mask frame 2100, and each of the pixel opening portions 2230 can have a width that increases toward the unit opening portion 2102. For example, an inner side surface of each of the pixel opening portions 2230 can have an inclination θ of about 30° to about 85° or so, and a portion of the inorganic layer 2212 located between the pixel opening portions 2230 can have a cross-sectional shape in the form of an inverted triangle.

[0232] As compared with the deposition mask 2004 that has been described with reference to Figure 15 , the deposition mask 2006 according to the present embodiment can have a structure in which the metal layer 2220 disposed on the inorganic layer 2212 is removed. That is, the deposition mask 2006 according to the present embodiment can be configured to be substantially the same as the deposition mask 2004 that has been described with reference to Figure 17 , except for the inorganic layer 2212 and the metal layer 2220. Specifically, the metal layer 2220 can be removed by an etching process after forming second opening portions 2234 that pass through the inorganic layer 2212, which can serve as the pixel opening portions 2230. Therefore, further description will be omitted for the remaining constituent elements other than the inorganic layer 2212.

[0233] According to the present embodiment, the lower surface portion of the inorganic layer 2212 can be removed by the anisotropic etching process for forming the second opening portion 2234, whereby the thickness Thl of the unit region 2202 can become smaller than the thickness Th2 of the grid region 2204. In addition, the inorganic layer 2212 can have a surface roughness (Ra) of about 0.1 nm to about 1.0 nm or so. For example, after the inorganic layer 2212 is formed on the substrate 2010, an IBM process using an ion beam is performed, whereby the surface roughness (Ra) of the inorganic layer 2212 can be improved to about 0.1 nm to about 1.0 nm or so. In this case, the metal layer 2220 can be formed on the inorganic layer 2212 after the IBM process is performed.

[0234] Figures 11 to 13 is for illustrating a deposition apparatus including Figure 17 a schematic view of a deposition apparatus using the deposition mask shown in FIG. 2.

[0235] Referring to Figures 18 to 24 , the deposition apparatus 3000 can be used to form light emitting layers on the backplane substrate 3002. Specifically, an anode electrode can be disposed on the backplane substrate 3002, and the deposition apparatus 3000 can be used to form red, green, and blue light emitting layers on the anode electrode.

[0236] For example, the deposition apparatus 3000 can include a process chamber 3100, a deposition source 3110 disposed inside the process chamber 3100, a deposition mask 2000 disposed above the deposition source 3110, a support member 3120 for supporting the deposition mask 2000, an electrostatic chuck 3130 disposed above the deposition mask 2000 and supporting the backplane substrate 3002, and the like.

[0237] The process chamber 3100 can have a sealed internal space, and can perform a deposition process for forming light emitting layers on the backplane substrate 3002 in the internal space of the process chamber 3100. The process chamber 3100 can be connected to a vacuum pump (not shown), and the internal space of the process chamber 3100 can be modulated to a vacuum atmosphere by the vacuum pump.

[0238] The deposition source 3110 can be disposed inside the process chamber 3100, and a deposition material can be received inside the deposition source 3110. The deposition source 3110 can evaporate a deposition material such as an organic material, an inorganic material, a conductive material, or the like toward the backplane substrate 3002, and the evaporated deposition material can be deposited onto the backplane substrate 3002 through the deposition mask 2000. For example, the deposition source 3110 can evaporate an organic material for forming light emitting layers on the backplane substrate 3002, and can be provided with a heater (not shown) for evaporating the organic material.

[0239] The support member 3120 for supporting the deposition mask 2000 can be arranged above the deposition source 3110. For example, the support member 3120 can support an edge portion of the deposition mask 2000. Although not shown, the support member 3120 can be configured to be movable and rotatable in a vertical direction or a horizontal direction by a driving portion (not shown) in order to adjust a position and an angle of the deposition mask 2000.

[0240] The electrostatic chuck 3130 for supporting the backplane substrate 3002 can be arranged above the deposition mask 2000. The electrostatic chuck 3130 can clamp the backplane substrate 3002 with an electrostatic force to make the backplane substrate 3002 face downward, i.e., to make the backplane substrate 3002 face the deposition mask 2000. At this time, the backplane substrate 3002 can be arranged to have the anode electrode face downward, and the deposition mask 2000 can be arranged to have the metal layer 2220 face the backplane substrate 3002.

[0241] Although not shown, the electrostatic chuck 3130 can be configured to be movable and rotatable in a vertical direction or a horizontal direction by a driving portion (not shown) in order to adjust a position and an angle of the backplane substrate 3002. Further, after the deposition mask 2000 is arranged on the support member 3120 and the backplane substrate 3002 is clamped to the electrostatic chuck 3130 below, a position alignment between the backplane substrate 3002 and the deposition mask 2000 can be performed. For example, after the backplane substrate 3002 and the deposition mask 2000 are aligned to make the pixel opening portion 2230 of the deposition mask 2000 face the anode electrode of any one of the light emitting stacks ES1, ES2, ES3, the electrostatic chuck 3130 can be lowered or the support member 3120 can be raised, and thus the deposition mask 2000 can be closely attached to the backplane substrate 3002. At this time, the metal layer 2220 of the deposition mask 2000 can be closely attached to the backplane substrate 3002, and thus the first opening portion 2232 of the pixel opening portion 2230 of the through metal layer 2220 can be arranged to be adjacent to the anode electrode.

[0242] As described above, after the deposition mask 2000 is tightly attached to the backplane substrate 3002, the deposition source 3110 can evaporate the organic substance, and the evaporated organic substance can be deposited onto the anode electrode of the backplane substrate 3002 through the unit opening portion 2102 and the pixel opening portion 2230 of the deposition mask 2000. At this time, since the second opening portion 2234 of the pixel opening portion 2230 adjacent to the unit opening portion 2102 has a width that increases toward the unit opening portion 2102, the amount of the organic substance deposited on the anode electrode can be increased, and the amount of the organic substance blocked by the deposition mask 2000 can be reduced. As a result, during the deposition process, the loss of the organic substance can be reduced, and the thickness and size of the light-emitting layer can be more accurately controlled.

[0243] Figure 18 is a schematic cross-sectional view for explaining a manufacturing method of a deposition mask according to still another embodiment of the present application.

[0244] Referring to Figure 19 The inorganic layer 2210 can be formed on the substrate 2010. For example, a silicon wafer can be used as the substrate 2010, and the inorganic layer 2210 can be formed by a TCVD process. The inorganic layer 2210 can include silicon nitride, and can be formed by the TCVD process to have a thickness of about 0.1 μm to about 3.0 μm, for example, a thickness of about 1 μm. In this case, the inorganic layer 2210 can be formed on the front surface of the substrate 2010, and a back surface inorganic layer 2300 can be formed on the back surface of the substrate 2010. That is, the inorganic layer 2210 and the back surface inorganic layer 2300 can be simultaneously formed by the TCVD process.

[0245] For example, a DCS (Dichlorosilane, SiH2Cl2) gas used as a source gas and an ammonia (NH3) gas used as a reaction gas can be supplied in a process chamber of a deposition apparatus for performing the TCVD process, whereby silicon nitride layers can be formed on the front surface and the back surface of the substrate 2010. However, since the kinds of the source gas and the reaction gas can vary, the scope of the present application is not limited thereto. In this case, in order to reduce the unit warpage of the deposition mask 2000, the inorganic layer 2210 is preferably formed to have a residual tensile stress. For example, by appropriately adjusting the supply flow rates of the source gas and the reaction gas, the pressure and the temperature inside the process chamber, and the like, the inorganic layer 2210 and the back surface inorganic layer 2300 having a residual tensile stress of about 200 MPa to about 500 MPa can be formed on the front surface and the back surface of the substrate 2010, respectively.

[0246] Next, a metal layer 2220 can be formed on the inorganic layer 2210. For example, the metal layer 2220 can include at least one of metals such as chromium (Cr), tungsten (W), titanium (Ti), tantalum (Ta), aluminum (Al), etc., or nitrides or oxides of the metals, and can be formed on the inorganic layer 2210 to have a thickness of about 0.1 μm to about 1 μm or so by a chemical vapor deposition process or a physical vapor deposition process. At this time, the metal layer 2220 can have a residual compressive stress.

[0247] On the other hand, although not shown, an alignment key (not shown) for alignment with the back plate substrate 3002 in a deposition process can be formed on the front surface edge portion of the substrate 2010. For example, the alignment key can be formed by patterning a metal layer (not shown) formed on the front surface of the substrate 2010. In this case, the inorganic layer 2210 and the back surface inorganic layer 2300 can be formed on the front surface and the back surface of the substrate 2010, respectively, after the alignment key is formed.

[0248] Referring to Figure 20 and Figure 19 The metal layer 2220 can be patterned to form a plurality of first opening portions 2232 exposing the inorganic layer 2210. For example, as shown in FIG. 22B, a photoresist pattern 2020 exposing a portion where the first opening portion 2232 is to be formed can be formed on the metal layer 2220, as shown in FIG. 22C, the first opening portion 2232 exposing the inorganic layer 2210 can be formed by performing an anisotropic etching process (e.g., an RIE process) using the photoresist pattern 2020 as an etching mask. After the first opening portion 2232 is formed, the photoresist pattern 2020 can be removed by a lift-off and / or ashing process. Figure 20 Figure 21

[0249] Referring to Figure 21 ​​The inorganic layer 2210 can be patterned to form a plurality of second opening portions 2234 exposing the substrate 2010. The second opening portions 2234 can be formed by an anisotropic etching process using the ion beam IB (for example, an IBE process, an RIBE process, or a CAIBE process), in which case the metal layer 2220 in which the first opening portions 2232 are formed can function as an etching mask. For example, in the IBE process, a sputtering gas such as argon (Ar) gas can be used. In this case, the ion beam IB including argon ions can be irradiated onto the metal layer 2220 and the inorganic layer 2210, and the inorganic layer 2210 can be partially removed by the ion beam IB. On the other hand, in the RIBE process or the CAIBE process, a reaction gas (for example, a reaction gas such as CF4, CF4 / O2, CHF3, CF3Br, HBr, or the like) for chemically reacting with the inorganic layer 2210 can be used together with the sputtering gas. However, since the kinds of the sputtering gas and the reaction gas can be variously changed, the scope of the present application will not be limited to the kinds as described above.

[0250] According to the present embodiment, the second opening portions 2234 can be formed by the anisotropic etching process such that the inner side surfaces of each of the second opening portions 2234 have an inclination θ of about 30° to about 85° or so. The inclination θ of the inner side surfaces of the second opening portions 2234 can be determined by an incident angle of the ion beam IB irradiated onto the metal layer 2220 and the inorganic layer 2210 in the anisotropic etching process. The incident angle of the ion beam IB can be adjusted by an inclination of a chuck (not shown) on which the substrate 2010 is placed, and the inclination θ of the inner side surfaces of each of the second opening portions 2234 can be determined by the incident angle of the ion beam IB. In particular, during the anisotropic etching process using the ion beam IB, the substrate 2010 can be rotated at a predetermined speed by the chuck, and thus the width of the second opening portions 2234 can gradually increase toward the substrate 2010 by the anisotropic etching process using the ion beam IB. In addition, as shown in FIG. 22, a portion of the inorganic layer 2210 between the second opening portions 2234 can have a cross-sectional shape in the form of an inverted trapezoid. Figures 22 to 24

[0251] ​On the other hand, during the anisotropic etching process, the metal layer 2220 can be partially removed by the ion beam IB, and after the anisotropic etching process, the thickness of the metal layer 2220 can be reduced to approximately 10 nm to approximately 100 nm. Furthermore, in the anisotropic etching process utilizing the ion beam IB, the surface roughness (Ra) of the metal layer 2220 can be significantly improved by the ion beam IB. The surface roughness (Ra) of the metal layer 2220 can be improved by approximately 0.1 nm to approximately 1.0 nm by irradiation with the ion beam IB.

[0252] Reference Figure 22 After forming the second opening 2234, the substrate 2010 can be patterned to form a unit opening 2102 communicating with the second opening 2234. For example, as Figure 23 As shown, a photoresist pattern 2030 that exposes the portion of the unit opening 2102 to be formed can be formed on the back surface inorganic layer 2300, such as... Figure 24 As shown, a back surface inorganic pattern layer 2310 can be formed on the back surface of the substrate 2010 by performing an anisotropic etching process (e.g., RIE process) using the photoresist pattern 2030 as an etching mask. After the back surface inorganic pattern layer 2310 is formed, the photoresist pattern 2030 can be removed by a stripping and / or ashing process.

[0253] Next, as Figure 13 As shown, the substrate 2010 can be partially removed by a wet etching process using the back surface inorganic pattern layer 2310 as an etching mask, thereby forming a unit opening 2102 that penetrates the substrate 2010 and connects to the second opening 2234. For example, the wet etching process can be performed using an etching solution including tetramethyl ammonium hydroxide (TMAH) or potassium hydroxide (KOH) until the inorganic layer 2210 is exposed, thus enabling the fabrication of... Figure 14 The deposition mask shown is 2000.

[0254] According to another embodiment of the present invention, although not shown, after forming the unit opening 2102, the metal layer 2220 can be removed by an isotropic etching process. For example, the metal layer 2220 can be removed by a wet etching process, thus enabling the fabrication of... Figure 25The deposition mask 2002 is shown. In this case, after the inorganic layer 2210 is formed on the substrate 2010, an IBM process can be performed in order to improve the surface roughness (Ra) of the inorganic layer 2210. The surface roughness (Ra) of the inorganic layer 2210 can be improved to about 0.1 nm to about 1.0 nm or so by the IBM process, and a metal layer 2220 can be formed on the inorganic layer 2210 after the IBM process is performed.

[0255] Figure 26 and Figures 18 to 20 is a schematic sectional view for explaining a manufacturing method of a deposition mask according to still another embodiment of the present application.

[0256] According to still another embodiment of the present application, the inorganic layer 2212 and the back surface inorganic layer 2300 can be formed on the front surface and the back surface of the substrate 2010, and the metal layer 2220 can be formed on the inorganic layer 2212. Next, the metal layer 2220 can be patterned to form a first opening portion 2232 that exposes the inorganic layer 2212. In the present embodiment, the inorganic layer 2212, the back surface inorganic layer 2300, the metal layer 2220, and the first opening portion 2232 are substantially the same as those already described with reference to Figure 25

[0257] Referring to Figure 25 The inorganic layer 2212 can be patterned to form a plurality of second opening portions 2234 that expose the substrate 2010. The second opening portions 2234 can be formed by an anisotropic etching process using the ion beam IB (for example, an IBE process, an RIBE process, or a CAIBE process), in which case the metal layer 2220 in which the first opening portion 2232 is formed can function as an etching mask in the anisotropic etching process.

[0258] ​According to the present embodiment, the second opening portions 2234 can be formed by the anisotropic etching process such that the inner side surfaces of each of the second opening portions 2234 have an inclination θ of about 30° to about 85° or so. The inclination θ of the inner side surfaces of the second opening portions 2234 can be determined by the incident angle of the ion beam IB irradiated onto the metal layer 2220 and the inorganic layer 2210 in the anisotropic etching process. The incident angle of the ion beam can be adjusted by the inclination of a chuck (not shown) on which the substrate 2010 is placed, and the inclination θ of the inner side surfaces of each of the second opening portions 2234 can be determined by the incident angle of the ion beam IB. In particular, during the anisotropic etching process using the ion beam IB, the substrate 2010 can be rotated at a predetermined speed by the chuck, and thus, the width of the second opening portions 2234 can gradually increase toward the substrate 2010 by the anisotropic etching process using the ion beam IB.

[0259] In particular, according to the present embodiment, the inclination of the chuck can be adjusted such that the inner side surfaces of the second opening portions 2234 adjacent to each other are connected to each other, and thus, by the irradiation of the ion beam IB, as shown in FIG. 23B, cavities 2236 connected to the second opening portions 2234 can be formed between the inorganic layer 2212 and the substrate 2010. Figure 25 In particular, according to the present embodiment, the inclination of the chuck can be adjusted such that the inner side surfaces of the second opening portions 2234 adjacent to each other are connected to each other, and thus, by the irradiation of the ion beam IB, as shown in FIG. 23B, cavities 2236 connected to the second opening portions 2234 can be formed between the inorganic layer 2212 and the substrate 2010. Figure 26 As shown in FIG. 23B, a portion of the inorganic layer 2212 between the second opening portions 2234 can have a cross-sectional shape in the form of an inverted triangle.

[0260] On the other hand, during the anisotropic etching process, the metal layer 2220 can be partially removed by the ion beam IB, and after the anisotropic etching process, the thickness of the metal layer 2220 can be reduced to about 10 nm to about 100 nm or so. In addition, in the anisotropic etching process using the ion beam IB, the surface roughness (Ra) of the metal layer 2220 can be significantly improved by the irradiation of the ion beam IB. The surface roughness (Ra) of the metal layer 2220 can be improved to about 0.1 nm to about 1.0 nm or so by the irradiation of the ion beam IB.

[0261] Referring to FIG. 24A, the substrate 2010 can be rotated at a predetermined speed by the chuck, and thus, the width of the second opening portions 2234 can gradually increase toward the substrate 2010 by the anisotropic etching process using the ion beam IB. Figure 15After forming the second opening 2234, the substrate 2010 can be patterned to form a unit opening 2102 communicating with the second opening 2234. For example, the back surface inorganic layer 2300 can be patterned to form a back surface inorganic pattern layer 2310, and the unit opening 2102 communicating with the second opening 2234 can be formed by performing an etching process using the back surface inorganic pattern layer 2310 as an etching mask. Specifically, the unit opening 2102 can be formed by a wet etching process and can be connected to the second opening 2234 through the cavity 2236. For example, the wet etching process can be performed using an etching solution including TMAH or KOH, thus enabling the fabrication of... Figures 22 to 24 The deposition mask 2004 is shown. In this embodiment, since the step of forming the unit opening 2102 is the same as that already referred to... Figure 16 The steps for explaining are essentially the same, so further detailed explanations will be omitted.

[0262] According to another embodiment of the present invention, although not shown, after forming the unit opening 2102, the metal layer 2220 can be removed by an isotropic etching process. For example, the metal layer 2220 can be removed by a wet etching process, thus enabling the fabrication of... ​ The deposition mask 2006 is shown. In this case, after the inorganic layer 2212 is formed on the substrate 2010, an IBM process can be performed to improve the surface roughness (Ra) of the inorganic layer 2212. The surface roughness (Ra) of the inorganic layer 2212 can be improved to about 0.1 nm to about 1.0 nm by the IBM process, and a metal layer 2220 can be formed on the inorganic layer 2212 after the IBM process is performed.

[0263] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as exemplary in all respects, and not as limiting.

Claims

1. A deposition mask, characterized by, Comprising: a mask frame having a cell opening portion; and a film including an inorganic layer disposed on the mask frame and a metal layer disposed on the inorganic layer, the film having a plurality of pixel opening portions communicating with the cell opening portion, each of the pixel opening portions including a first opening portion through the metal layer and a second opening portion through the inorganic layer, the second opening portion having a width that increases toward the cell opening portion.

2. The deposition mask according to claim 1, wherein a surface roughness of the metal layer is 0.1 nm to 1.0 nm.

3. The deposition mask according to claim 1, wherein a portion of the inorganic layer located between the pixel opening portions has a cross-sectional shape of an inverted trapezoid form.

4. The deposition mask according to claim 1, wherein the inorganic layer has a residual tensile stress, and the metal layer has a residual compressive stress that is smaller than the residual tensile stress of the inorganic layer.

5. A deposition mask, characterized by, Comprising: a mask frame having a cell opening portion, and including a rim region defining the cell opening portion; and a film including a cell region disposed on the cell opening portion and a grid region disposed on the rim region, the cell region having a plurality of pixel opening portions communicating with the cell opening portion, and a thickness of the cell region being smaller than a thickness of the grid region.

6. The deposition mask according to claim 5, wherein the film includes an inorganic layer disposed on the mask frame.

7. The deposition mask according to claim 6, wherein a portion of the inorganic layer located between the pixel opening portions has a cross-sectional shape of an inverted triangle form.

8. The deposition mask according to claim 6, wherein each of the pixel opening portions is through the inorganic layer, and has a width that increases toward the cell opening portion.

9. The deposition mask according to claim 6, wherein a surface roughness of the inorganic layer is 0.1 nm to 1.0 nm.

10. The deposition mask according to claim 5, wherein the film includes an inorganic layer disposed on the mask frame and a metal layer disposed on the inorganic layer, each of the pixel opening portions includes a first opening portion through the metal layer and a second opening portion through the inorganic layer, the second opening portion has a width that increases toward the cell opening portion.

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