MOSFET driving circuit based on edge triggering

Abstract

The utility model discloses an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) driving circuit based on edge triggering. The MOSFET driving circuit comprises an edge triggering pulse generating circuit used for generating differential pulses; the circuit also comprises a post-stage circuit. The back-stage circuit is in butt joint with the positive pulse output end and the negative pulse output end of the edge trigger pulse generation circuit. The post-stage circuit comprises a transformer (T1), a voltage-regulator tube (D1), a first switch tube (K1), a second switch tube (K2) and a third switch tube (S1); the MOSFET driving circuit based on edge triggering is simple and reliable, and the cost and the size of the driving circuit can be greatly reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a MOSFET drive circuit based on edge triggering. BACKGROUND

[0002] The current widely used inverter full bridge needs to use isolation drive to realize the isolation of main circuit and control circuit, and the isolation drive can use optical coupling drive or transformer drive, the advantage of optical coupling drive is that it can transmit arbitrary duty cycle drive signal, but the circuit is relatively complex, and the cost is also higher, because a special isolation power supply is needed, in addition, optical coupling will produce delay, when the drive signal frequency is high, the delay will lead to signal distortion. Based on transformer drive, no isolation power supply is needed, but it cannot transmit too large or too small duty cycle. In addition, transformer drive can be divided into direct drive and edge trigger drive, the disadvantages of direct drive are: the drive transformer loss is related to the drive signal frequency, and high or low drive signal frequency will lead to high loss and serious heating.

[0003] There is an isolation FET pulse transformer drive circuit based on edge triggering, which does not need an isolation power supply and can transmit a duty cycle close to 100%. However, this circuit does not have the ability to generate dead time, and the drive charging resistance and discharging resistance cannot be independently controlled, and the use of too many discrete components will increase the unreliability of the drive circuit.

[0004] At present, optical coupling drive is a commonly used method, and the optical coupling drive method is also relatively simple, but optical coupling drive needs an independent isolation power supply, and in addition, high-power high-speed drive optical coupling is also relatively expensive, in summary, the optical coupling drive method has large volume and high cost, and cannot be used in some occasions requiring compact structure. Transformer drive is also a commonly used drive method, and the volume of high-frequency magnetic transformer can be very small, and the output power can also be relatively large, but the drive transformer cannot transmit 100% duty cycle, because it will lead to transformer saturation. Even if the primary side of the transformer uses an isolation capacitor, it can effectively prevent the direct current bias of the primary side of the isolation transformer from leading to transformer magnetic saturation, but if the drive signal frequency is too low, the transformer loss will be greatly increased, which may lead to thermal runaway of the drive pulse transformer magnetic characteristic, thereby increasing the risk of equipment damage.

[0005] Therefore, it is necessary to design a new MOSFET drive circuit. UTILITY MODEL CONTENTS

[0006] The utility model solves the technical problem to provide a MOSFET drive circuit based on edge triggering, the MOSFET drive circuit based on edge triggering is simple and reliable, and can greatly reduce the cost and volume of the drive circuit.

[0007] The technical solutions of the utility model are as follows:

[0008] A MOSFET drive circuit based on edge triggering, characterized in that it comprises an edge-triggered pulse generation circuit for generating a differential pulse;

[0009] The edge-triggered pulse generation circuit: the input signal (input) is connected to the first input end of the first NAND gate (U4B) through the first NOT gate (U1C); the output end of the first NOT gate (U1C) is also connected to the negative electrode of the first diode (D3); the positive electrode of the first diode (D3) is connected to the ground through the first capacitor (C2); the first resistor (R5) is connected in parallel with the first diode (D3); the positive and negative electrodes of the first diode (D3) are also connected to the second input end of the first NAND gate (U4B) through the second NOT gate (U1D);

[0010] The output end of the first NAND gate (U4B) is connected to the positive pulse output end (pwm-p) through the third NOT gate (U1F);

[0011] The input signal (input) is also connected to the first end of the second NAND gate (U5C) and the negative electrode of the second diode (D4); the positive electrode of the second diode (D4) is connected to the second end of the second NAND gate (U5C) through the fourth NOT gate (U2E); the positive electrode of the second diode (D4) is connected to the ground through the second capacitor (C3); the second resistor (R6) is connected in parallel with the second diode (D4); the output end of the second NAND gate (U5C) is connected to the negative pulse output end (pwm-n) through the fifth NOT gate (U6A).

[0012] It also comprises a post-stage circuit; the post-stage circuit is connected to the positive pulse output end and the negative pulse output end of the edge-triggered pulse generation circuit;

[0013] The post-stage circuit comprises a transformer (T1), a voltage stabilizing tube (D1), a first switch tube (K1), a second switch tube (K2) and a third switch tube (S1);

[0014] The first switch tube (K1), the second switch tube (K2) and the third switch tube (S1) are all N-MOS tubes with body diodes;

[0015] The positive pulse output end (pwm-p) is connected to the primary first end of the transformer (T1) through the third capacitor (C4); the negative pulse output end (pwm-n) is connected to the primary second end of the transformer (T1); the first end of the secondary side of the transformer (T1) and the first end of the primary side of the transformer (T1) are the same-named ends;

[0016] The first end and the second end of the secondary side of the transformer (T1) are connected to the S pole and the G pole of the first switch tube (K1) respectively;

[0017] The D pole of the first switch tube (K1) is connected to the G pole of the third switch tube (S1) through the third resistor (R1);

[0018] The G pole of the first switch tube (K1) and the S pole of the third switch tube (S1) are connected to the negative pole and the positive pole of the stabilizing tube (D1) respectively;

[0019] The G pole and the S pole of the second switch tube (K2) are connected to the negative pole and the positive pole of the stabilizing tube (D1) respectively; the D pole of the second switch tube (K2) is connected to the G pole of the third switch tube (S1) through the fourth resistor (R2); the fifth resistor (R3) is connected between the S pole and the G pole of the third switch tube (S1).

[0020] The edge trigger pulse generating circuit is connected with the subsequent circuit through a gate drive device.

[0021] The gate drive device adopts a UCC27524 chip.

[0022] The utility model scheme adopts a transformer as isolation, and the transformer isolation is a commonly used isolation form of a full-control device driving circuit such as MOSFET and IGBT, which has the advantages of simple circuit, no need to provide an isolation power supply, low cost, no transmission delay to a pulse signal and the like.

[0023] Beneficial effects:

[0024] The circuit has the following characteristics:

[0025] 1. The rising edge and the falling edge dead time can be independently controlled to prevent the upper and lower bridge arms from being directly connected, and the CPU control dead time is not needed, so that the PCB layout and wiring can be more conveniently arranged;

[0026] 2. The pulse width of the opening pulse and the closing pulse can be independently controlled, and the opening and closing of different types of MOSFETs can be reliably ensured through actual adjustment;

[0027] 3. The resistance values of the drive gate charging resistor and the discharging resistor can be independently selected, and the MOSFET opening and closing time can be flexibly controlled

[0028]

[0029] 4. The duty cycle close to 100% can be transmitted, and the efficiency is high and the loss is small;

[0030] 5. The circuit principle is simple, the structure is compact, and the circuit is easy to integrate. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is an inverter full-bridge topology structure diagram;

[0032] Figure 2 It is an edge trigger pulse generating circuit;​

[0033] Figure 3 Edge triggered pulse generation circuit timing diagram;

[0034] Figure 4 Edge triggered pulse generation circuit timing diagram;

[0035] Figure 5 Edge triggered pulse generation circuit schematic diagram;

[0036] Figure 6 Edge triggered pulse generation simulation schematic diagram;

[0037] Figure 7 S1 gate voltage simulation waveform. DETAILED DESCRIPTION

[0038] The utility model will be made further detailed description in combination with the drawings and specific embodiments:

[0039] Example 1:

[0040] The inverter full-bridge main circuit is as shown in Figure 1 The inverter full-bridge has various modulation modes, and the output is a square wave with controllable duty ratio when adopting phase-shift control, which is commonly used in the inverter front end of isolated power supply, at this time, the CPU needs to give the driving signal of S1 and S4; It can also adopt a bipolar modulation mode, at this time, S1 and S4 are turned on at the same time, and are turned off at the same time, at this time, the CPU only needs to give a driving signal of S1; In addition, it can also adopt a unipolar modulation mode, at this time, the CPU also needs to give the driving signal of S1 and S4. After the unipolar and bipolar PWM modulation is filtered, AC power can be output, which is commonly used in inverter AC power circuit. In order to prevent the two switches on one bridge arm from being short-circuited, it is necessary to set a dead time delay at the turn-on time of the upper and lower switch tubes of one bridge arm, and the current CPU also has the function of setting the dead time, but if so, one bridge inverter circuit needs to draw four signal lines from the CPU, as described above, if the bipolar modulation mode is adopted, only one driving signal line needs to be drawn from the CPU, so in many cases, the method of generating a dead time delay by the driving circuit itself will make the PCB layout and wiring much easier.

[0041] The edge triggered pulse generation circuit is as shown in Figure 2 Figure 1 ​S1 and S2) are the same if bipolar modulation is adopted. In the circuit, PWM is a signal output by the CPU and is an input signal in the circuit, and the signal voltage range is 0-3.3v. PWM1P and PWM1N are a pair of differential driving of switch S1. PWM2P and PWM2N are a pair of differential driving of switch S2, and the voltage range is 0-5v. Δt1 is the rising edge dead time delay, Δt2 is the falling edge dead time delay, and it is necessary to set the dead time delay, and the purpose is to prevent the two switches of one bridge arm from being short-circuited due to the through fault. Δt3 is the on pulse width of S1, and Δt4 is the off pulse width of S1. Δt5 is the on pulse width of S2, and Δt6 is the off pulse width of S2.

[0042] Figure 3 The timing diagram of the edge-triggered pulse generation circuit, wherein PWM1 is the driving signal synthesized by PWM1P and PWM1N, and PWM2 is the driving signal synthesized by PWM2P and PWM2N. Since Δt1-Δt6 can be independently set, the setting rules of the utility model are as follows: the dead time (Δt1 and Δt2) > the on pulse width (Δt3 and Δt5) > the off pulse width (Δt4 and Δt6).

[0043] Δt4 all can be independently set, the setting rules of the utility model are as follows: the dead time (Δt1 and Δt2) > the on pulse width (Δt3 and Δt5) > the off pulse width (Δt4 and Δt6).

[0044] Figure 4 The signal is amplified by UCC27524 power after the edge-triggered pulse generation circuit is driven, and the direct current bias is filtered by C4 direct current isolation capacitor, the capacitance value of C4 is 2.2uF, and finally the switch tube S1 is driven after T1 isolation. There is a gate drive circuit on the secondary side of T1 isolation transformer, and the output voltage range of the secondary side of T1 is 15v- -15v. K1 and K2 are small MOSFETs, R1 is a charging resistor, the resistance range is several Ω-ten several Ω, R2 is a discharging resistor, the resistance range is zero point several Ω-several Ω, D1 is a voltage stabilizing tube, and generally is 15v. When PWM1P>PWM1N, K1 and K2 are closed, the charging current path is shown by the thick dashed line in the figure, the charging current passes through the body diode of K1, R1 and D1 to charge the gate of S1. When PWM1P=PWM1N, K1 and K2 are still closed, and the gate voltage of S1 remains high. When PWM1P<PWM1N, K1 and K2 are opened, the discharging path is shown by the thin dashed line in the figure, and since R2 << R1, most of the current passes through R2, and only a small part of the discharging current passes through R1, so that the voltage on the gate of S1 is rapidly discharged. By controlling the size of R1 and R2, the charging and discharging speed of S1 can be controlled, so that the on and off speed of S1 can be controlled.

[0045] The simulation parameters are shown in Table 1, the simulation circuit is shown in Figure 5 The simulation platform is NI Multisim13.0

[0046] Table 1 list of simulation model parameters

[0047]

[0048]

[0049] Figure 6 The final drive gate voltage waveform. It can be seen that the S1 gate voltage is kept at high level under the action of the turn-on narrow pulse, and is quickly reduced to 0v under the action of the turn-off narrow pulse, achieving the purpose of circuit design. In practical application, UCC27524 (UCC27524 device is a double-channel, high-speed, low-side gate driver device, which can effectively drive MOSFET and IGBT switch tube) is used for power and voltage amplification between the front-end and rear-end circuits, and the actual designed circuit gate voltage is generally 0-15v.

[0050] The above only describes the preferred embodiments of the present application and is not intended to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An edge-triggered MOSFET drive circuit, comprising: The edge-triggered pulse generating circuit comprises a first inverter (U1C) and a first NAND gate (U4B). The input signal (input) is connected to the first input terminal of the first NAND gate (U4B) through the first inverter (U1C), and the output terminal of the first inverter (U1C) is also connected to the negative electrode of the first diode (D3). The output terminal of the first NAND gate (U4B) is connected to the positive pulse output terminal (pwm-p) through the third inverter (U1F). The input signal (input) is also connected to the first terminal of the second NAND gate (U5C) and the negative electrode of the second diode (D4), and the positive electrode of the second diode (D4) is connected to the second terminal of the second NAND gate (U5C) through the fourth inverter (U2E).

2. The edge-triggered MOSFET drive circuit according to claim 1, wherein, The output terminal of the second NAND gate (U5C) is connected to the negative pulse output terminal (pwm-n) through the fifth inverter (U6A). The post-stage circuit is also connected to the positive pulse output terminal and the negative pulse output terminal of the edge-triggered pulse generating circuit. The post-stage circuit comprises a transformer (T1), a voltage stabilizing tube (D1), a first switch tube (K1), a second switch tube (K2) and a third switch tube (S1). The first switch tube (K1), the second switch tube (K2) and the third switch tube (S1) are all N-MOS tubes with body diodes. The positive pulse output terminal (pwm-p) is connected to the first primary terminal of the transformer (T1) through the third capacitor (C4), and the negative pulse output terminal (pwm-n) is connected to the second primary terminal of the transformer (T1). The first terminal of the secondary side of the transformer (T1) and the first terminal of the primary side of the transformer (T1) are the same terminals. The first terminal and the second terminal of the secondary side of the transformer (T1) are respectively connected to the S terminal and the G terminal of the first switch tube (K1). The D terminal of the first switch tube (K1) is connected to the G terminal of the third switch tube (S1) through the third resistor (R1).

3. The edge-triggered MOSFET drive circuit according to claim 1 or 2, characterized in that, The G terminal of the first switch tube (K1) and the S terminal of the third switch tube (S1) are respectively connected to the negative electrode and the positive electrode of the voltage stabilizing tube (D1).

4. The edge-triggered MOSFET drive circuit according to claim 3, wherein The G terminal and the S terminal of the second switch tube (K2) are respectively connected to the negative electrode and the positive electrode of the voltage stabilizing tube (D1), and the D terminal of the second switch tube (K2) is connected to the G terminal of the third switch tube (S1) through the fourth resistor (R2). The edge-triggered pulse generating circuit is connected to the post-stage circuit through a gate driver device. The gate driver device adopts a UCC27524 chip.

Images