Chip pin configuration circuit and chip

Abstract

The embodiment of the utility model discloses a chip pin configuration circuit and a chip, and relates to the field of circuits. By introducing the multifunctional module, the multi-layer multiplexer and the flexible configuration mechanism, the problem that the chip pin function is limited in flexible expandability and performance is successfully solved. The flexibility and the application range of the chip can be improved, pin management is simplified, and the utilization rate and the cost performance of the chip are improved.

Description

Technical Field

[0001] This utility model relates to the field of circuits, and in particular to a chip pin configuration circuit and a chip. Background Technology

[0002] In the field of modern electronics, integrated circuit chips, as core components of electronic devices, undertake multiple functions such as data processing, signal transmission, and control. With technological advancements and the diversification of applications, increasingly higher demands are being placed on the flexibility and scalability of chip pin functions. However, existing chip pin configuration methods have significant limitations.

[0003] Traditional chip design typically assigns each pin a fixed configuration for one or a limited number of functions. This fixed configuration determines the pin's specific purpose during the chip design phase, and once the chip is manufactured, its pin functions cannot be changed. While this design approach simplifies chip production and testing, it also significantly limits the chip's flexibility and applicability. Utility Model Content

[0004] This application provides a chip pin configuration circuit and a chip, which can flexibly configure chip pins according to requirements. The technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide a chip pin configuration circuit, wherein the chip has M built-in functional modules, each functional module corresponding to a function, the M functional modules are divided into N groups, each group includes at least one functional module, and M and N are integers greater than 1;

[0006] The chip pin configuration circuit includes:

[0007] N multiplexers: MUX11~MUX1N, multiplexer MUX2 and multiplexer MUX3, N port control registers R11~R1N, port control register R2, port control register R3, processor, and communication bus;

[0008] The processor is connected to the communication bus;

[0009] There is a one-to-one mapping relationship between N port controllers R11 to R1N and N multiplexers MUX11 to MUX1N; one end of port control register R11 is connected to the control terminal of multiplexer MUX11, and the other end of port control register R11 is connected to the communication bus; one end of port control register R12 is connected to the control terminal of multiplexer MUX12, and the other end of port control register R12 is connected to the communication bus; ..., one end of port control register R1N is connected to the control terminal of multiplexer MUX1N, and the other end of port control register R1N is connected to the communication bus.

[0010] There is a one-to-one mapping relationship between N groups and N MUX11 multiplexers; each functional module in each group is connected one-to-one with the input of the corresponding multiplexer.

[0011] Each of the M functional modules is connected one-to-one to the input of the multiplexer MUX2; one end of the port control register R2 is connected to the control terminal of the multiplexer MUX2, and the other end of the port control register R2 is connected to the communication bus.

[0012] The outputs of N multiplexers MUX11 to MUX1N and the output of multiplexer MUX2 are connected one-to-one with the input of multiplexer MUX3.

[0013] One end of the port control register R3 is connected to the control terminal of the multiplexer MUX3, and the other end of the port control register R3 is connected to the communication bus.

[0014] The output of the multiplexer MUX3 is connected to one of the chip pins of the chip.

[0015] The processor configures each port control register through the communication bus. Each multiplexer reads the configuration information in the corresponding port control register and selects one input terminal from multiple input terminals to conduct according to the configuration information.

[0016] Secondly, this application provides an electronic device including the aforementioned chip pin configuration circuit.

[0017] The beneficial effects of the technical solutions provided in some embodiments of this application include at least the following:

[0018] This technical solution achieves dynamic functional configuration of chip pins through the built-in M functional modules and a three-level multiplexer (MUX11~MUX1N, MUX2, MUX3) structure. The processor can flexibly configure the control registers (R11~R1N, R2, R3) of each port as needed via the communication bus, thereby changing the input selection of the multiplexer and thus changing the function of the chip pins.

[0019] Because the number of functional modules and multiplexers (M and N) is variable, and they can be combined through flexible connection methods, this technical solution has good scalability and upgradeability. With technological advancements and the diversification of applications, new application requirements can be adapted by increasing the number of functional modules and multiplexers, or by adjusting their connection methods.

[0020] By dividing M functional modules into N groups and assigning a multiplexer (MUX11~MUX1N) to each group, this technical solution simplifies pin management. The processor can more easily group and configure pin functions, improving configuration efficiency and accuracy.

[0021] The multi-functional module and multi-layer multiplexer structure in this technical solution enable the chip to be compatible with a variety of different application requirements. Through flexible configuration, the same chip can be applied to different electronic devices, achieving hardware reusability.

[0022] Because pin functions can be flexibly configured, pin usage can be optimized according to actual application requirements. This avoids the situation where some pins may be idle due to functional mismatch, as is the case with traditional fixed configurations, thus improving chip utilization and cost-effectiveness. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a structural diagram of the chip pin configuration circuit provided in the embodiments of this application. Detailed Implementation

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0026] Please see Figure 1 This utility model provides a schematic diagram of the structure of a chip pin configuration circuit according to an embodiment.

[0027] exist Figure 1 In the chip, there are M built-in functional modules, each of which corresponds to one function. The M functional modules are divided into N groups, and each group includes at least one functional module. For example, M = 200, that is, the chip has 200 built-in functional modules, totaling 200 functions, and N = 5, that is, each group includes 5 functional modules.

[0028] The chip pin configuration circuit includes: N multiplexers: MUX11~MUX1N ( Figure 1 Only MUX11, multiplexer MUX2 and multiplexer MUX3, and N port control registers R11 to R1N are shown in the diagram. Figure 1Only R11, port control register R2, port control register R3, processor, and communication bus are shown. Each multiplexer allows only one input to be active at any given time. The processor is connected to the communication bus; there is a one-to-one mapping between N port controllers R11 to R1N and N multiplexers MUX11 to MUX1N; one end of port control register R11 is connected to the control terminal of multiplexer MUX11, and the other end is connected to the communication bus; one end of port control register R12 is connected to the control terminal of multiplexer MUX12, and the other end is connected to the communication bus; ..., one end of port control register R1N is connected to the control terminal of multiplexer MUX1N, and the other end is connected to the communication bus; there is a one-to-one mapping between N groups and N multiplexers MUX11; each functional module in each group is connected one-to-one to the input terminal of the corresponding multiplexer; M functional modules... Each block is connected one-to-one to the input of multiplexer MUX2; one end of port control register R2 is connected to the control terminal of multiplexer MUX2, and the other end of port control register R2 is connected to the communication bus; the outputs of N multiplexers MUX11 to MUX1N and the output of multiplexer MUX2 are connected one-to-one to the input of multiplexer MUX3; one end of port control register R3 is connected to the control terminal of multiplexer MUX3, and the other end of port control register R3 is connected to the communication bus; the output of multiplexer MUX3 is connected to a chip pin of the chip; the processor configures each port control register through the communication bus, each multiplexer reads the configuration information in the corresponding port control register, and selects one input terminal from multiple input terminals to conduct according to the configuration information.

[0029] This application achieves flexible configuration of chip pins by incorporating multiple functional modules, multiplexers, port control registers, a processor, and a communication bus within the chip. The processor configures each port control register via the communication bus, and the multiplexer selects one input terminal from multiple input terminals to conduct based on the configuration information in the port control register, thereby realizing dynamic configuration of pin functions.

[0030] The chip has M built-in functional modules, each corresponding to a specific function. These functional modules are divided into N groups, and each group includes at least one functional module. Each group forms a one-to-one mapping relationship with a multiplexer (MUX11~MUX1N). Each functional module in a group is connected one-to-one to the input of the corresponding multiplexer.

[0031] Each multiplexer (MUX11~MUX1N, MUX2, MUX3) has a corresponding port control register (R11~R1N, R2, R3). One end of the port control register is connected to the control terminal of the multiplexer, and the other end is connected to the communication bus. The processor writes configuration information to the port control register through the communication bus, and this configuration information determines which input terminal the multiplexer should select for conduction.

[0032] The outputs of N multiplexers MUX11 to MUX1N, as well as the output of multiplexer MUX2, are connected one-to-one to the input of multiplexer MUX3. Multiplexer MUX3 selects one of these inputs to activate based on its configuration information (provided by port control register R3). Finally, the output of multiplexer MUX3 is connected to a pin of the chip, enabling dynamic configuration of that pin's function.

[0033] For example: Suppose the chip has 8 built-in functional modules (M=8), these modules are divided into 2 groups (N=2), and each group contains 4 functional modules.

[0034] The processor writes configuration information to the port control register R11 via the communication bus, specifying that MUX11 should select its second input (i.e., the second functional module in group 1) for conduction. Similarly, the processor writes configuration information to R12, R2, and R3, specifying the input selection of MUX12, MUX2, and MUX3, respectively.

[0035] Based on the configuration information of R11, MUX11 selects its second input terminal to conduct, transmitting the signal from that input terminal to its output terminal. The output signals of MUX11 and MUX2, as well as other possible input signals (if any), are transmitted to the input terminals of MUX3. Based on the configuration information of R3, MUX3 selects one of these input terminals to conduct and transmits the signal to a pin on the chip. In this way, the function of the chip pins can be dynamically configured as needed to perform any of the eight functional modules.

[0036] In summary, this technical solution achieves dynamic functional configuration of chip pins by flexibly configuring multiplexers and port control registers, thereby improving the chip's flexibility and scalability.

[0037] In this embodiment, the communication bus serves as the primary channel for data transmission between the processor and various port control registers. The processor writes configuration information to the port control registers via the communication bus, which determines which input terminal the multiplexer should select for conduction. Simultaneously, the port control registers may also relay current status or error information to the processor via the communication bus. The processor sends configuration instructions to each port control register via the communication bus to control the multiplexer. These configuration instructions contain specific information about which input terminal to select for conduction and are crucial for the system's dynamic pin configuration. In complex systems, the communication bus can also play a role in system synchronization and coordination. For example, when the processor needs to configure multiple port control registers simultaneously, it can send configuration instructions in parallel via the communication bus, thereby accelerating configuration and improving system efficiency. The existence of the communication bus also provides the system with good scalability and compatibility. With technological advancements and changing application requirements, it may be necessary to add new functional modules or adjust existing configurations. The communication bus facilitates the configuration and integration of new functional modules while maintaining compatibility with existing systems.

[0038] In the embodiments of this application, each group contains an equal number of functional modules. This setting helps simplify configuration logic and improve system consistency and maintainability. When each group contains the same number of functional modules, the system becomes simpler and more intuitive in design, configuration, and maintenance. For example, if each group contains four functional modules, the processor can use a uniform strategy to process all groups when configuring the multiplexer, without needing special processing for different groups. Since each group has an equal number of functional modules, the processor can use a more standardized configuration format when writing configuration information to the port control register via the communication bus. This helps reduce configuration errors and improve system stability and reliability. When the number of functional modules in a group is equal, system resources can be allocated and utilized more rationally. For example, if functional modules in a certain group are frequently used, while functional modules in other groups are used less frequently, resource utilization can be optimized by adjusting the grouping strategy or increasing the number of functional modules.

[0039] The embodiments of this application have the following technical effects:

[0040] This technical solution achieves dynamic functional configuration of chip pins through the built-in M functional modules and a three-level multiplexer (MUX11~MUX1N, MUX2, MUX3) structure. The processor can flexibly configure the control registers (R11~R1N, R2, R3) of each port as needed via the communication bus, thereby changing the input selection of the multiplexer and thus changing the function of the chip pins.

[0041] Because the number of functional modules and multiplexers (M and N) is variable, and they can be combined through flexible connection methods, this technical solution has good scalability and upgradeability. With technological advancements and the diversification of applications, new application requirements can be adapted by increasing the number of functional modules and multiplexers, or by adjusting their connection methods.

[0042] By dividing M functional modules into N groups and assigning a multiplexer (MUX11~MUX1N) to each group, this technical solution simplifies pin management. The processor can more easily group and configure pin functions, improving configuration efficiency and accuracy.

[0043] The multi-functional module and multi-layer multiplexer structure in this technical solution enable the chip to be compatible with a variety of different application requirements. Through flexible configuration, the same chip can be applied to different electronic devices, achieving hardware reusability.

[0044] Because pin functions can be flexibly configured, pin usage can be optimized according to actual application requirements. This avoids the situation where some pins may be idle due to functional mismatch, as is the case with traditional fixed configurations, thus improving chip utilization and cost-effectiveness.

[0045] The chips provided in this application embodiment, which are equipped with the aforementioned chip pin configuration circuits, include, but are not limited to, processor chips, microcontrollers, application-specific integrated circuit (ASIC) chips, and field-programmable gate arrays (FPGAs). Processor chips include, for example, central processing units (CPUs), graphics processing units (GPUs), and digital signal processors (DSPs). These chips typically contain a large number of functional modules used to perform various complex calculations and processing tasks. By implementing the above technical solutions, flexible configuration of these chip pins can be achieved, thereby meeting different application requirements.

[0046] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A chip pin configuration circuit, characterized by, The chip is applied to a chip, the chip is built-in with M function modules, each function module corresponds to a function, the M function modules are divided into N groups, each group includes at least one function module, M and N are integers greater than 1; The chip pin configuration circuit comprises: N multiplexers MUX11-MUX1N, a multiplexer MUX2, a multiplexer MUX3, N port control registers R11-R1N, a port control register R2, a port control register R3, a processor and a communication bus; The processor is connected with the communication bus; The N port control registers R11-R1N are in one-to-one mapping relationship with the N multiplexers MUX11-MUX1N; one end of the port control register R11 is connected with the control end of the multiplexing control MUX11, the other end of the port control register R11 is connected with the communication bus, one end of the port control register R12 is connected with the control end of the multiplexing control MUX12, the other end of the port control register R12 is connected with the communication bus, …, one end of the port control register R1N is connected with the control end of the multiplexing control MUX1N, the other end of the port control register R1N is connected with the communication bus; The N groups are in one-to-one mapping relationship with the N multiplexers MUX11; each function module in each group is connected with the input end of the corresponding multiplexer in one-to-one manner; The M function modules are connected with the input end of the multiplexer MUX2 in one-to-one manner; one end of the port control register R2 is connected with the control end of the multiplexer MUX2, the other end of the port control register R2 is connected with the communication bus; The output end of the N multiplexers MUX11-MUX1N and the output end of the multiplexer MUX2 are connected with the input end of the multiplexer MUX3 in one-to-one manner; One end of the port control register R3 is connected with the control end of the multiplexer MUX3, the other end of the port control register R3 is connected with the communication bus; The output end of the multiplexer MUX3 is connected with one chip pin of the chip; The processor configures each port control register through the communication bus, each multiplexer reads the configuration information in the corresponding port control register, and selects one input end to be turned on according to the configuration information.

2. The circuit of claim 1, wherein, The number of function modules included in each group is equal.

3. A chip, characterized by The chip pin configuration circuit comprises the above.

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