Logic interlocking circuit and equipment controller and equipment applying logic interlocking circuit
By using a logic interlock circuit composed of dual optocoupler chips, two independent control signals are converted into logic interlock signals, solving the signal failure problem in the prior art and achieving reliable signal output and stability.
Patent Information
- Application Number
- CN202520015274.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-03
- Publication Date
- 2026-01-06
- Estimated Expiration
- 2035-01-03
AI Technical Summary
In existing technologies, when two independently generated control signals are designed as logical interlocks or interlocks, they are prone to failure, and this problem cannot be effectively solved.
A logic interlock circuit composed of two dual optocoupler chips is used to convert two independent input signals into two logically interlocked output signals through parallel connection and short circuit. Resistors are used to limit current and voltage to ensure electrical isolation and signal stability.
It achieves reliable logic interlocking output of two control signals, reduces the probability of device failure, and ensures the stability of the output signal and the unchanged function of the independent signal.
Smart Images
Figure CN223772032U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electronic circuit technology, specifically to a logic interlock circuit and a device controller and device using the logic interlock circuit. Background Technology
[0002] Different control signals controlling the same or related devices are usually generated independently; however, in some cases, it is required that the two control signals of the device be driven by a logical interlock or interlocking method.
[0003] However, in existing technologies, whether using software or hardware to design two independently generated control signals as logical interlocks or interlocks, failures can occur. The inventors of this application discovered, during the development of this utility model, that the shortcomings of the existing technology have not yet been effectively resolved. Utility Model Content
[0004] The purpose of this utility model embodiment is to provide a logic interlock circuit that outputs two independently generated control signals in a logic interlock manner.
[0005] To achieve the above objectives, this utility model provides a logic interlock circuit for converting independent first and second input signals into two logically interlocked output signals, comprising: a first dual optocoupler chip and a second dual optocoupler chip.
[0006] Wherein, the first input terminal of the first optical coupler of the first dual optical coupler chip and the first input terminal of the first optical coupler of the second dual optical coupler chip are connected in parallel to the first input signal, and the second input terminal of the second optical coupler of the second dual optical coupler chip is connected to the second input signal.
[0007] The second input terminal of the first optocoupler of the second dual optocoupler chip and the first input terminal of the second optocoupler of the second dual optocoupler chip are shorted together.
[0008] The first output terminal of the first optocoupler of the first dual optocoupler chip and the first output terminal of the first optocoupler of the second dual optocoupler chip are connected in parallel to output a first output signal; the second output terminal of the second optocoupler of the second dual optocoupler chip outputs a second output signal.
[0009] The second output terminal of the first optocoupler of the second dual optocoupler chip and the first output terminal of the second optocoupler of the second dual optocoupler chip are shorted.
[0010] Preferably, the logic interlock circuit further includes a first resistor connected between the input-side power supply and the first input terminal of the first optocoupler of the first dual optocoupler chip.
[0011] Preferably, the logic interlock circuit further includes a second resistor connected between the second input terminal of the first optocoupler of the first dual optocoupler chip and the reference ground terminal.
[0012] Preferably, the logic interlock circuit further includes a third resistor connected between the input terminals of the first input signal and the second input signal.
[0013] Preferably, the logic interlock circuit further includes a fourth resistor, through which the second input signal is connected to the second input terminal of the second optocoupler of the second dual optocoupler chip.
[0014] Preferably, the logic interlock circuit further includes a fifth resistor connected between the output power supply and the first output terminal of the first optocoupler of the first dual optocoupler chip.
[0015] Preferably, the logic interlock circuit further includes a sixth resistor connected between the second output terminal of the first optocoupler of the first dual optocoupler chip and the output terminal of the first output signal.
[0016] Preferably, the logic interlock circuit further includes a seventh resistor, connected between the second output terminal of the first optocoupler of the second dual optocoupler chip and the output terminal of the second output signal.
[0017] Preferably, the first, second, third, fourth, fifth, sixth, and seventh resistors in the logic interlock circuit are all integrated resistors.
[0018] Preferably, the first dual optocoupler chip and the second dual optocoupler chip are ELD3H7 chips.
[0019] On the other hand, this utility model embodiment also provides a device controller, including the logic interlock circuit of this application. After the two independent control signals are processed by the logic interlock circuit, the output two logic interlock control signals are applied to the device to be controlled.
[0020] Optionally, the equipment to be controlled can be motor equipment, power equipment, electrical equipment, or electrical appliances.
[0021] On the other hand, this utility model embodiment also provides a device, including the device controller of this application, which receives control signals processed by the device controller and controls the operating parameters of the device through the control signals.
[0022] Through the above technical solution, the first input terminals of the first optocouplers of the first and second dual optocoupler chips are connected in parallel to the first input signal, and the second input terminal of the second optocoupler of the second dual optocoupler chip is connected to the second input signal; the first output terminals of the first optocouplers of the first and second dual optocoupler chips are connected in parallel to output the first output signal, and the second output terminal of the second optocoupler of the second dual optocoupler chip outputs the second output signal; the second input terminal of the first optocoupler of the second dual optocoupler chip and the first input terminal of the second optocoupler of the second dual optocoupler chip are short-circuited; the second output terminal of the first optocoupler of the second dual optocoupler chip and the first output terminal of the second optocoupler of the second dual optocoupler chip are short-circuited, thereby realizing the series connection of the outputs of the two optocouplers, and thus realizing the interlocked output of two conventional digital output signals.
[0023] Other features and advantages of this utility model embodiment will be described in detail in the following detailed description section. Attached Figure Description
[0024] The accompanying drawings are provided to further illustrate the embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:
[0025] Figure 1 This is a circuit diagram of one embodiment of the logic interlock circuit of this utility model. Detailed Implementation
[0026] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.
[0027] It should be noted that the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.
[0028] Figure 1 This is a circuit diagram of a logic interlock circuit provided in an embodiment of the present invention. The decoding circuit is used to convert two independent inputs into two logic-interlocked outputs. The two independent inputs are respectively... Figure 1 The DO1 and DO2 terminals of the microcontroller shown are processed by the logic interlock circuit of this application, and the two digital signals output by the microcontroller are converted into... Figure 1 The two outputs shown are DO_PIN1 and DO_PIN2.
[0029] In this embodiment, the logic interlock circuit mainly includes a first dual optocoupler chip Q1 and a second dual optocoupler chip Q2. Both the first dual optocoupler chip Q1 and the second dual optocoupler chip Q2 are ELD3H7 chips, but this application is not limited to this. Those skilled in the art can select the specific models of Q1 and Q2 according to the specific parameters required, as long as Q1 and Q2 each have two independent optocouplers. The applicant suggests that Q1 and Q2 use the same model of dual optocoupler chip.
[0030] Specifically, in this embodiment, the first input terminal of the first optocoupler of the first dual optocoupler chip Q1 and the first input terminal of the first optocoupler of the second dual optocoupler chip Q2 are connected in parallel to the first input signal. That is... Figure 1 The first pins of Q1 and Q2 shown are connected in parallel to the first input signal DO1.
[0031] The second input terminal of the second optocoupler of the second dual optocoupler chip Q2 is connected to the second input signal. That is... Figure 1 The fourth pin of Q2 shown is connected to the second input signal DO2.
[0032] The second input terminal of the first optocoupler of the second dual optocoupler chip Q2 is shorted to the first input terminal of the second optocoupler of the second dual optocoupler chip Q2. The second output terminal of the first optocoupler of the second dual optocoupler chip Q2 is shorted to the first output terminal of the second optocoupler of the second dual optocoupler chip Q2. That is... Figure 1 The second and third pins of Q2 are shorted, and the sixth and seventh pins of Q2 are shorted.
[0033] The first output terminal of the first optocoupler of the first dual optocoupler chip Q1 and the first output terminal of the first optocoupler of the second dual optocoupler chip Q2 are connected in parallel to output a first output signal, and the second output terminal of the second optocoupler of the second dual optocoupler chip Q2 outputs a second output signal. Figure 1 The eighth pins of Q1 and Q2 are connected in parallel to output the first output signal DO_PIN1, and the fifth pin of Q2 outputs the second output signal DO_PIN2.
[0034] Therefore, in this embodiment, the output of the first output signal DO_PIN1 depends on the first input signal DO1. That is, DO_PIN1 can be high or low following DO1, or DO_PIN1 can be the opposite of DO1. The output of the second output signal DO_PIN2 depends on the first input signal DO1 and the second input signal DO2. DO_PIN2 can only output a high level when DO1 is high and DO2 is low.
[0035] It should be noted that both Q1 and Q2 in this application are implemented using the same type of chip. Figure 1The electrical isolation between the input-side power supply V3.3 and the output-side power supply V24 is shown. Opto-isolation is achieved using an ELD3H7 chip.
[0036] In order to increase the input voltage of the first pins of Q1 and Q2, the logic interlock circuit of this embodiment also includes a first resistor connected between the input power supply and the first input terminal of the first optocoupler of the first dual optocoupler chip Q1.
[0037] To limit the current output of DO1 by the microcontroller, the logic interlock circuit in this embodiment also includes a second resistor connected between the second input terminal of the first optocoupler of the first dual optocoupler chip Q1 and the reference ground terminal.
[0038] To limit the voltage amplitude of DO1 and DO2 output by the microcontroller and prevent voltage overshoot, the logic interlock circuit in this embodiment also includes a third resistor, which is connected between the input terminals of the first input signal and the second input signal.
[0039] To limit the current input to Q2, the logic interlock circuit in this embodiment also includes a fourth resistor, through which the second input signal is connected to the second input terminal of the second optocoupler of the second dual optocoupler chip Q2.
[0040] In order to limit the total current on the output side, the logic interlock circuit of this embodiment also includes a fifth resistor, which is connected between the output power supply and the first output terminal of the first optocoupler of the first dual optocoupler chip Q1.
[0041] In order to limit the output current of Q1, that is, to limit the current of the first output signal, the logic interlock circuit of this embodiment also includes a sixth resistor, which is connected between the second output terminal of the first optocoupler of the first dual optocoupler chip Q1 and the output terminal of the first output signal.
[0042] In order to limit the output current of Q2, that is, to limit the current of the second output signal, the logic interlock circuit of this embodiment also includes a seventh resistor, which is connected between the second output terminal of the first optocoupler of the second dual optocoupler chip Q2 and the output terminal of the second output signal.
[0043] To reduce resistance drift caused by temperature and ensure output stability and low variation, the first, second, third, fourth, fifth, sixth, and seventh resistors in the logic interlock circuit of this embodiment are all integrated resistors.
[0044] Compared with the prior art, the technical advantages of this embodiment are as follows:
[0045] 1. The use of two dual optocoupler chips to realize the logic interlock of two independent digital output signals reduces the probability of device failure in discrete optocouplers and improves the reliability of logic interlock signals.
[0046] 2. While ensuring that the output DO_PIN2 and DO_PIN1 are logically interlocked, the original output DO_PIN1 signal function remains unchanged and is not affected by the logical interlock.
[0047] This utility model embodiment also provides a device controller, including the logic interlock circuit of this application. After the two independent control signals are processed by the logic interlock circuit, the output two logic interlock control signals are applied to the device to be controlled.
[0048] In some implementations, the device to be controlled is a motor, power, electrical equipment, or electrical appliance.
[0049] This utility model embodiment also provides a device, including the device controller of this application, which receives control signals processed by the device controller and controls the operating parameters of the device through the control signals.
[0050] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0051] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.
Claims
1. A logic interlock circuit for converting independent first and second input signals into two-way output signals which are logically interlocked, characterized by Comprise: a first dual optical coupling chip and a second dual optical coupling chip, wherein a first input end of a first optical coupling of the first dual optical coupling chip and a first input end of a first optical coupling of the second dual optical coupling chip are connected in parallel to a first input signal, and a second input end of a second optical coupling of the second dual optical coupling chip is connected to a second input signal; a second input end of the first optical coupling of the second dual optical coupling chip and a first input end of the second optical coupling of the second dual optical coupling chip are short-circuited; a first output end of the first optical coupling of the first dual optical coupling chip and a first output end of the first optical coupling of the second dual optical coupling chip are connected in parallel to output a first output signal, and a second output end of the second optical coupling of the second dual optical coupling chip outputs a second output signal; and a second output end of the first optical coupling of the second dual optical coupling chip and a first output end of the second optical coupling of the second dual optical coupling chip are short-circuited.
2. The logic interlock circuit of claim 1, wherein, Further comprising a first resistor connected between an input-side power supply and the first input end of the first optical coupling of the first dual optical coupling chip.
3. The logic interlock circuit of claim 1, wherein, Further comprising a second resistor connected between the second input end of the first optical coupling of the first dual optical coupling chip and a reference ground terminal.
4. The logic interlock circuit of claim 1, wherein, Further comprising a third resistor connected across input terminals of the first input signal and input terminals of the second input signal.
5. The logic interlock circuit of claim 1, wherein, Further comprising a fourth resistor, and the second input signal is connected to the second input end of the second optical coupling of the second dual optical coupling chip via the fourth resistor.
6. The logic interlock circuit of claim 1, wherein, Further comprising a fifth resistor connected between an output-side power supply and the first output end of the first optical coupling of the first dual optical coupling chip.
7. The logic interlock circuit of claim 1, wherein, Further comprising a sixth resistor connected between the second output end of the first optical coupling of the first dual optical coupling chip and output terminals of the first output signal.
8. The logic interlock circuit of claim 1, wherein, Further comprising a seventh resistor connected between the second output end of the first optical coupling of the second dual optical coupling chip and output terminals of the second output signal.
9. The logic interlock circuit of any of claims 1-8, wherein, The first dual optical coupling chip and the second dual optical coupling chip are ELD3H7 chips.
10. A device controller, characterized by The logic interlocking circuit according to any one of claims 1-9, two independent control signals are processed by the logic interlocking circuit, and two logic-interlocked control signals output by the logic interlocking circuit are applied to a device to be controlled.
11. The device controller of claim 10, wherein, The device to be controlled is a motor device, a power device, an electrical device, or an electric appliance.
12. An apparatus, comprising: The device controller according to claim 10 or 11, a control signal processed by the device controller is received, and an operating parameter of the device is controlled by the control signal.