Driving circuit of high-speed IGBT and silicon carbide MOS
By designing high-speed IGBT and silicon carbide MOS drive circuits and using components such as drive isolation chips and RC filters, the problem that existing drive circuits cannot meet high power requirements has been solved, achieving low-cost, high-efficiency drive and improved reliability.
Patent Information
- Application Number
- CN202520160522.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-01-09
- Estimated Expiration
- 2035-01-23
AI Technical Summary
Existing drive circuits cannot meet the drive requirements of high-power IGBT modules and silicon carbide MOS modules, and are also costly.
A high-speed IGBT and silicon carbide MOS driving circuit was designed, including a driving power supply, a driver circuit, and a driving power amplifier circuit. The circuit uses a driving isolation chip U1, an RC filter, capacitors, and resistors to achieve efficient driving through signal processing and amplification. A Miller clamping function is added to prevent false turn-on.
It achieves the requirement of high drive power, shortens turn-on and turn-off time, reduces switching losses, improves application reliability, and reduces costs.
Smart Images
Figure CN223785942U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the power electronics technical field, concretely relates to a kind of driving circuit of high-speed IGBT and silicon carbide MOS. BACKGROUND
[0002] With the gradual development of photovoltaic installation, the use of higher power IGBT module and third-generation wide bandgap silicon carbide MOS module gradually, the requirement of driving circuit is also increasingly strict.
[0003] The current driving scheme is to purchase driving single board, which does not meet the silicon carbide MOS driving demand due to the characteristics of slow rising, large delay of optical coupling, and the 1.5w rated driving power cannot meet the power demand of various IGBT modules on the market, and the cost is high.
[0004] Therefore, it is urgent to develop a driving circuit to adapt to the current power tube module application, to solve the problems of no silicon carbide MOS driving circuit, insufficient driving capacity and high cost. INVENTION CONTENTS
[0005] The utility model aims at overcoming the problems of no silicon carbide MOS driving circuit, insufficient driving capacity and high cost, and proposes a kind of driving circuit of high-speed IGBT and silicon carbide MOS.
[0006] To achieve the above purpose, the utility model adopts the following technical scheme:
[0007] A kind of driving circuit of high-speed IGBT and silicon carbide MOS, including driving power supply, driver circuit and driving power amplifier circuit;
[0008] The first end of the driver circuit is connected to the driving power supply, the second end of the driver circuit is connected to the PWM signal, the third end of the driver circuit is connected to one end of the driving power amplifier circuit, and the other end of the driving power amplifier circuit is connected to the high-speed IGBT and silicon carbide MOS;
[0009] The driver circuit includes driving isolation chip U1, RC filter, second resistor R2 and diode D1;The first pin and the second pin of the driving isolation chip U1 are connected to the RC filter, the RC filter is connected to the diode D1, the third pin of the driving isolation chip U1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the RC filter and the diode D1, the fifth pin and the eighth pin of the driving isolation chip U1 are connected to the driving power supply, the sixth pin of the driving isolation chip U1 is connected to the G pole of the high-speed IGBT and silicon carbide MOS, and the seventh pin of the driving isolation chip U1 is connected to the driving power amplifier circuit.
[0010] Further, the RC filter comprises a first resistor R1 and a first capacitor C1;
[0011] One end of the first resistor R1 is connected with a PWM signal and a cathode of a diode D1, and the other end of the first resistor R1 is connected with a first pin of a driving isolation chip U1 and one end of a first capacitor C1.
[0012] The other end of the first capacitor C1 is grounded with an anode of the diode D1 and the other end of a second resistor R2.
[0013] Further, the driver circuit further comprises a second capacitor C2, one end of the second capacitor C2 is connected with a positive pole VCC+ of a driving power source, and the other end of the second capacitor C2 is connected with a negative pole VCC- of a driving voltage source.
[0014] Further, the driver circuit further comprises a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a voltage stabilizing tube D2, one end of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifth capacitor C5 and one end of the voltage stabilizing tube D2 are all connected with the positive pole VCC+ of the driving power source, and the other end of the third capacitor C3, the other end of the fourth capacitor C4, the other end of the fifth capacitor C5 and the other end of the voltage stabilizing tube D2 are all connected with an E pole of a high-speed IGBT and a silicon carbide MOS.
[0015] Further, the driver circuit further comprises a sixth capacitor C6, a seventh capacitor C7, a third resistor R3 and a fourth resistor R4, one end of the sixth capacitor C6, one end of the seventh capacitor C7, one end of the third resistor R3 and one end of the fourth resistor R4 are all connected with the negative pole VCC- of the driving voltage source, and the other end of the sixth capacitor C6, the other end of the seventh capacitor C7, the other end of the third resistor R3 and the other end of the fourth resistor R4 are all connected with the E pole of the high-speed IGBT and the silicon carbide MOS.
[0016] Further, the driving power amplification circuit comprises an NPN type transistor Q1 and a PNP type transistor Q2, the base of the NPN type transistor Q1 and the base of the PNP type transistor Q2 are both connected with a seventh pin of the driving isolation chip U1.
[0017] The emitter of the NPN type transistor Q1 and the emitter of the PNP type transistor Q2 are both connected with a driving resistor interface of the high-speed IGBT and the silicon carbide MOS.
[0018] Further, the collector of the NPN type transistor Q1 is connected with the positive pole VCC+ of the driving voltage source.
[0019] The collector of the PNP type transistor Q2 is connected with the negative pole VCC- of the driving voltage source.
[0020] Furthermore, the sixth pin of the drive isolation chip U1 is configured with a Miller clamp.
[0021] Furthermore, the drive isolation chip U1 is a chip with the model number UCC23514MDWVR.
[0022] Furthermore, the driving power supply adopts a 24V voltage source.
[0023] Compared with the prior art, the present invention has the following beneficial technical effects:
[0024] This invention proposes a driving circuit for high-speed IGBTs and silicon carbide MOS transistors. The PWM signal from the product's DSP is level-converted and then input to the driver circuit. After processing by the driver circuit, a drive signal is output. This drive signal then passes through a drive power amplifier circuit to control the turn-on and turn-off of the subsequent high-speed IGBTs and silicon carbide MOS transistors. This driving circuit can meet the turn-on and turn-off requirements of high-power MOS transistors and IGBTs, while shortening the turn-on and turn-off times of the power transistors and the rise and fall times of the drive, reducing switching losses, and improving the application reliability of high-speed IGBTs and silicon carbide MOS transistors. Attached Figure Description
[0025] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of the present invention in any way. Furthermore, the shapes and proportions of the components in the drawings are merely schematic to aid in understanding the present invention and do not specifically limit the shapes and proportions of the components. In the drawings:
[0026] Figure 1 This is a schematic diagram of a high-speed IGBT and silicon carbide MOS driving circuit according to the present invention. Detailed Implementation
[0027] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.
[0028] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.
[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0030] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0031] Example 1
[0032] A high-speed IGBT and silicon carbide MOS driving circuit, such as Figure 1 As shown, the DSP (Digital Signal Processor) outputs a PWM (Pulse Width Modulation) signal, which passes through an RC filter and is input to pins 1 and 2 of the driver isolation chip U1;
[0033] Pin 8 of the driver isolation chip U1 is connected to VCC+ of the driver power supply, and pin 5 of the driver isolation chip U1 is connected to VCC- of the driver power supply. The driver power supply is 24V.
[0034] Pin 7 of the driver isolation chip U1 outputs a drive signal to the push-pull circuit, which drives the output positive voltage through the Zener diode D2, and drives the output negative voltage through the voltage across the current limiting resistors R3 and R4. The total voltage VCC ± minus the voltage of the Zener diode D2.
[0035] In the push-pull circuit, NPN transistor Q1 and PNP transistor Q2 form a signal amplification circuit. NPN transistor Q1 amplifies the positive voltage of the input signal, and PNP transistor Q2 amplifies the negative voltage of the input signal. After passing through the push-pull circuit, a complete drive output signal is obtained to control the turn-on and turn-off of the silicon carbide MOS and high-speed IGBT.
[0036] Pin 6 of the driver isolation chip U1 is the Miller clamp function pin. Pin 6 of the driver isolation chip U1 is connected to the gate of the subsequent high-speed IGBT and silicon carbide MOS. It provides a low impedance loop when the silicon carbide MOS and IGBT are turned off, ensuring that the power transistor device will not be mis-turned on due to interference when it is turned off.
[0037] The driver isolation chip U1 uses a chip with the model number UCC23514MDWVR.
[0038] The driver circuit includes: driver isolation chip U1, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5, sixth capacitor C6, seventh capacitor C7, diode D1, and Zener diode D2.
[0039] One end of the first resistor R1 is the PWM signal input from the DSP and is connected to the cathode of the first diode D1. The other end of the first resistor R1 is connected to pin 1 of the driver isolation chip U1 and one end of the first capacitor C1.
[0040] Pin 3 of the driver isolation chip U1 is connected to one end of the second resistor R2;
[0041] Pins 8 and 5 of the driver isolation chip U1 are connected to the driver power supply;
[0042] Pin 6 of the driver isolation chip U1 is connected to the gate of the subsequent high-speed IGBT and silicon carbide MOS.
[0043] Pin 4 of the driver isolation chip U1 is not connected;
[0044] The second capacitor C2 is connected to the power supply VCC±; one end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the first Zener diode D2 is connected to the positive terminal VCC+ of the power supply, and the other end of the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the first Zener diode D2 is connected to the emitter of the subsequent high-speed IGBT and silicon carbide MOS.
[0045] One end of the sixth capacitor C6, the seventh capacitor C7, the third resistor R3, and the fourth resistor R4 is connected to the negative terminal VCC- of the power supply, and the other end of the sixth capacitor C6, the seventh capacitor C7, the third resistor R3, and the fourth resistor R4 is connected to the emitter of the subsequent high-speed IGBT and silicon carbide MOS.
[0046] The driver amplifier circuit includes: NPN transistor Q1 and PNP transistor Q2;
[0047] The base of NPN transistor Q1 and the base of PNP transistor Q2 are both connected to pin 7 of the driver isolation chip U1;
[0048] The emitters of NPN transistor Q1 and PNP transistor Q2 are both connected to the drive resistor interface of the subsequent high-speed IGBT and silicon carbide MOST.
[0049] The collector of the NPN transistor Q1 is connected to the positive drive voltage source VCC+.
[0050] The collector of the PNP transistor Q2 is connected to the negative drive voltage source VCC-.
[0051] In this embodiment, the driver isolation chip U1 is replaced with a capacitive isolation solution compared to the previous optocoupler solution. This results in lower cost, improved performance, and fast response characteristics with low turn-on and turn-off delays and low rise and fall times. It is also matched with high-speed SiC devices to reduce losses. Furthermore, the selection of push-pull circuit components for the driver output is adapted to the driving requirements of high-power IGBT modules.
[0052] Based on the characteristics of SiC, a Miller clamp function has also been added. By driving pin 6: CLAMP of the isolation chip U1, a low impedance loop is provided when the silicon carbide MOS and IGBT are turned off, ensuring that the power transistor device will not be mis-turned on due to interference when it is turned off.
[0053] Narrow pulse interference suppression can be achieved by adjusting the RC parameters at the input front end of the isolation IC. For example, it can suppress narrow pulses of up to 200ns (5V).
[0054] The driving circuit for a high-speed IGBT and silicon carbide MOS provided in this embodiment is further explained in terms of its working principle as follows;
[0055] PWM signal input and processing: The DSP (Digital Signal Processor) outputs a PWM (Pulse Width Modulation) signal, which is initially current-limited and protected by a combination of a resistor (first resistor R1) and a diode (diode D1). The PWM signal then passes through an RC filter (composed of a first capacitor C1 and a second resistor R2) for smoothing to remove high-frequency noise and interference.
[0056] Driver Isolation and Signal Amplification: The processed PWM signal is input to pins 1 and 2 of the driver isolation chip U1. The driver isolation chip U1 uses a UCC23514MDWVR chip with isolation capabilities to prevent electrical interference between upstream and downstream circuits. Based on the input PWM signal, the driver isolation chip U1 outputs a corresponding drive signal at pin 7. This drive signal is amplified by a push-pull circuit (composed of NPN transistor Q1 and PNP transistor Q2) to meet the driving requirements of subsequent power devices (high-speed IGBT silicon carbide and MOSFETs).
[0057] Positive and negative voltage drive and Miller clamping: The amplified drive signal, through Zener diode D2 and current-limiting resistors R3 and R4, generates positive and negative voltage drive signals, respectively. These signals are used to control the turn-on and turn-off of the high-speed IGBT and silicon carbide MOSFET. Simultaneously, pin 6 (CLAMP) of the drive isolation chip U1 is connected to the gate (G) of the subsequent power device, implementing the Miller clamping function. When the power device is turned off, this pin provides a low-impedance loop to prevent secondary mis-turn-on due to interference.
[0058] Power supply and capacitor filtering: The drive power supply is 24V, connected to pin 8 (VCC+) and pin 5 (VCC-) of the drive isolation chip U1. Multiple capacitors (second capacitor C2, third capacitor C3, etc.) are used for power supply filtering and decoupling to reduce the impact of power supply fluctuations on circuit performance.
[0059] Narrow pulse interference suppression: By adjusting the RC parameters (such as the first resistor R1 and the first capacitor C1) at the input front end of the isolation IC, this circuit can achieve narrow pulse interference suppression.
[0060] This embodiment provides a method for controlling the operation of a high-speed IGBT and silicon carbide MOS driving circuit. This method is implemented through multiple steps and principles, including PWM signal input and processing, drive isolation and signal amplification, positive and negative voltage driving and Miller clamping, power supply and capacitor filtering, and narrow pulse interference suppression. This method offers advantages such as low cost, high performance, and fast response, and is suitable for driving high-speed SiC devices and high-power IGBT modules.
[0061] Many embodiments and applications beyond the examples provided will be apparent to those skilled in the art upon reading the foregoing description. Therefore, the scope of this teaching should not be determined by reference to the foregoing description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed utility model subject matter.
[0062] The above content provides a further detailed description of this utility model. It should not be considered that the specific embodiments of this utility model are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of this utility model, and all of these should be considered to fall within the defined protection scope of this utility model.
Claims
1. A driving circuit for a high-speed IGBT and silicon carbide MOS, characterized in that, This includes the power supply, driver circuit, and drive power amplifier circuit. The first terminal of the driver circuit is connected to the driving power supply, the second terminal of the driver circuit is connected to the PWM signal, the third terminal of the driver circuit is connected to one end of the driving power amplifier circuit, and the other end of the driving power amplifier circuit is connected to the high-speed IGBT and silicon carbide MOS. The driver circuit includes a driver isolation chip U1, an RC filter, a second resistor R2, and a diode D1. The first and second pins of the driver isolation chip U1 are connected to the RC filter, the RC filter is connected to the diode D1, the third pin of the driver isolation chip U1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the RC filter and the diode D1, the fifth and eighth pins of the driver isolation chip U1 are connected to the drive power supply, the sixth pin of the driver isolation chip U1 is connected to the gate of the high-speed IGBT and the silicon carbide MOS, and the seventh pin of the driver isolation chip U1 is connected to the drive power amplifier circuit.
2. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The RC filter includes a first resistor R1 and a first capacitor C1; One end of the first resistor R1 is connected to the PWM signal and the cathode of the diode D1, and the other end of the first resistor R1 is connected to the first pin of the driver isolation chip U1 and one end of the first capacitor C1. The other end of the first capacitor C1 is grounded to the anode of the diode D1 and the other end of the second resistor R2.
3. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driver circuit also includes a second capacitor C2, one end of which is connected to the positive terminal VCC+ of the driving power supply, and the other end of which is connected to the negative terminal VCC- of the driving voltage source.
4. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driver circuit also includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a Zener diode D2. One end of the third capacitor C3, one end of the fourth capacitor C4, one end of the fifth capacitor C5, and one end of the Zener diode D2 are all connected to the positive terminal VCC+ of the drive power supply. The other end of the third capacitor C3, the other end of the fourth capacitor C4, the other end of the fifth capacitor C5, and the other end of the Zener diode D2 are all connected to the emitter (E) of the high-speed IGBT and the silicon carbide MOS.
5. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driver circuit also includes a sixth capacitor C6, a seventh capacitor C7, a third resistor R3, and a fourth resistor R4. One end of the sixth capacitor C6, one end of the seventh capacitor C7, one end of the third resistor R3, and one end of the fourth resistor R4 are all connected to the negative terminal VCC- of the driving voltage source. The other ends of the sixth capacitor C6, the seventh capacitor C7, the third resistor R3, and the fourth resistor R4 are all connected to the emitter (E) of the high-speed IGBT and the silicon carbide MOS.
6. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driving power amplifier circuit includes an NPN transistor Q1 and a PNP transistor Q2. The bases of both the NPN transistor Q1 and the PNP transistor Q2 are connected to the seventh pin of the driving isolation chip U1. The emitters of both the NPN transistor Q1 and the PNP transistor Q2 are connected to the drive resistor interfaces of the high-speed IGBT and silicon carbide MOS.
7. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 6, characterized in that, The collector of the NPN transistor Q1 is connected to the positive terminal VCC+ of the driving voltage source. The collector of the PNP transistor Q2 is connected to the negative terminal VCC- of the driving voltage source.
8. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The sixth pin of the driver isolation chip U1 is configured with a Miller clamp.
9. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driver isolation chip U1 is a chip with the model number UCC23514MDWVR.
10. The driving circuit for a high-speed IGBT and silicon carbide MOS according to claim 1, characterized in that, The driving power supply uses a 24V voltage source.