High-reliability H-bridge dead zone generating circuit

Abstract

The utility model relates to the technical field of H-bridge drive circuits, and discloses a high-reliability H-bridge dead-zone generation circuit, which comprises two AND gates for preventing two MOS (Metal Oxide Semiconductor) transistors on the same side of the circuit from being switched on at the same time; the exclusive-OR gate can distinguish input signal directions and output response control signals; the Schmitt trigger is used for converting the curve waveform into a PWM (Pulse Width Modulation) square wave signal and inhibiting noise and interference in an input signal; the RC time delay circuit is connected with the Schmitt trigger and is used for realizing signal delay; the two AND gates comprise a first AND gate and a second AND gate; the first AND gate and the second AND gate are electrically connected with the exclusive-OR gate, and the exclusive-OR gate and the first AND gate are electrically connected with the Schmitt trigger; according to the utility model, the formation of dead zone time is realized through RC time delay and Schmidt characteristics, the condition of circuit damage caused by simultaneous conduction of the H-bridge drive circuit in the working process is avoided, the hardware cost is lower, and the reliability is higher than the reliability realized by software.

Description

Technical Field

[0001] This utility model relates to the field of H-bridge drive circuit technology, specifically a highly reliable H-bridge dead-time generation circuit. Background Technology

[0002] H-bridge drive circuit: An H-bridge is an electronic circuit that reverses the voltage / current across the connected load or output terminals. This type of circuit can be used in robots and other practical applications for forward / reverse control and speed control of DC motors, stepper motor control, most DC-AC converters and some DC-DC converters in power conversion, and other power electronic devices.

[0003] Dead zone: In the transfer function of a control system, the range of input signals where the output is zero. Servo drives, for example, have dead zones to prevent oscillations caused by repeated enable-disable cycles (called hunting in proportional control systems).

[0004] Existing solutions generally avoid dead time by controlling the time difference between the upper and lower bridge arms by controlling the processor program to create dead time; another solution is that some specific I / O ports inside the processor can be used as timer I / O ports, and the dead time can be configured through specific registers.

[0005] The existing solution has the following drawbacks:

[0006] 1) Software control can lead to issues like program crashes or resets. In high real-time scenarios, the presence of a dead zone can result in equipment failure or component damage. The reliability of software-based dead zones is generally lower than that of purely hardware-based implementations.

[0007] 2) While the built-in configuration of the processor is more reliable than software implementation, it requires a specific processor model to have these configurations, and different processors have different configurations, making them non-interchangeable. Furthermore, selecting these processors often increases hardware costs significantly. Therefore, we need to propose a highly reliable H-bridge dead-time generation circuit. Utility Model Content

[0008] The purpose of this invention is to provide a highly reliable H-bridge dead-time generation circuit. By using RC delay and Schmitt's characteristics to generate dead time, the dead time is generated, avoiding damage to the H-bridge drive circuit caused by simultaneous conduction during operation. Moreover, the hardware cost is lower and the reliability is higher than that of software implementation, thus solving the problems mentioned in the background art.

[0009] To achieve the above objectives, this utility model provides the following technical solution: a highly reliable H-bridge dead-time generation circuit, comprising: two AND gates to prevent two MOS transistors on the same side of the circuit from conducting simultaneously; an XOR gate capable of distinguishing the direction of the input signal and outputting a response control signal; a Schmitt trigger for converting a curved waveform into a PWM square wave signal and suppressing noise and interference in the input signal; and an RC delay circuit connected to the Schmitt trigger to implement signal delay; the two AND gates include a first AND gate and a second AND gate; the first AND gate and the second AND gate are both electrically connected to the XOR gate, and the XOR gate and the first AND gate are both electrically connected to the Schmitt trigger.

[0010] Preferably, a lower MOSFET is connected to the first AND gate, and an upper MOSFET is connected to the second AND gate.

[0011] Preferably, the Schmitt trigger includes a chip U1, with pin 5 of the chip U1 connected to a 3.3V operating voltage, and the RC delay circuit includes a grounded capacitor C1 connected to pin 2 of the chip U1 and a resistor R1 for receiving the PWM_L signal.

[0012] Preferably, the XOR gate includes chip U2, pin 5 of chip U2 is connected to a 3.3V operating voltage, pin 1 of chip U2 is connected to pin 4 of chip U1, and pin 2 of chip U2 is connected to resistor R1.

[0013] Preferably, the first AND gate includes chip U3, pin 5 of chip U3 is connected to a 3.3V operating voltage, pin 1 of chip U3 is connected to pin 4 of chip U1, pin 2 of chip U3 is connected to pin 2 of chip U2, and the lower MOSFET is connected to pin 4 of chip U3.

[0014] Preferably, the second AND gate includes chip U4, pin 5 of chip U4 is connected to a 3.3V operating voltage, pin 1 of chip U4 receives a PWM_H signal, pin 2 of chip U4 is connected to pin 4 of chip U2, and the upper MOSFET is connected to pin 4 of chip U4.

[0015] Compared with the prior art, the beneficial effects of this utility model are:

[0016] This invention achieves dead time through RC delay and Schmitt's characteristics, avoiding damage to the H-bridge drive circuit caused by simultaneous conduction during operation. It also has lower hardware costs and higher reliability than software implementation. Attached Figure Description

[0017] Figure 1 This is the circuit diagram of this utility model. Detailed Implementation

[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0019] Please see Figure 1 This utility model provides a technical solution: a highly reliable H-bridge dead-time generation circuit, comprising:

[0020] A Schmitt trigger is used to convert curved waveforms into PWM square wave signals and suppress noise and interference in the input signal, which facilitates subsequent digital circuit processing.

[0021] The Schmitt trigger in an H-bridge dead-time generation circuit primarily provides a stable control signal and noise immunity. Schmitt triggers exhibit hysteresis, meaning they only change the output state when the input signal rises from a low level to a certain positive threshold, and only when it falls to a certain negative threshold. This hysteresis characteristic allows Schmitt triggers to effectively suppress noise and interference in the input signal, thus providing a stable control signal.

[0022] The Schmitt trigger includes a chip U1, model number SN74LVC2G17DBVR, and pin 5 of the chip U1 is connected to a 3.3V operating voltage.

[0023] An RC delay circuit connected to a Schmitt trigger to delay the signal;

[0024] The RC delay circuit includes a grounded capacitor C1 connected to pin 2 of chip U1 and a resistor R1 for receiving the PWM_L signal.

[0025] An XOR gate that can distinguish the direction of an input signal and output a response control signal;

[0026] The XOR gate compares two input signals and determines whether they are the same. When the two input signals are different (one is high and the other is low), the XOR gate outputs a high level; when the two input signals are the same (both are high or both are low), the XOR gate outputs a low level. Using the XOR gate as a direction control signal generator, it outputs signals to control the forward and reverse rotation of the motor based on different combinations of input signals.

[0027] The XOR gate includes chip U2, model number SN74LVC1 G86DCKR. Pin 5 of chip U2 is connected to a 3.3V operating voltage. Pin 1 of chip U2 is connected to pin 4 of chip U1. Pin 2 of chip U2 is connected to resistor R1.

[0028] Two AND gates are used to prevent two MOS transistors on the same side of the circuit from conducting simultaneously; the two AND gates include a first AND gate and a second AND gate; a lower MOS transistor is connected to the first AND gate, and an upper MOS transistor is connected to the second AND gate.

[0029] Two AND gates can receive signals from different control sources and output a single control signal through a logical AND operation. This control signal ensures that only one switching element is on at any given time on the same side of the H-bridge. This prevents a short circuit even during the dead time (the period when both control signals are inactive).

[0030] The first AND gate includes chip U3, model number SN74AHC1 G08DBVR. Pin 5 of chip U3 is connected to a 3.3V operating voltage. Pin 1 of chip U3 is connected to pin 4 of chip U1. Pin 2 of chip U3 is connected to pin 2 of chip U2. The lower MOSFET is connected to pin 4 of chip U3.

[0031] The second AND gate includes chip U4, model number SN74AHC1 G08DBVR. Pin 5 of chip U4 is connected to a 3.3V operating voltage, pin 1 of chip U4 receives a PWM_H signal, pin 2 of chip U4 is connected to pin 4 of chip U2, and the upper MOSFET is connected to pin 4 of chip U4.

[0032] The first AND gate and the second AND gate are both electrically connected to the XOR gate, and the XOR gate and the first AND gate are both electrically connected to the Schmitt trigger.

[0033] This circuit can be implemented using two AND gates, one XOR gate, and one Schmitt trigger, resulting in low circuit cost. If PWM_H and PWM_L operate simultaneously, a dead time will occur. However, an RC delay circuit can be used to generate a time delay, slowing down the operation of PWM_L and creating a time difference between it and PWM_H. However, the waveform generated by the RC delay circuit is a curved waveform. Since a square wave PWM signal is actually needed, the Schmitt trigger can convert the curved waveform into a square wave PWM signal.

[0034] The logic of a Schmitt trigger is that when the input voltage is higher than the positive threshold voltage, the output is high; when the input voltage is lower than the negative threshold voltage, the output is low. Thus, an RC delay circuit combined with a Schmitt trigger can achieve a signal delay function.

[0035] The PWM_L signal is passed through an XOR gate and a first AND gate to generate two logically opposite control signals with dead time. The MOSFET control signal and PWM_H are then passed through a second AND gate to enable MOSFET_H.

[0036] In summary, this circuit achieves dead time through the characteristics of RC delay circuit and Schmitt trigger, thus avoiding damage to the H-bridge drive circuit caused by simultaneous conduction during operation.

[0037] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-reliability H-bridge dead-band generation circuit, characterized by, The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on.

2. The high reliability H-bridge dead-band generation circuit of claim 1, wherein: The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on.

3. The high reliability H-bridge dead-band generation circuit of claim 2, wherein: The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on.

4. The high reliability H-bridge dead-band generation circuit of claim 3, wherein: The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on.

5. The high reliability H-bridge dead-band generation circuit of claim 4, wherein: The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on.

6. The high reliability H-bridge dead-band generation circuit of claim 5, wherein: The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to a circuit for preventing two MOS transistors on the same side from being simultaneously turned on. The application relates to

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