Current steering DAC circuit and electronic equipment
By using a parallel structure of current source arrays and a fully differential transimpedance amplifier module, combined with a current shifting module, the current is controlled to center around 0, which solves the problem of limited output voltage swing of the current-controlled DAC and achieves output and accuracy over a larger voltage range.
Patent Information
- Application Number
- CN202520156663.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2035-01-22
AI Technical Summary
The voltage swing of the differential voltage signal output by a traditional current-controlled DAC is limited by the full-scale bias current, making it impossible to achieve a large voltage range output.
It adopts a parallel structure of current source array, combined with a fully differential transimpedance amplifier module and a current shifting module. By setting the common-mode voltage and differential current signal, the current flowing through the resistor generates a differential voltage signal. The current is controlled to be centered at 0, which increases the voltage swing and maintains the output accuracy.
The voltage swing of the differential voltage signal output by the current-steering DAC is increased, avoiding errors in the current source output of the current source array and improving the stability and accuracy of the current source array output.
Smart Images
Figure CN223798226U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of circuit technology, and in particular to a current-controlled DAC circuit and electronic device. Background Technology
[0002] A digital-to-analog converter (DAC) is a signal converter that can convert digital signals into analog signals. A current-steering digital-to-analog converter (CSDAC) is a commonly used type of DAC, offering advantages such as high matching accuracy, fast response speed, and high energy efficiency. Therefore, CSDACs are widely used in computer, communication, audio / video processing, and measurement and control systems.
[0003] The maximum voltage of the differential voltage signal output by a traditional current-controlled DAC is V. out_max =I max ×R L , where V out_max I is the maximum value of the differential voltage signal. max R is the full-scale bias current of the current source array. L This represents the resistance value of the load.
[0004] As can be seen, the maximum value of the differential voltage signal output by a traditional current-controlled DAC is limited by the full-scale bias current, while the minimum value is zero. This limits the voltage swing of the differential voltage signal output by the current-controlled DAC.
[0005] Therefore, how to solve the technical problem of the limited voltage swing of the differential voltage signal output by traditional current-controlled DACs has become an urgent technical problem to be solved in the industry. Utility Model Content
[0006] This invention provides a current-steering DAC circuit and its electronic device, aiming to solve the technical problem that the voltage swing of the differential voltage signal output by the current-steering DAC is limited.
[0007] According to a first aspect of the present invention, an embodiment of the present invention provides a current-driven DAC circuit, comprising: a current source array, consisting of N working units connected in parallel, where N is an integer and N≥2, and each working unit comprising: a current source, a first differential switch, and a second differential switch; wherein:
[0008] The first terminal of the current source receives a first voltage, and the second terminal of the current source is coupled to the non-inverting input terminal and the inverting input terminal of the fully differential transimpedance amplifier module through a first differential switch and a second differential switch, respectively. The control terminals of the first differential switch and the second differential switch both receive corresponding digital code control signals. The working unit controls the corresponding current source to connect to the non-inverting input terminal or the inverting input terminal based on the digital code control signals. The current source array sends differential current signals to the non-inverting input terminal and the inverting input terminal. The differential current signals include a first differential current signal and a second differential current signal.
[0009] The fully differential transimpedance amplifier module has a first resistor connected between its non-inverting input terminal and its non-inverting output terminal, and a second resistor connected between its inverting input terminal and its inverting output terminal. Its common-mode voltage adjustment terminal receives a set voltage. The fully differential transimpedance amplifier module is configured to output a differential voltage signal based on the voltage generated by the current flowing through the first resistor and the second resistor, respectively, using the set voltage as the common-mode voltage. The differential voltage signal includes a first differential voltage signal and a second differential voltage signal.
[0010] A current shifting module, the first and second ends of which are respectively coupled to the positive input terminal and the negative input terminal, and the third end of which is grounded;
[0011] The current shifting module is used to control the first current of the first differential current signal received by the positive input terminal and the second current of the second differential current signal received by the negative input terminal to be centered at 0.
[0012] Optionally, the current shifting module includes: a first current source and a second current source;
[0013] The first terminal of the first current source is coupled to the non-inverting input terminal, the first terminal of the second current source is coupled to the inverting input terminal, and the second terminals of both the first current source and the second current source are grounded.
[0014] The magnitude of the current provided by the first current source and the second current source is 1 / 2 of the full-scale bias current of the current source array.
[0015] Optionally, the first current source includes a first NMOS transistor and a second NMOS transistor; the second current source includes a third NMOS transistor and a fourth NMOS transistor.
[0016] The drain of the first NMOS transistor is coupled to the non-inverting input terminal, the gate of the first NMOS transistor receives a first bias voltage, the source of the first NMOS transistor is coupled to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives a second bias voltage, and the drain of the second NMOS transistor is grounded.
[0017] The drain of the third NMOS transistor is coupled to the inverting input terminal, the gate of the third NMOS transistor receives the first bias voltage, the source of the third NMOS transistor is coupled to the drain of the fourth NMOS transistor, the gate of the third NMOS transistor receives the second bias voltage, and the drain of the fourth NMOS transistor is grounded.
[0018] The first current source is used to control the first current of the first differential current signal received at the non-inverting input terminal to be centered at 0;
[0019] The second current source is used to control the second current of the second differential current signal received at the inverting input terminal to be centered at 0.
[0020] Optionally, the current source includes: a first PMOS transistor and a second PMOS transistor;
[0021] The source of the first PMOS transistor receives a first voltage, the gate of the first PMOS transistor receives a third bias voltage, the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor, the gate of the second PMOS transistor receives a fourth bias voltage, and the drain of the second PMOS transistor is coupled to the non-inverting input terminal and the inverting input terminal respectively through corresponding first differential switches and second differential switches.
[0022] Optionally, the current provided by each working unit of the current source array increases sequentially from the least significant bit to the most significant bit in powers of 2.
[0023] Optionally, the current-steering DAC circuit further includes a second decoding module;
[0024] The input terminal of the second decoding module receives a digitally encoded signal, and the second decoding module is used to generate digital code control signals required by each working unit based on the digitally encoded signal.
[0025] Optionally, the current source array includes a high-order current source array and a low-order current source array, wherein 2 out of the N working units are high-order current source arrays. n -1 of the aforementioned working units serve as the high-level current source array, 2 m Each of the aforementioned working units serves as the low-order current source array, where n and m are both integers greater than or equal to 1;
[0026] The current provided by each working unit in the high-level current source array is of the same magnitude.
[0027] The current provided by each working unit in the low-order current source array increases sequentially from the low-order to the high-order, in powers of 2, and the current provided by the highest-order working unit is 1 / 2 of the current provided by the current sources in the high-order current source array.
[0028] Optionally, the digital code control signal includes a high-order digital code control signal and a low-order digital code control signal; the current steering DAC circuit further includes a first decoding module, the input of which receives the digital code signal, and the first decoding module includes a high-order decoding unit and a low-order decoding unit.
[0029] The high-bit decoding unit is used to generate high-bit digital code control signals required by each working unit in the high-bit current source array based on the digital encoded signal.
[0030] The low-order decoding unit is used to generate low-order digital code control signals required by each working unit in the low-order current source array based on the digital encoded signal.
[0031] Optionally, the fully differential transimpedance amplifier module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first voltage-regulating resistor, and a second voltage-regulating resistor.
[0032] The sources of the first, second, third, and fourth transistors all receive a power supply voltage, and the gates of the first, second, third, and fourth transistors all receive a bias voltage. The drain of the first transistor is coupled to the drain of the fifth transistor, the drain of the second transistor is coupled to the sources of the sixth and seventh transistors, the drain of the third transistor is coupled to the drain of the eighth transistor, the drain of the fourth transistor is coupled to the sources of the ninth and tenth transistors, and the drain and gate of the fifth transistor are coupled to the drains of the sixth and eleventh transistors. The gate of the sixth transistor is the non-inverting input terminal and is coupled to the non-inverting output terminal through the first resistor. The gate of the seventh transistor is the inverting input terminal. The input terminal is coupled to the inverting output terminal through the second resistor. The drains of the seventh transistor and the twelfth transistor are both coupled to the gate of the eighth transistor. The gate of the ninth transistor is coupled to the inverting output terminal and the non-inverting output terminal through the first end of the first voltage regulator and the first end of the second voltage regulator, respectively. The drain of the ninth transistor is coupled to the drain and gate of the thirteenth transistor. The drain of the tenth transistor is coupled to the drain and gate of the fourteenth transistor. The gate of the tenth transistor is a common-mode adjustment terminal, which receives the set voltage. The sources of the fifth, eighth, eleventh, twelfth, thirteenth, and fourteenth transistors are all grounded.
[0033] According to a second aspect of the present invention, an electronic device is provided, comprising the current steering DAC circuit described in any of the first aspects above.
[0034] Compared with the prior art, the technical solution of this utility model embodiment has the following beneficial effects:
[0035] This invention provides a current-steering DAC circuit and electronic device. The current source array in the circuit consists of N parallel working units. Each working unit sends a first differential current signal and a second differential current signal to the non-inverting and inverting input terminals of a fully differential transimpedance amplifier module, respectively. The common-mode voltage adjustment terminal of the fully differential transimpedance amplifier module receives a set voltage. Its non-inverting and inverting input terminals are coupled to the non-inverting and inverting output terminals, respectively, through a first resistor and a second resistor. The first and second terminals of the current shifting module are coupled to the non-inverting and inverting input terminals, respectively. This invention reduces the minimum value of the differential voltage signal output by the current-steering DAC by controlling the first and second currents received at the non-inverting and inverting input terminals to center around 0. By using the set voltage as the common-mode voltage, the differential voltage signal output is based on the voltage generated by the current flowing through the first and second resistors of the differential current signal. This increases the maximum value of the differential voltage signal output by the current-steering DAC. This allows the voltage swing of the differential voltage signal output by the current-controlled DAC to be unaffected by the magnitude of the full-scale bias current of the current source array.
[0036] Furthermore, since the fully differential impedance amplifier module stabilizes the voltages of its non-inverting and inverting input terminals at the set voltage, the drain voltage of the PMOS transistor of the current source is the same when the working unit in the current source array receives different digital code control signals. Therefore, the stability of the current source in the current source array is improved, and errors in the differential current signal output by the current source in the current source array are avoided. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a schematic diagram of a traditional current-controlled DAC circuit.
[0039] Figure 2 This is a schematic diagram of the current-steering DAC circuit in the first embodiment of the present invention;
[0040] Figure 3 This is a schematic diagram of the structure of the first decoding module in the first embodiment of this utility model;
[0041] Figure 4 This is a schematic diagram of the current-rudder DAC circuit in the second embodiment of the present invention;
[0042] Figure 5 This is a schematic diagram of the second decoding structure in the second embodiment of the present invention;
[0043] Figure 6 This is a schematic diagram of the current source structure in the current source array of this utility model;
[0044] Figure 7 This is a schematic diagram of the structure of the fully differential transimpedance amplifier module of this utility model;
[0045] Figure 8 This is a schematic diagram of the structure of a current translation module according to the present invention;
[0046] Figure 9 This is a schematic diagram of another current translation module of this utility model. Detailed Implementation
[0047] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.
[0048] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0049] The technical solution of this utility model will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0050] As described in the background section, this utility model aims to solve the technical problem that the swing of the differential voltage output by a traditional current-controlled DAC is limited. The following description will be provided in conjunction with the accompanying drawings.
[0051] For traditional current-controlled DACs, the maximum value of the differential voltage signal output by the DAC is limited by the full-scale bias current, while the minimum value of the differential voltage output by the DAC is zero. This limits the swing of the differential voltage output by the DAC.
[0052] For details, please refer to Figure 1 , Figure 1 A current-rudder DAC in the prior art is shown. In this embodiment, the method to increase the maximum value of the differential voltage signal output by the conventional current-rudder DAC is to control the current of the differential current signal output by the current source array 100 to be greater than the full-scale bias current.
[0053] However, this method causes the first PMOS transistor MP1 and the second PMOS transistor MP2 in the current source array 100 to enter the linear region, resulting in an error in the magnitude of the output current of the current source 1011, which in turn leads to inaccurate output of the current-driven DAC.
[0054] Furthermore, this method can only increase the maximum value of the first differential voltage signal Vout_n and the second differential voltage signal Vout_p, but cannot reduce the minimum value of the first differential voltage signal Vout_n and the second differential voltage signal Vout_p.
[0055] It should be understood that, Figure 1 R in L1 As the first load, R L2 This is the second load.
[0056] It is evident that how to solve the technical problem of limited differential voltage swing in traditional current-driven DAC outputs while ensuring accurate current-driven DAC output has become an urgent technical issue to be addressed in the industry.
[0057] In view of this, this utility model proposes a current-steering DAC circuit, comprising: a current source array sending differential current signals to the non-inverting and inverting input terminals of a fully differential transimpedance amplifier module based on a digital code control signal; a common-mode voltage adjustment terminal of the fully differential transimpedance amplifier module receiving a set voltage; the non-inverting and inverting input terminals being coupled to the non-inverting and inverting output terminals respectively through a first resistor and a second resistor; and a first and second terminal of a current shifting module being coupled to the non-inverting and inverting input terminals respectively. This utility model reduces the minimum value of the differential voltage signal output by the current-steering DAC by controlling the first and second currents received at the non-inverting and inverting input terminals to center around 0. It outputs a differential voltage signal based on the voltages generated by the current flowing through the first and second resistors, using the set voltage as the common-mode voltage, thereby increasing the maximum value of the differential voltage signal output by the current-steering DAC. This ensures that the voltage swing of the differential voltage signal output by the current-driven DAC is not limited by the magnitude of the full-scale bias current of the current source array, while also maintaining the accuracy of the current-driven DAC output.
[0058] To make the above-mentioned objectives, features and beneficial effects of this utility model more apparent and understandable, the specific embodiments of this utility model will be described in detail below with reference to the accompanying drawings.
[0059] According to one embodiment of the present invention, please refer to 2, the present invention provides a current-controlled DAC circuit, including:
[0060] The current source array 100 is composed of N working units 101 connected in parallel, where N is an integer and N≥2. Each working unit 110 includes: a current source 1011, a first differential switch S1, and a second differential switch S2; wherein:
[0061] The first terminal of the current source 1011 receives a first voltage V1. The second terminal of the current source 1011 is coupled to the non-inverting input terminal and the inverting input terminal of the fully differential transimpedance amplifier module 200 through a first differential switch S1 and a second differential switch S2, respectively. The control terminals of the first differential switch S1 and the second differential switch S2 both receive corresponding digital code control signals DSC. The working unit 101 controls the corresponding current source 1011 to connect to the non-inverting input terminal or the inverting input terminal based on the digital code control signal DSC. The current source array 100 sends differential current signals to the non-inverting input terminal and the inverting input terminal. The differential current signals include a first differential current signal Iip and a second differential current signal Iin.
[0062] The fully differential transimpedance amplifier module 200 has a first resistor R1 connected between its non-inverting input terminal and its non-inverting output terminal, and a second resistor R2 connected between its inverting input terminal and its inverting output terminal. Its common-mode voltage adjustment terminal receives a set voltage Vcm. The fully differential transimpedance amplifier module 200 is configured to output differential voltage signals based on the voltages generated by the first differential current signal Iip and the second differential current signal Iin flowing through the first resistor R1 and the second resistor R2, respectively, using the set voltage Vcm as the common-mode voltage. The differential voltage signals include a first differential voltage signal Vout_n and a second differential voltage signal Vout_p.
[0063] The current shifting module 300 has its first and second terminals coupled to the positive input terminal and the negative input terminal, respectively, and its third terminal grounded to GND.
[0064] The current shifting module 300 is used to control the first current of the first differential current signal Iip received by the positive input terminal and the second current of the second differential current signal Iin received by the negative input terminal to be centered at 0.
[0065] for Figure 2 Both the control terminals of the first differential switch S1 and the second differential switch S2 receive the digital code control signal DSC. Figure 2 The diagram only shows the circuit structure of one working unit 101 in which the control terminal of the first differential switch S1 and the control terminal of the second differential switch S2 receive the digital code control signal DSC. It should be understood that the structures of other working units 101 in which the control terminal of the first differential switch S1 and the control terminal of the second differential switch S2 receive the digital code control signal DSC are the same as those of the working unit 101 described above.
[0066] In actual implementation, the first voltage V1 is used to provide a stable voltage to the first terminal of the current source 1011 in the current source array 100. Those skilled in the art can select a suitable voltage as needed.
[0067] As an example, the set voltage Vcm is usually set to 1 / 2 of the first voltage, but of course, this invention is not limited thereto.
[0068] Now Figure 2 The working principle of this utility model will be further explained based on this.
[0069] Because the current shifting module 300 reduces the current of the first differential current signal Iip to half of the full-scale bias current Imax of the current source array 100, the first current of the first differential current signal Iip is centered at 0. Therefore, the voltage swing of the first differential voltage signal Vout_n output from the non-inverting output terminal of the current rudder DAC is shifted from 0 to Imax×R1.
[0070] Simultaneously, because the current shifting module 300 reduces the current of the second differential current signal Iin to half of the full-scale bias current Imax of the current source array 100, the second current of the second differential current signal Iin is centered at 0. Therefore, the voltage swing of the first differential voltage signal Vout_p output from the inverting output terminal of the current rudder DAC is shifted from 0 to Imax×R2.
[0071] It can be seen that this invention reduces the minimum voltage of the differential voltage signal output by the current-controlled DAC.
[0072] The full-scale bias current is the maximum current that the current source array 100 can provide when all current sources 1011 in the current source array 100 guarantee output accuracy and output current to the positive input terminal or all current to the negative input terminal.
[0073] Since the common-mode voltage of the fully differential transimpedance amplifier module 200 is the set voltage Vcm, the voltage swing of the output first differential voltage signal Vout_n, based on the voltage generated by the first differential current signal Iip flowing through the first resistor R1, is...
[0074]
[0075] Simultaneously, based on the voltage generated by the second differential current signal Iin flowing through the second resistor R2, the voltage swing of the output second differential voltage signal Vout_p is...
[0076]
[0077] As can be seen, this invention only requires increasing the set voltage to increase the maximum value of the output differential voltage signal. Therefore, even when the full-scale bias current output by the current source array 100 is relatively small, this invention can still meet the application scenarios requiring a larger output differential voltage signal.
[0078] In summary, this invention reduces the minimum value of the differential voltage signal output by the current-steering DAC by controlling the first and second currents of the differential current signals received at the positive and negative input terminals to center around 0. By using a set voltage as the common-mode voltage, the differential voltage signal is output based on the voltages generated by the current flowing through the first and second resistors of the differential current signal. This increases the maximum value of the differential voltage signal output by the current-steering DAC. Therefore, the voltage swing of the differential voltage signal output by the current-steering DAC is not limited by the magnitude of the full-scale bias current of the current source array, while also ensuring the accuracy of the current-steering DAC output.
[0079] It should be understood that this utility model does not limit the specific composition of the current source array 100.
[0080] For a specific implementation method, please refer to [link / reference]. Figure 2 The current provided by each working unit 101 of the current source array 100 increases sequentially from the least significant bit to the most significant bit in powers of 2.
[0081] To control the current supplied to each working unit 101, please refer to the following specific implementation method: Figure 3 The current-rudder DAC circuit also includes a first decoding module 400;
[0082] The first decoding module 400 receives a digital code signal DS at its input terminal, and the first decoding module 400 is used to generate a digital code control signal DSC required by each working unit 101 based on the digital code signal DS.
[0083] Each working unit 101 is controlled by the corresponding digital code control signal DSC. The working unit 101 is configured to control the corresponding current source to be coupled to the non-inverting input terminal or the inverting input terminal based on the digital code control signal DSC.
[0084] Figure 3 Both the control terminals of the first differential switch S1 and the second differential switch S2 receive the digital code control signal DSC sent by the first decoding module 400. Figure 3 The diagram only shows the circuit structure of one working unit 101 in which the control terminal of the first differential switch S1 and the control terminal of the second differential switch S2 receive the digital code control signal DSC sent by the first decoding module 400. It should be understood that the structures of other working units 101 in which the control terminals of the first differential switch S1 and the second differential switch S2 receive the digital code control signal DSC sent by the first decoding module 400 are the same as those of the working unit 101 described above.
[0085] As another specific implementation method, please refer to Figure 4The current source array 100 includes a high-order current source array 110 and a low-order current source array 120, wherein 2 out of the N working units 101 n -1 of the aforementioned working units 101 serve as the high-level current source array 110, 2 m Each of the aforementioned working units 101 serves as the low-order current source array 120, where n and m are both integers greater than or equal to 1;
[0086] The current provided by each working unit 101 in the high-level current source array 110 is of the same magnitude; the current provided by each working unit 101 in the low-level current source array 110 increases sequentially from low to high level in powers of 2, and the current provided by the highest working unit 101 is 1 / 2 of the current provided by the current source 1011 in the high-level current source array 110.
[0087] in, Figure 4 Medium current source array 100 is Figure 2 Another implementation of the medium current source array 100 is provided. Of course, this utility model is not limited to this. The current source array 100 can also be a current source array 100 in which the current source 1011 in each working unit 101 outputs the same current. Those skilled in the art can choose the appropriate type of current source array 100 as needed.
[0088] To control the current supplied to each working unit 101, please refer to the following specific implementation method: Figure 5 The digital code control signal DSC includes the high-order digital code control signal DSC. H and low-order digital code control signal DSC H The current-steering DAC circuit further includes a second decoding module 500. The input terminal of the second decoding module 500 receives a digitally encoded signal DS. The second decoding module 500 includes a high-order decoding unit 501 and a low-order decoding unit 502.
[0089] The high-order decoding unit 501 is used to generate, based on the digital encoded signal DS, the high-order digital code control signal DSC required by each working unit 101 in the high-order current source array 110. H ;
[0090] The low-order decoding unit 502 is used to generate low-order digital code control signals DSC required by each working unit 101 in the low-order current source array 120 based on the digital encoded signal DS. L .
[0091] Each working unit 101 in the high-level current source array 110 is controlled by the corresponding high-level digital code control signal DSC. HEach working unit 101 in the low-order current source array 120 is controlled by the corresponding low-order digital code control signal DSC. L The working unit 101 is configured to: control the DSC based on the high-order digital code. H Or the low-order digital code control signal DSC L The corresponding current source 1011 is coupled to the positive or negative input terminal.
[0092] Figure 5 In the high-order current source array 110, the control terminals of the first differential switch S1 and the second differential switch S2 both receive the high-order digital code control signal DSC sent by the high-order decoding unit 501. H In the low-order current source array 120, both the control terminals of the first differential switch S1 and the second differential switch S2 receive the low-order digital code control signal DSC sent by the low-order decoding unit 502. L , Figure 5 Only the control terminals of the first differential switch S1 and the second differential switch S2 in one working unit 101 of the high-order current source array 110 are shown receiving the high-order digital code control signal DSC from the high-order decoding unit 501. H The circuit structure, and the control terminals of the first differential switch S1 and the second differential switch S2 in a working unit 101 of the low-order current source array 120 receive the low-order digital code control signal DSC from the low-order decoding unit 502. L Regarding the circuit structure, it should be understood that in the high-order current source array 110, the control terminals of the other first differential switches S1 and the control terminal of one second differential switch S2 all receive the high-order digital code control signal DSC sent by the high-order decoding unit 501. H The control terminals of the other first differential switch S1 and one of the second differential switches S2 both receive the low-order digital code control signal DSC sent by the low-order decoding unit 502. L .
[0093] For one specific implementation method, please refer to Figure 6 The current source 1011 includes: a first PMOS transistor MP1 and a second PMOS transistor MP2;
[0094] The source of the first PMOS transistor MP1 receives a first voltage V1, the gate of the first PMOS transistor MP1 receives a third bias voltage VBP, the drain of the first PMOS transistor MP1 is coupled to the source of the second PMOS transistor MP2, the gate of the second PMOS transistor MP2 receives a fourth bias voltage VBP_CAS, and the drain of the second PMOS transistor MP2 is coupled to the non-inverting input terminal and the inverting input terminal respectively through the corresponding first differential switch S1 and the second differential switch S2.
[0095] The range of the third bias voltage VBP and the fourth bias voltage VBP_CAS is 1V to 3V. It should be understood that this utility model is not limited to this range. The third bias voltage VBP and the fourth bias voltage VBP_CAS are sufficient to enable the first PMOS transistor MP1 and the second PMOS transistor MP2 to be turned on.
[0096] Because the magnitudes of the first differential current signal Iip and the second differential current signal Iin sent by the current source array 100 to the non-inverting input terminal and to the inverting output terminal are different, the voltage magnitudes of the non-inverting input terminal and the inverting input terminal are different. Furthermore, because the digital encoding signal DS received by each working unit 101 from the digital code control signal DSC is different, the input ports connected to the current source 1011 in the fully differential transimpedance amplifier module 200 are different (the input ports being the non-inverting input terminal and the inverting input terminal). Therefore, when the digital encoding signal DS received from the digital code control signal DSC is different, the drain voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 in each current source will change, causing the current source 1011 to malfunction.
[0097] Therefore, as a preferred implementation method, please refer to... Figure 7 The fully differential transimpedance amplifier module 200 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a first voltage regulator resistor R3, and a second voltage regulator resistor R4.
[0098] The sources of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 all receive a power supply voltage VDD. The gates of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 all receive a bias voltage VB. The drain of the first transistor M1 is coupled to the drain of the fifth transistor M5. The drain of the second transistor M2 is coupled to the source of the sixth transistor M6 and the source of the seventh transistor M7. The drain of the third transistor M3 is coupled to the drain of the eighth transistor M8. The drain of the fourth transistor M4 is coupled to the source of the ninth transistor M9 and the source of the tenth transistor M10. The drain and gate of the fifth transistor M5 are coupled to the drain of the sixth transistor M6 and the drain of the eleventh transistor M11. The gate of the sixth transistor M6 is the non-inverting input terminal and is coupled to the non-inverting output terminal through the first resistor R1. The gate of the seventh transistor M7 is the inverting input terminal. The seventh transistor M7 and the twelfth transistor M12 are both coupled to the gate of the eighth transistor M8 via the second resistor R2. The gate of the ninth transistor M9 is connected to the first terminal of the first voltage regulator R3 and the first terminal of the second voltage regulator R4. The second terminal of the first voltage regulator R3 and the second terminal of the second voltage regulator R4 are respectively coupled to the inverting output terminal out2 and the non-inverting output terminal. The drain of the ninth transistor M9 is coupled to the drain and gate of the thirteenth transistor M13. The drain of the tenth transistor M10 is coupled to the drain and gate of the fourteenth transistor M14. The gate of the tenth transistor M10 is a common-mode adjustment terminal, which receives the set voltage Vcm. The sources of the fifth transistor M5, the eighth transistor M8, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13, and the fourteenth transistor M14 are all grounded to GND.
[0099] As an example, the bias voltage VB and the power supply voltage VDD are sufficient to enable the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 to be turned on. This invention does not impose any restrictions on the power supply voltage VDD and the bias voltage VB.
[0100] The fully differential transimpedance amplifier module 200 controls the voltages at the non-inverting and inverting input terminals to a set voltage Vcm. Therefore, even when the digital codes of the received digital code control signal DSC differ, the drain voltages of the first PMOS transistor MP1 and the second PMOS transistor MP2 in each current source 1011 remain constant. This ensures that the magnitude of the current source 1011 is not affected by the differences in the digital code control signal DSC, improving the dynamic performance of the current-controlled DAC.
[0101] It should be understood that, Figure 9 The structure of the fully differential transimpedance amplifier module 200 described above is only an example, and this utility model does not limit the specific structure of the fully differential transimpedance amplifier module 200.
[0102] The internal structure of the current shifting module 300 will now be further described.
[0103] Please refer to Figure 8 As one embodiment, the current shifting module 300 includes: a first current source I1 and a second current source I2;
[0104] The first terminal of the first current source I1 is coupled to the non-inverting input terminal, the first terminal of the second current source I2 is coupled to the inverting input terminal, and the second terminals of the first current source I1 and the second current source I2 are both grounded to GND.
[0105] The magnitudes of the currents provided by the first current source I1 and the second current source I2 are both 1 / 2 of the full-scale bias current of the current source array 100.
[0106] As one specific embodiment, please refer to Figure 9 The first current source I1 includes a first NMOS transistor MN1 and a second NMOS transistor MN2; the second current source I2 includes a third NMOS transistor MN3 and a fourth NMOS transistor MN4.
[0107] The drain of the first NMOS transistor MN1 is coupled to the non-inverting input terminal, the gate of the first NMOS transistor MN1 receives the first bias voltage VBN_CS, the source of the first NMOS transistor MN1 is coupled to the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2 receives the second bias voltage VBN, and the drain of the second NMOS transistor MN2 is grounded.
[0108] The drain of the third NMOS transistor MN3 is coupled to the inverting input terminal, the gate of the third NMOS transistor MN3 receives the first bias voltage VBN_CS, the source of the third NMOS transistor MN3 is coupled to the drain of the fourth NMOS transistor MN4, the gate of the third NMOS transistor MN3 receives the second bias voltage VBN, and the drain of the fourth NMOS transistor MN4 is grounded to GND.
[0109] The first current source I1 is used to control the first current of the first differential current signal Iip received at the non-inverting input terminal to be centered at 0;
[0110] The second current source I2 is used to control the second current of the second differential current signal Iin received at the inverting input terminal to be centered at 0.
[0111] For example, the first bias voltage VBN_CS and the second bias voltage VBN need to be sufficient to turn on the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor.
[0112] In summary, the current-steering DAC circuit provided by this invention includes: a current source array composed of N working units connected in parallel; each working unit sends a first differential current signal and a second differential current signal to the non-inverting and inverting input terminals of a fully differential transimpedance amplifier module, respectively; the common-mode voltage adjustment terminal of the fully differential transimpedance amplifier module receives a set voltage; its non-inverting and inverting input terminals are coupled to the non-inverting and inverting output terminals respectively through a first resistor and a second resistor; and the first and second terminals of a current shifting module are coupled to the non-inverting and inverting input terminals, respectively. This invention reduces the minimum value of the differential voltage signal output by the current-steering DAC by controlling the first and second currents of the differential current signals received at the non-inverting and inverting input terminals to center around 0. By using the set voltage as the common-mode voltage, the differential voltage signals output are based on the voltages generated by the differential current signals flowing through the first and second resistors, respectively. This increases the maximum value of the differential voltage signal output by the current-steering DAC. This allows the voltage swing of the differential voltage signal output by the current-controlled DAC to be unaffected by the magnitude of the full-scale bias current of the current source array, while also ensuring the accuracy of the current-controlled DAC output. Furthermore, by controlling the voltages at the non-inverting and inverting input terminals to a set voltage, this invention ensures that the magnitude of the current source is not affected by differences in the digital code control signal, thereby improving the dynamic performance of the current-controlled DAC.
[0113] Furthermore, this invention also provides an electronic device, including the current-controlled DAC circuit described in any of the preceding claims. For example, the electronic device includes, but is not limited to, cameras, mobile phones, and unmanned aerial vehicles.
[0114] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A current-controlled DAC circuit, characterized in that, include: The current source array consists of N working units connected in parallel, where N is an integer and N≥2. Each working unit includes: a current source, a first differential switch, and a second differential switch; wherein: The first terminal of the current source receives a first voltage, and the second terminal of the current source is coupled to the non-inverting input terminal and the inverting input terminal of the fully differential transimpedance amplifier module through a first differential switch and a second differential switch, respectively. The control terminals of the first differential switch and the second differential switch both receive corresponding digital code control signals. The working unit controls the corresponding current source to connect to the non-inverting input terminal or the inverting input terminal based on the digital code control signals. The current source array sends differential current signals to the non-inverting input terminal and the inverting input terminal. The differential current signals include a first differential current signal and a second differential current signal. The fully differential transimpedance amplifier module has a first resistor connected between its non-inverting input terminal and its non-inverting output terminal, and a second resistor connected between its inverting input terminal and its inverting output terminal. Its common-mode voltage adjustment terminal receives a set voltage. The fully differential transimpedance amplifier module is configured to output a differential voltage signal based on the voltage generated by the current flowing through the first resistor and the second resistor, respectively, using the set voltage as the common-mode voltage. The differential voltage signal includes a first differential voltage signal and a second differential voltage signal. A current shifting module, the first and second ends of which are respectively coupled to the positive input terminal and the negative input terminal, and the third end of which is grounded; The current shifting module is used to control the first current of the first differential current signal received by the positive input terminal and the second current of the second differential current signal received by the negative input terminal to be centered at 0.
2. The current-driven DAC circuit as described in claim 1, characterized in that, The current translation module includes: a first current source and a second current source; The first terminal of the first current source is coupled to the non-inverting input terminal, the first terminal of the second current source is coupled to the inverting input terminal, and the second terminals of both the first current source and the second current source are grounded. The magnitude of the current provided by the first current source and the second current source is 1 / 2 of the full-scale bias current of the current source array.
3. The current-controlled DAC circuit as described in claim 2, characterized in that, The first current source includes a first NMOS transistor and a second NMOS transistor; the second current source includes a third NMOS transistor and a fourth NMOS transistor; The drain of the first NMOS transistor is coupled to the non-inverting input terminal, the gate of the first NMOS transistor receives a first bias voltage, the source of the first NMOS transistor is coupled to the drain of the second NMOS transistor, the gate of the second NMOS transistor receives a second bias voltage, and the drain of the second NMOS transistor is grounded. The drain of the third NMOS transistor is coupled to the inverting input terminal, the gate of the third NMOS transistor receives the first bias voltage, the source of the third NMOS transistor is coupled to the drain of the fourth NMOS transistor, the gate of the third NMOS transistor receives the second bias voltage, and the drain of the fourth NMOS transistor is grounded. The first current source is used to control the first current of the first differential current signal received at the non-inverting input terminal to be centered at 0; The second current source is used to control the second current of the second differential current signal received at the inverting input terminal to be centered at 0.
4. The current-controlled DAC circuit as described in claim 1, characterized in that, The current source includes: a first PMOS transistor and a second PMOS transistor; The source of the first PMOS transistor receives a first voltage, the gate of the first PMOS transistor receives a third bias voltage, the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor, the gate of the second PMOS transistor receives a fourth bias voltage, and the drain of the second PMOS transistor is coupled to the non-inverting input terminal and the inverting input terminal respectively through corresponding first differential switches and second differential switches.
5. The current-controlled DAC circuit as described in claim 4, characterized in that, The current provided by each working unit of the current source array increases sequentially from the least significant bit to the most significant bit in powers of 2.
6. The current-controlled DAC circuit as described in claim 5, characterized in that, The current-rudder DAC circuit also includes a second decoding module; The input terminal of the second decoding module receives a digitally encoded signal, and the second decoding module is used to generate digital code control signals required by each working unit based on the digitally encoded signal.
7. The current-driven DAC circuit as described in claim 4, characterized in that, The current source array includes a high-order current source array and a low-order current source array, wherein there are 2 in the N working units. n -1 of the aforementioned working units serve as the high-level current source array, 2 m Each of the aforementioned working units serves as the low-order current source array, where n and m are both integers greater than or equal to 1; The current provided by each working unit in the high-level current source array is of the same magnitude. The current provided by each working unit in the low-order current source array increases sequentially from the low-order to the high-order, in powers of 2, and the current provided by the highest-order working unit is 1 / 2 of the current provided by the current sources in the high-order current source array.
8. The current-controlled DAC circuit as described in claim 7, characterized in that, The digital code control signal includes a high-order digital code control signal and a low-order digital code control signal; the current steering DAC circuit also includes a first decoding module, the input of which receives the digital code signal, and the first decoding module includes a high-order decoding unit and a low-order decoding unit. The high-bit decoding unit is used to generate high-bit digital code control signals required by each working unit in the high-bit current source array based on the digital encoded signal. The low-order decoding unit is used to generate low-order digital code control signals required by each working unit in the low-order current source array based on the digital encoded signal.
9. The current-driven DAC circuit as described in claim 1, characterized in that, The fully differential transimpedance amplifier module includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a first voltage-regulating resistor, and a second voltage-regulating resistor. The sources of the first, second, third, and fourth transistors all receive a power supply voltage, and the gates of the first, second, third, and fourth transistors all receive a bias voltage. The drain of the first transistor is coupled to the drain of the fifth transistor, the drain of the second transistor is coupled to the sources of the sixth and seventh transistors, the drain of the third transistor is coupled to the drain of the eighth transistor, the drain of the fourth transistor is coupled to the sources of the ninth and tenth transistors, and the drain and gate of the fifth transistor are coupled to the drains of the sixth and eleventh transistors. The gate of the sixth transistor is the non-inverting input terminal and is coupled to the non-inverting output terminal through the first resistor. The gate of the seventh transistor is the inverting input terminal. The input terminal is coupled to the inverting output terminal through the second resistor. The drains of the seventh transistor and the twelfth transistor are both coupled to the gate of the eighth transistor. The gate of the ninth transistor is coupled to the inverting output terminal and the non-inverting output terminal through the first end of the first voltage regulator and the first end of the second voltage regulator, respectively. The drain of the ninth transistor is coupled to the drain and gate of the thirteenth transistor. The drain of the tenth transistor is coupled to the drain and gate of the fourteenth transistor. The gate of the tenth transistor is a common-mode adjustment terminal, which receives the set voltage. The sources of the fifth, eighth, eleventh, twelfth, thirteenth, and fourteenth transistors are all grounded.
10. An electronic device, characterized in that, Includes the current-steering DAC circuit as described in any one of claims 1-9.