Full-bridge gate driving circuit and load driving device

Abstract

The utility model provides a full-bridge gate drive circuit and a load drive device, the circuit comprises a first drive circuit, a second drive circuit and a full-bridge circuit, the full-bridge circuit comprises a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube; the input end of the first driving circuit receives a PWM control signal, and the output end of the first driving circuit is connected with the grid electrode of the first MOS tube and the grid electrode of the fourth MOS tube. The input end of the second driving circuit is connected with a PWM control signal, and the output end of the second driving circuit is connected with the grid electrode of the second MOS tube and the grid electrode of the third MOS tube; the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are electrically connected with the power supply. Therefore, commutation control can be realized by externally inputting a single-path PWM pulse signal, and the method is suitable for a low-voltage logic signal control system; and a double-side dead zone is configured to prevent same-side conduction, so that the safety of the control system is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to drive circuit technical field especially relates to a full bridge gate drive circuit and load driving device. BACKGROUND

[0002] At present, in the direct current motor control system, the gate drive circuit for controlling the power switch tube device and the discrete power switch tube device are connected into a full bridge or half bridge circuit.

[0003] Among them, the commonly used integrated gate driver integrates the gate drive circuit miniaturization in a device, and at least 2 control signals are needed for control, and more I / O port resources will be occupied in the single-chip microcomputer control application, and the control mode is relatively complex, and it is inconvenient to debug the fault point, and additional operation and maintenance cost and customization cost will be generated in the subsequent operation, and it is not flexible enough. UTILITY MODEL CONTENTS

[0004] Based on this, the application provides a full bridge gate drive circuit and load driving device, which is used to solve the technical problems of complex control mode, safety hazards and high maintenance cost of the above-mentioned integrated full bridge drive circuit.

[0005] In a first aspect, the application provides a full bridge gate drive circuit, comprising: a first drive circuit, a second drive circuit and a full bridge circuit, the full bridge circuit comprising a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a load; wherein,

[0006] The input end of the first drive circuit receives a PWM control signal, and the output end of the first drive circuit is connected with the gate of the first MOS tube and the gate of the fourth MOS tube respectively; the input end of the second drive circuit is connected with the PWM control signal, and the output end of the second drive circuit is connected with the gate of the second MOS tube and the gate of the third MOS tube respectively; the drain of the first MOS tube and the drain of the second MOS tube are electrically connected with a power supply respectively; one end of the load is connected between the source of the first MOS tube and the drain of the third MOS tube, and the other end of the load is connected between the source of the second MOS tube and the drain of the fourth MOS tube;

[0007] The first drive circuit is used for driving the conduction and the closing of the first MOS tube and the fourth MOS tube according to the level of the PWM control signal;

[0008] The second drive circuit is used for receiving the PWM control signal and driving the conduction and the closing of the second MOS tube and the third MOS tube according to the level of the PWM control signal.

[0009] According to the aspect and any possible implementation manner above, further provided is an implementation manner, when the first MOS tube and the fourth MOS tube are turned on and the second MOS tube and the third MOS tube are turned off, the full-bridge circuit is in a forward conduction state to realize forward driving load operation; when the second MOS tube and the third MOS tube are turned on and the first MOS tube and the fourth MOS tube are turned off, the full-bridge circuit is in a reverse conduction state to realize reverse driving load operation.

[0010] According to the aspect and any possible implementation manner above, further provided is an implementation manner, the full-bridge gate drive circuit further comprises an inverter; an input end of the inverter receives the PWM control signal, and output ends of the inverter are connected to input ends of the first drive circuit and the second drive circuit respectively; the inverter is configured to perform inversion processing on a polarity of the received PWM control signal.

[0011] According to the aspect and any possible implementation manner above, further provided is an implementation manner, the first drive circuit comprises a first control circuit and a fourth control circuit, the first control circuit comprises a first delay circuit, a first sub-inverter, a second sub-inverter and a first level conversion circuit; wherein an input end of the first delay circuit is connected to an output end of the inverter, an output end of the first delay circuit is connected to an input end of the first sub-inverter, an output end of the first sub-inverter is connected to an input end of the second sub-inverter, an output end of the second sub-inverter is connected to an input end of the first level conversion circuit, and an output end of the first level conversion circuit is connected to a gate of the first MOS tube; an input end of the fourth control circuit is connected to an output end of the second sub-inverter, and an output end of the fourth control circuit is connected to a gate of the fourth MOS tube; the first delay circuit is configured to delay a power-on time of the PWM control signal; the first sub-inverter and the second sub-inverter are configured to perform inversion processing on a polarity of the PWM control signal; and the first level conversion circuit is an OC gate circuit configured to convert a level of the PWM control signal.

[0012] According to the aspect and any possible implementation manner above, further provided is an implementation manner, the first delay circuit comprises a first resistor, a first capacitor and a first diode; wherein the first resistor and the first diode are connected in parallel, input ends of the first resistor and the first diode are connected to the output end of the inverter, a first output end of the first resistor and the first diode is connected to an input end of the first capacitor, a second output end of the first resistor and the first diode is connected to an input end of the first sub-inverter, and an output end of the first capacitor is connected to ground; the first delay circuit adjusts a length of the power-on time, and the length of the power-on time is positively correlated with a resistance value of the first resistor and a capacitance value of the first capacitor.

[0013] As the above aspect and any possible implementation, further provides an implementation, the second driving circuit includes a second control circuit and a third control circuit, the third control circuit includes a third inverter, a second delay circuit, a fourth inverter and a fifth inverter, and the second control circuit includes a second level conversion circuit;Wherein, the input end of the third inverter is connected to the output end of the inverter, the output end of the third inverter is connected to the input end of the second delay circuit, the output end of the second delay circuit is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the gate of the third MOS tube;The input end of the second level conversion circuit is connected to the output end of the fifth inverter, and the output end of the second level conversion circuit is connected to the gate of the second MOS tube;The second delay circuit is used to delay the power-on time of the PWM control signal;The second level conversion circuit is an OC gate circuit, which is used to convert the level of the PWM control signal.

[0014] As the above aspect and any possible implementation, further provides an implementation, the second delay circuit is composed of a second resistor, a second capacitor and a second diode;Wherein, the second resistor and the second diode are connected in parallel, the input end of the second resistor and the second diode is connected to the output end of the third inverter, the first output end of the second resistor and the second diode is connected to the input end of the second capacitor, the second output end of the second resistor and the second diode is connected to the input end of the fourth sub-inverter, and the output end of the second capacitor is grounded;The second delay circuit adjusts the length of the power-on time, and the resistance value of the second resistor and the capacitance value of the second capacitor are positively correlated.

[0015] As the above aspect and any possible implementation, further provides an implementation, the full-bridge gate driving circuit further includes a bridge-off circuit, the bridge-off circuit includes an enable signal generator, a first OC transmission gate and a second OC transmission gate;Wherein, the first OC transmission gate and the second OC transmission gate are connected in parallel, the input end of the first OC transmission gate and the second OC transmission gate is connected to the enable signal generator respectively, the output end of the first OC transmission gate is connected to the output end of the first level conversion circuit, and the output end of the second OC transmission gate is connected to the output end of the second level conversion circuit;The enable signal generator is used to output an enable signal to the first OC transmission gate and the second OC transmission gate;The first OC transmission gate and the second OC transmission gate are used to perform a line and operation on the enable signal and the PWM control signal of the high-side MOS tube of the full-bridge circuit, so as to control the switching state of the full-bridge circuit through the PWM control signal when the enable signal is a high-level signal, or to close the full-bridge circuit when the enable signal is a low-level signal.

[0016] In any of the above aspects and any possible implementation, further implementation is provided, the enable signal generator comprises a single-chip microcomputer and a monostable trigger, wherein an output end of the single-chip microcomputer is connected to input ends of the first OC transmission gate and the second OC transmission gate, an input pin of the monostable trigger receives a trigger signal, and an output pin of the monostable trigger is connected to the input ends of the first OC transmission gate and the second OC transmission gate; the monostable trigger is configured to output a high-level enable signal to the first OC transmission gate and the second OC transmission gate according to the received trigger signal, and output a low-level enable signal when the trigger signal is not received within a preset time length; and the single-chip microcomputer is configured to generate the enable signal.

[0017] In a second aspect, the embodiments of the present application also provide a load driving device, the load driving device comprising the full-bridge gate driving circuit according to any one of the first aspect.

[0018] In the present application, the full-bridge gate driving circuit comprises a first driving circuit, a second driving circuit and a full-bridge circuit, the full-bridge circuit comprising a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a load; wherein an input end of the first driving circuit receives a PWM control signal, output ends of the first driving circuit are connected to a gate of the first MOS transistor and a gate of the fourth MOS transistor respectively; an input end of the second driving circuit is connected to the PWM control signal, and output ends of the second driving circuit are connected to a gate of the second MOS transistor and a gate of the third MOS transistor respectively; drain electrodes of the first MOS transistor and the second MOS transistor are electrically connected to a power supply respectively; one end of the load is connected between a source electrode of the first MOS transistor and a drain electrode of the third MOS transistor, and the other end of the load is connected between a source electrode of the second MOS transistor and a drain electrode of the fourth MOS transistor. In this way, commutation control can be realized by externally inputting a single-channel PWM pulse signal, which is suitable for a low-voltage logic signal control system; and a double-side dead zone is configured to prevent same-side conduction and improve the safety of the control system. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0020] Figure 1 is a structural schematic diagram of a full-bridge gate driving circuit provided by the embodiments of the present application;

[0021] Figure 2 is a circuit topology diagram of a full-bridge gate driving circuit provided by the embodiments of the present application;

[0022] Figure 3 is a timing diagram of a full-bridge gate drive circuit provided by an embodiment of the present application;

[0023] Figure 4 is a bridge-off circuit topology diagram of a full-bridge gate drive circuit provided by an embodiment of the present application;

[0024] Figure 5 is a timing diagram of another full-bridge gate drive circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative work fall within the scope of protection of the present application.

[0026] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0027] It should be understood that the term "and / or" herein is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this paper represents that the front and rear associated objects are a "or" relationship.

[0028] "Multiple" appearing in the embodiments of the present application means two or more. "Connection" appearing in the embodiments of the present application means direct connection or indirect connection and various connection modes to achieve communication between devices, which is not limited by the embodiments of the present application.

[0029] Reference to "embodiments" in this document means that the specific features, structures, or characteristics described in conjunction with the embodiments can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it mutually exclusive or alternative to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0030] First, the related terms involved in the present application are introduced.

[0031] OC gate (Open-Collector): Open collector transmission gate device with level conversion function.

[0032] Line and operation relationship: a circuit operation relationship, the specific logic is that if all lines in the two short-circuit lines are high level, the short-circuit node line outputs high level; if one side is low level or both sides are low level, the short-circuit node line outputs low level.

[0033] Please refer to Figure 1 , Figure 1 is a structure diagram of a full-bridge gate drive circuit provided by an embodiment of the present application, as shown in Figure 1 , comprising: a first drive circuit 110, a second drive circuit 120 and a full-bridge circuit, the full-bridge circuit comprising a first MOS tube 131, a second MOS tube 132, a third MOS tube 133, a fourth MOS tube 134 and a load 135; wherein the input end of the first drive circuit 110 receives a PWM control signal, the output end of the first drive circuit 110 is connected with the gate of the first MOS tube 131 and the gate of the fourth MOS tube 134 respectively; the input end of the second drive circuit 120 is connected with the PWM control signal, the output end of the second drive circuit 120 is connected with the gate of the second MOS tube 132 and the gate of the third MOS tube 133 respectively; the drain of the first MOS tube 131 and the drain of the second MOS tube 132 are electrically connected with a power supply respectively; one end of the load 135 is connected between the source of the first MOS tube 131 and the drain of the third MOS tube 133, the other end of the load 135 is connected between the source of the second MOS tube 132 and the drain of the fourth MOS tube 134; the first drive circuit 110 is used for driving the conduction and the closing of the first MOS tube 131 and the fourth MOS tube 134 according to the level of the PWM control signal; the second drive circuit 120 is used for receiving the PWM control signal and driving the conduction and the closing of the second MOS tube 132 and the third MOS tube 133 according to the level of the PWM control signal. Thus, only one PWM pulse signal needs to be input externally to realize the commutation control of the load, and the control mode is simple and efficient.

[0034] Wherein, when the first MOS tube and the fourth MOS tube are turned on and the second MOS tube and the third MOS tube are turned off, the full-bridge circuit is in a forward conduction state to realize forward driving load work; when the second MOS tube and the third MOS tube are turned on and the first MOS tube and the fourth MOS tube are turned off, the full-bridge circuit is in a reverse conduction state to realize reverse driving load work.

[0035] Specifically, please refer toFigure 2 , Figure 2 is a circuit topology of a full-bridge gate drive circuit provided by an embodiment of the present application, Figure 2 The first MOS transistor is referred to as Q1, the second MOS transistor is referred to as Q2, the third MOS transistor is referred to as Q3, and the fourth MOS transistor is referred to as Q4 in the full-bridge gate drive circuit, which further includes an inverter U3-A. As shown in Figure 2 The PWM control signal passes through the resistor R25, and the working voltage VDD passes through the resistor R26 to be connected to the No. 1 interface of the inverter U3-A. The working voltage VDD is connected to the capacitor C21 and the No. 14 interface of the inverter U3-A. The other end of the capacitor C21 is grounded. The No. 7 interface of the inverter U3-A is grounded. The No. 2 interface of the inverter U3-A is connected to the input end of the first drive circuit and the second drive circuit.

[0036] The input end of the inverter U3-A receives the PWM control signal. The output end of the inverter U3-A is connected to the input end of the first drive circuit and the input end of the second drive circuit, respectively. The inverter U3-A is used to perform inversion processing on the polarity of the received PWM control signal.

[0037] In one possible example, the first drive circuit includes a first control circuit and a fourth control circuit. The first control circuit includes a first delay circuit, a first sub-inverter, a second sub-inverter, and a first level conversion circuit. The input end of the first delay circuit is connected to the output end of the inverter. The output end of the first delay circuit is connected to the input end of the first sub-inverter. The output end of the first sub-inverter is connected to the input end of the second sub-inverter. The output end of the second sub-inverter is connected to the input end of the first level conversion circuit. The output end of the first level conversion circuit is connected to the gate of the first MOS transistor. The input end of the fourth control circuit is connected to the output end of the second sub-inverter. The output end of the fourth control circuit is connected to the gate of the fourth MOS transistor. The first delay circuit is composed of a first resistor R27, a first capacitor C22, and a first diode D6. The first resistor R27 is connected in parallel with the first diode D6. The input end of the first resistor R27 and the first diode D6 is connected to the output end of the inverter. The first output end of the first resistor R27 and the first diode D6 is connected to the input end of the first capacitor C22. The second output end of the first resistor R27 and the first diode D6 is connected to the input end of the first sub-inverter U3-B. The output end of the first capacitor C22 is grounded.

[0038] The first delay circuit is used to delay the power-on time of the PWM control signal. The delay time Td of the first delay circuit is proportional to the time constant τ=RC. The delay time can be adjusted by adjusting the value of RC. R is the resistance value of the first resistor R27, and C is the capacitance value of the first capacitor C22. Since the flip speed of the digital logic gate circuit is generally at the nanosecond level, it can be ignored. Therefore, the signal delay time Td (dead time) is determined by the delay circuit.

[0039] The output end of the first sub-inverter U3-B is connected to the input end of the second sub-inverter U3-C, and the output end of the second sub-inverter U3-C is connected to the input end of the first OC gate U4-A in the first level conversion circuit; the first level conversion circuit comprises the first OC gate U4-A, a capacitor C23, a capacitor C24, a resistor R28 and a resistor R33, wherein the working voltage VDD is connected to the 14th interface of the capacitor C23 and the first OC gate U4-A respectively; the 2nd interface (output end) of the first OC gate U4-A is connected to the capacitor C24 and two parallel resistors, i.e., the resistor R28 and the resistor R33, the resistor R28 is connected to the circuit voltage VIN, and the other end of the resistor R33 is grounded; the 2nd interface of the first OC gate U4-A is further connected to the resistor R30, and the output end of the resistor R30 is connected in parallel to a diode D7 and the gate (4th interface of Q1) of the first MOS tube; the first sub-inverter and the second sub-inverter are used for inverting the polarity of the PWM control signal; and the first level conversion circuit is used for converting the level of the PWM control signal.

[0040] The output end of the second sub-inverter U3-C is further connected to the input end of the fourth control circuit, and the fourth control circuit comprises a resistor R42 and a resistor R43, the resistor R43 is connected to the resistor R42 and the gate (4th interface of Q4) of the fourth MOS tube respectively, and the other end of the resistor R42 is grounded.

[0041] It can be seen that the aforementioned PWM control signal is first subjected to the first delay circuit, the first delay circuit can delay the power-on time of the input signal and accelerate the power-off speed, so as to obtain a sawtooth wave signal with slow power-on and fast power-off, and then the signal is subjected to signal shaping processing by the two sub-inverters (U3-B, U3-C), so as to obtain a square wave signal with stable phase difference. The square wave signal is connected to the gate of the fourth MOS tube for controlling the switching state thereof, and is connected to the first level conversion circuit constructed by the first OC gate U4-A and then connected to the gate of the first MOS tube for controlling the switching state thereof, so that the gate driving control of the forward driving side is realized.

[0042] In one possible example, the second driving circuit includes a second control circuit and a third control circuit, the third control circuit includes a third inverter, a second delay circuit, a fourth inverter, and a fifth inverter, and the second control circuit includes a second level conversion circuit; wherein the input end of the third inverter is connected to the output end of the inverter, the output end of the third inverter is connected to the input end of the second delay circuit, the output end of the second delay circuit is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the gate of the third MOS tube; the input end of the second level conversion circuit is connected to the output end of the fifth inverter, and the output end of the second level conversion circuit is connected to the gate of the second MOS tube; the second delay circuit is used to delay the power-on time of the PWM control signal; and the second level conversion circuit is an OC gate circuit used to convert the level of the PWM control signal.

[0043] Specifically, the third control circuit includes a third inverter U3-D, a second delay circuit, a fourth inverter U3-E, and a fifth inverter U3-F; the second delay circuit is composed of a second resistor R32, a second capacitor C28, and a second diode D9; wherein the second resistor R32 is connected in parallel with the second diode D9, the input end of the second resistor R32 and the second diode D9 is connected to the output end of the third inverter U3-D, the first output end of the second resistor R32 and the second diode D9 is connected to the input end of the second capacitor C28, the second output end of the second resistor R32 and the second diode D9 is connected to the input end of the fourth inverter U3-E, and the output end of the second capacitor C28 is grounded. Wherein, the second delay circuit is used to adjust the length of the power-on time of the PWM control signal, and has a positive correlation with the resistance value of the second resistor R32 and the capacitance value of the second capacitor C28.

[0044] Wherein, the output end of the fourth inverter U3-E is connected to the input end of the fifth inverter U3-F, the output end of the fifth inverter U3-F is connected to the resistor R40, the resistor R40 is respectively connected to the resistor R41 and the gate of the third MOS tube (the No. 4 interface of Q3), and the other end of the resistor R41 is grounded.

[0045] Specifically, the second control circuit includes a second level conversion circuit, and the second level conversion circuit includes a second OC gate U4-B, a capacitor C27, a resistor R29, a resistor R36, a resistor R31, and a diode D8; wherein the input end of the second OC gate U4-B is connected to the output end of the fifth inverter U3-F, the output end of the second OC gate U4-B is connected to the capacitor C27 and the parallel resistor: the resistor R29 and the resistor R36, the other end of the resistor R29 is connected to the input voltage VIN, the output end of the resistor R29 and the resistor R36 is commonly connected to the input end of the resistor R31, and the output end of the resistor R31 is respectively connected to the diode D8 and the gate of the second MOS tube (the No. 4 interface of Q2).

[0046] The control logic of the specific forward driving is as follows: when the external input PWM control signal is converted to high level, after the inversion, hardware delay, and signal shaping processing of the first circuit, the fourth MOS tube becomes the gate drive signal Q4-G of the fourth MOS tube, so at this moment, the gate of the fourth MOS tube is converted to low level, and the fourth MOS tube is closed; the signal Q4-G only changes in level after the level conversion circuit, and becomes the gate drive signal Q1-G of the first MOS tube, so at this moment, the gate of the first MOS tube is converted to low level, and the first MOS tube is closed; at the same time, as described above, the external input PWM control signal is processed by the second circuit, and then becomes the gate drive signal Q3-G of the third MOS tube, which is opposite in polarity to the first signal, so at this moment, the gate of the third MOS tube is converted to high level, and the third MOS tube is turned on; the signal Q3-G only changes in level after the second level conversion circuit, and becomes the gate drive signal Q2-G of the second MOS tube, so at this moment, the gate of the second MOS tube is converted to high level, and the second MOS tube is turned on. As described above, the hardware delay circuit constructed by the utility model has the characteristics of delaying the power-on time of the input signal and accelerating the power-off speed, so please refer to Figure 3 , Figure 3 is a timing diagram of a full-bridge gate drive circuit provided by the embodiment of the application, U3-A-pin2 refers to the level signal of pin 2 of U3-A, U3-C-pin6-Q4 refers to the signal level of pin 6 of U3-C and is also the level signal of the fourth MOS tube, U4-A-pin2-Q1 refers to the signal level of pin 2 of U4-A and is also the level signal of the first MOS tube, U3-D-pin8 refers to the signal level of pin 8 of U3-D, U3-F-pin12-Q3 refers to the signal level of pin 12 of U3-F and is also the level signal of the third MOS tube, U4-B-pin4-Q2 refers to the signal level of pin 4 of U4-B and is also the level signal of the second MOS tube, it can be seen that the falling edge of Q1-G and Q4-G is aligned with the rising edge of the PWM signal, and the rising edge of Q2-G and Q3-G is later than the rising edge of the PWM control signal, so as to ensure that the reverse driving side switch tube is completely closed before the forward driving side switch tube is turned on, thereby preventing the same side conduction failure from occurring. The control logic of the reverse driving can be known by analogy.

[0047] It can be seen that the difference between the aforementioned PWM control signal and the signal received by the first drive circuit is that the signal is inverted by the inverter once before the same signal processing of the first circuit is performed, so the signal of this circuit is opposite in polarity to the signal of the first drive circuit, and is used for controlling the conduction and closing of the reverse driving side second MOS tube and third MOS tube (Q2, Q3), thereby achieving the gate drive control of the reverse driving side.

[0048] This invention inserts hardware delay circuits into both the forward gate drive signal link and the reverse gate drive signal link, realizing the hardware double-sided dead time function (when switching between forward and reverse drive states, a delay is inserted to ensure that the switch on the forward (reverse) drive side is completely turned off before the switch on the reverse (forward) drive side is turned on, so as to avoid the occurrence of same-side conduction failure), which improves the overall control circuit safety and reduces the difficulty of adjusting the delay time during operation and maintenance.

[0049] In addition, to ensure the integrity and normal operation of the full-bridge drive circuit, this embodiment also provides, for example... Figure 2 The resistors R24, R34, R35, and capacitors C19, C20, C25, and C26 are shown. The operating voltage VDD is connected to the input terminals of capacitors C19, C20, and R24, respectively. The other ends of capacitors C19 and C20 are grounded. The output terminal of resistor R24 ​​is connected to the drains of the first and second MOSFETs, respectively. The source and drain of the first and third MOSFETs are connected to the input terminal of resistor R34. The output terminal of resistor R34 is connected to the input terminal of capacitor C25 and the negative terminal of the load LOAD, respectively. The source and drain of the second and fourth MOSFETs are connected to the input terminal of resistor R35. The output terminal of resistor R35 is connected to the input terminal of capacitor C26 and the positive terminal of the load LOAD, respectively. The output terminals of capacitors C25 and C26 are grounded.

[0050] In one possible example, the full-bridge gate drive circuit also includes a bridge-off circuit, see details below. Figure 4 , Figure 4 This is a bridge-off circuit topology diagram of a full-bridge gate drive circuit provided in an embodiment of this application. Figure 4 The bridge circuit shown includes an enable signal generator, a first open-circuit (OC) transmission gate U4-C, and a second open-circuit (OC) transmission gate U4-D; wherein, the first OC transmission gate U4-C and the second OC transmission gate U4-D are connected in parallel, the input terminals of the first OC transmission gate U4-C and the second OC transmission gate U4-D are respectively connected to the enable signal generator, and the output terminal of the first OC transmission gate U4-C is connected to... Figure 2 The output terminal of the first level conversion circuit in the middle is also Figure 2 The output of the second open-source transmission gate U4-D, at node Q1G, is connected to the output of the second level conversion circuit, i.e. Figure 2 Mid-node Q2G;

[0051] An enable signal generator is configured to output an enable signal to the first OC transmission gate U4-C and the second OC transmission gate U4-D; the first OC transmission gate U4-C and the second OC transmission gate U4-D are configured to perform a line and operation between the enable signal and a PWM control signal of the high-side MOS tube of the full-bridge circuit, so as to control the switching state of the full-bridge circuit by the PWM control signal when the enable signal is a high-level signal, or to close the full-bridge circuit when the enable signal is a low-level signal.

[0052] Specifically, the enable signal of the full-bridge is subjected to a line and operation with the gate control signals of the two high-side NMOS (the first MOS tube and the second MOS tube between the power supply and the load) of the full-bridge after passing through the OC transmission gates. If the enable signal maintains a low level, the result of the line and operation is a low level, so that the high-side NMOS connected thereto maintains a closed state, and the PWM control signal generated by the aforementioned full-bridge gate drive circuit cannot control the state of the NMOS. If the enable signal maintains a high level, the result of the line and operation is determined by the PWM control signal generated by the aforementioned full-bridge gate drive circuit, that is, the switching state of the high-side NMOS is controlled by the external input PWM control signal.

[0053] It can be seen that in the present example, the bridge closing circuit and the full-bridge gate drive control circuit are independent of each other, the delay bridge closing circuit scheme has low cost, and has energy saving advantages in common application scenarios.

[0054] In one possible example, the enable signal generator includes a single-chip microcomputer and a monostable trigger U5, wherein an output end of the single-chip microcomputer is connected to input ends of the first OC transmission gate U4-C and the second OC transmission gate U4-D, an input pin B of the monostable trigger U5 receives a trigger signal, and an output pin Q of the monostable trigger U5 is connected to the input ends of the first OC transmission gate U4-C and the second OC transmission gate U4-D.

[0055] The monostable trigger U5 is configured to output a high-level enable signal to the first OC transmission gate U4-C and the second OC transmission gate U4-D according to the received trigger signal, and output a low-level enable signal when no trigger signal is received within a preset time length; and the single-chip microcomputer is configured to generate the enable signal. Specifically, Figure 4 The single-chip microcomputer is not shown in FIG. 6, and only a level signal EN generated by the single-chip microcomputer is shown.

[0056] Specifically, when the single-chip microcomputer is selected as the enable signal generator, the soldering resistor R48 is welded, and the resistor R45 is deleted. When an external PWM signal is required to control the operation of the full-bridge, a high-level signal EN generated by the single-chip microcomputer can be input to the enable signal port. When the full-bridge needs to be closed, a low-level signal EN generated by the single-chip microcomputer can be input to the enable signal port. As shown in FIG. 6, Figure 4As shown, in the present example, the output end of the resistor R48 is connected to the receiving end of the resistor R49, the output end of the resistor R49 is grounded, and the resistor R49 is connected in parallel with the capacitor C36, and the common output end is connected to the first OC transmission gate U4-C and the second OC transmission gate U4-D respectively.

[0057] Specifically, when the monostable trigger is selected as the enable signal generator, the welding resistor R45 is removed, and each rising edge of the externally input trigger signal (connected to the B pin) will repeatedly trigger the monostable trigger U5 to generate a high level output on the Q pin. Figure 4 As shown, the monostable trigger U5 generates a high level output on the Q pin. When the PWM control signal is required to control the full-bridge operation, the high level on the Q pin does not affect the full-bridge operation, and the external PWM signal can control the full-bridge switching state. When the PWM control signal does not occur level inversion within a preset time Tsd, the Q pin of the monostable trigger U5 will jump to a low level output, so that the two high-side MOS transistors connected thereto are kept in a closed state, i.e., the full-bridge is closed.

[0058] wherein the preset idle determination time Tsd is determined by the resistance and capacitance values of the periphery of the monostable trigger U5, and satisfies the following relationship: Tsd=Rx*Cx, wherein Rx=R38+R39+R44, and Cx=C31~C35.

[0059] Specifically, the timing of the control circuit after the off-bridge circuit is configured is as follows: Figure 5 As shown, U5-pin13 refers to the level signal of pin 13 of U5; it can be seen that when the full-bridge enable signal EN is high, the externally input PWM control signal can control the switching state of the full-bridge circuit; when the full-bridge enable signal EN is low, the high-side MOS of the full-bridge circuit is low, i.e., the high-side MOS is closed, and then the full-bridge circuit is closed.

[0060] It can be seen that by selecting one resistor, the external low-voltage logic signal control off-bridge mode or the hardware delay off-bridge mode can be selected. The external low-voltage logic signal control off-bridge mode is convenient for software to flexibly adjust the off-bridge time; and the hardware delay off-bridge mode is simple and low in cost, and only needs to modify the hardware delay time by modifying the resistance and capacitance values of the periphery, thereby improving the flexibility and energy saving of the circuit.

[0061] Consistent with the above-mentioned circuit, the present application also provides a load driving device, which comprises any full-bridge gate driving circuit as described above.

[0062] In one embodiment, the load driving device is used for generating impulse oscillometry (IOS), which refers to a rectangular electric impulse generated by a pulse generator based on the forced oscillation principle, with the signal source separated from the test object. Based on the principle, the flow change of the respiratory organ to the pressure can be measured, so that the resistance of the respiratory organ can be measured. The pressure is generated from the oral cavity and applied to the entire respiratory system. While the subject is breathing calmly, the oscillation wave is superimposed on the pressure and flow curve of the subject's breathing. By continuously recording and analyzing the airway pressure and flow, the total respiratory impedance (Zrs) can be obtained. Therefore, the detected resistance is not only the airway viscous resistance measured by body plethysmography, but also the total respiratory impedance of the entire system.

[0063] The forced oscillation technique is used to examine the impedance parameters of the respiratory system. From the initial single-frequency oscillation, various techniques such as pseudo-random oscillation and impulse oscillometry have been developed. The oscillation wave can be absorbed and reflected in the airway and lung tissue. Different tissues have different absorption and reflection of the wave, and therefore exhibit different characteristics and sizes. Different frequency oscillation waves have different transmission distances and different reaction sites. For example, a loudspeaker can be used as an excitation source: the oscillation driving current is an alternating current, which generates an alternating magnetic field through the voice coil, interacts with the permanent magnet to produce reciprocating motion, and drives the cone to vibrate, which drives the air to vibrate, thereby forming an oscillation signal; or an electric motor, fan or turbine can be used as an excitation source: the electric motor drives the fan or turbine blade to rotate, forming an oscillation signal.

[0064] It should be noted that for the foregoing embodiments of the application, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the application is not limited by the order of the described actions, because according to the application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily necessary for the application.

[0065] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0066] In several embodiments provided in the present application, it should be understood that the disclosed circuit, device can be implemented by other ways. For example, the above-described device embodiments are only schematic, and the division of the units is only a logical function division, and there can be another division way in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical or other forms.

[0067] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0068] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0069] The above describes the embodiments of the present application in detail, and the specific examples are applied to the principle and implementation mode of the present application. The above embodiment description is only used to help understand the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; according to the above, the content of the specification should not be understood as the limitation of the present application.

Claims

1. A full-bridge gate drive circuit, characterized by, The circuit comprises a first driving circuit, a second driving circuit and a full-bridge circuit, the full-bridge circuit comprising a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a load; wherein an input end of the first driving circuit receives a PWM control signal, output ends of the first driving circuit are connected with a gate of the first MOS transistor and a gate of the fourth MOS transistor respectively; an input end of the second driving circuit is connected with the PWM control signal, output ends of the second driving circuit are connected with a gate of the second MOS transistor and a gate of the third MOS transistor respectively; drain electrodes of the first MOS transistor and the second MOS transistor are electrically connected with a power supply respectively; one end of the load is connected between a source electrode of the first MOS transistor and a drain electrode of the third MOS transistor, the other end of the load is connected between a source electrode of the second MOS transistor and a drain electrode of the fourth MOS transistor; the first driving circuit is configured to drive the first MOS transistor and the fourth MOS transistor to be turned on or turned off according to a level of the PWM control signal; the second driving circuit is configured to receive the PWM control signal and drive the second MOS transistor and the third MOS transistor to be turned on or turned off according to a level of the PWM control signal.

2. The circuit according to claim 1, wherein when the first MOS transistor and the fourth MOS transistor are turned on and the second MOS transistor and the third MOS transistor are turned off, the full-bridge circuit is in a forward conduction state to realize forward driving of the load to work; when the second MOS transistor and the third MOS transistor are turned on and the first MOS transistor and the fourth MOS transistor are turned off, the full-bridge circuit is in a reverse conduction state to realize reverse driving of the load to work. The full-bridge gate driving circuit further comprises an inverter, an input end of the inverter receives the PWM control signal, and output ends of the inverter are connected with an input end of the first driving circuit and an input end of the second driving circuit respectively; 3. The circuit of claim 1 or 2, characterized in that, the inverter is configured to perform inversion processing on a polarity of the received PWM control signal. The first driving circuit comprises a first control circuit and a fourth control circuit, the first control circuit comprising a first delay circuit, a first sub-inverter, a second sub-inverter and a first level conversion circuit; wherein 4. The circuit of claim 3, wherein, an input end of the first delay circuit is connected with an output end of the inverter, an output end of the first delay circuit is connected with an input end of the first sub-inverter, an output end of the first sub-inverter is connected with an input end of the second sub-inverter, an output end of the second sub-inverter is connected with an input end of the first level conversion circuit, and an output end of the first level conversion circuit is connected with a gate of the first MOS transistor; an input end of the fourth control circuit is connected with an output end of the second sub-inverter, and an output end of the fourth control circuit is connected with a gate of the fourth MOS transistor; the first delay circuit is configured to delay a power-on time of the PWM control signal. ​ The first sub-inverter and the second sub-inverter are configured to invert the polarity of the PWM control signal. The first level conversion circuit is an OC gate circuit configured to convert the level of the PWM control signal.

5. The circuit of claim 4, wherein, The first delay circuit comprises a first resistor, a first capacitor and a first diode, wherein the first resistor and the first diode are connected in parallel, the input ends of the first resistor and the first diode are connected to the output end of the inverter, the first output end of the first resistor and the first diode is connected to the input end of the first capacitor, the second output end of the first resistor and the first diode is connected to the input end of the first sub-inverter, and the output end of the first capacitor is grounded. The first delay circuit adjusts the length of the power-on time, and the resistance value of the first resistor and the capacitance value of the first capacitor are positively correlated with the length of the power-on time.

6. The circuit of claim 4, wherein, The second driving circuit comprises a second control circuit and a third control circuit, the third control circuit comprises a third inverter, a second delay circuit, a fourth inverter and a fifth inverter, and the second control circuit comprises a second level conversion circuit. The input end of the third inverter is connected to the output end of the inverter, the output end of the third inverter is connected to the input end of the second delay circuit, the output end of the second delay circuit is connected to the input end of the fourth inverter, the output end of the fourth inverter is connected to the input end of the fifth inverter, the output end of the fifth inverter is connected to the gate of the third MOS tube, the input end of the second level conversion circuit is connected to the output end of the fifth inverter, and the output end of the second level conversion circuit is connected to the gate of the second MOS tube. The second delay circuit is configured to delay the power-on time of the PWM control signal. The second level conversion circuit is an OC gate circuit configured to convert the level of the PWM control signal.

7. The circuit of claim 6, wherein, The second delay circuit comprises a second resistor, a second capacitor and a second diode, wherein the second resistor and the second diode are connected in parallel, the input ends of the second resistor and the second diode are connected to the output end of the third inverter, the first output end of the second resistor and the second diode is connected to the input end of the second capacitor, the second output end of the second resistor and the second diode is connected to the input end of the fourth sub-inverter, and the output end of the second capacitor is grounded. The second delay circuit adjusts the length of the power-on time, and the resistance value of the second resistor and the capacitance value of the second capacitor are positively correlated with the length of the power-on time.

8. The circuit of claim 6, wherein, The full-bridge gate driving circuit further comprises a bridge-off circuit, the bridge-off circuit comprises an enable signal generator, a first OC transmission gate and a second OC transmission gate, wherein The first OC transmission gate and the second OC transmission gate are connected in parallel, the input ends of the first OC transmission gate and the second OC transmission gate are respectively connected to the enable signal generator, the output end of the first OC transmission gate is connected to the output end of the first level conversion circuit, and the output end of the second OC transmission gate is connected to the output end of the second level conversion circuit. The enable signal generator is configured to output an enable signal to the first OC pass gate and the second OC pass gate. The first OC pass gate and the second OC pass gate are configured to perform a logical AND operation between the enable signal and the PWM control signal of the high-side MOS tube of the full-bridge circuit, so as to control the switching state of the full-bridge circuit by the PWM control signal when the enable signal is a high-level signal, or to turn off the full-bridge circuit when the enable signal is a low-level signal.

9. The circuit of claim 8, wherein, The enable signal generator comprises a single-chip microcomputer and a monostable trigger, wherein an output end of the single-chip microcomputer is connected to input ends of the first OC pass gate and the second OC pass gate, an input pin of the monostable trigger receives a trigger signal, and an output pin of the monostable trigger is connected to the input ends of the first OC pass gate and the second OC pass gate. The monostable trigger is configured to output a high-level enable signal to the first OC pass gate and the second OC pass gate according to the received trigger signal, and output a low-level enable signal when the trigger signal is not received within a preset time length. The single-chip microcomputer is configured to generate the enable signal.

10. A load driving apparatus characterized by comprising: The load driving device comprises the full-bridge gate driving circuit according to any one of claims 1-9.

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