Double-circuit power supply switching circuit

Abstract

The utility model relates to a double-circuit power supply switching circuit, which comprises a first PMOS (P-channel Metal Oxide Semiconductor) tube and a third NMOS (N-channel Metal Oxide Semiconductor) tube, the first PMOS tube is connected with the grid electrode of the drain electrode of the first NMOS tube, and the first PMOS tube, the first NMOS tube and the third NMOS tube are used for receiving a first power supply; the drain electrode of the third NMOS tube is connected with the grid electrode of the second NMOS tube and the other end of the pull-up resistor; one end of the pull-up resistor is connected with the drain electrode of the second PMOS tube and is used for receiving a second power supply; the drain electrode of the second NMOS tube is connected with the grid electrode of the second PMOS tube; the source electrode of the first PMOS transistor and the source electrode of the second PMOS transistor are respectively used for being connected with the input end of power receiving equipment; the source electrode of the first NMOS tube, the source electrode of the second NMOS tube and the source electrode of the third NMOS tube are all grounded. The technical problem that in the prior art, it is difficult to achieve automatic switching of two paths of power supplies with different voltages, and meanwhile the system cannot be powered off or restarted is solved.

Description

Technical Field

[0001] This utility model relates to the field of power electronic devices, and in particular to a dual-power supply switching circuit. Background Technology

[0002] In the field of smart POS devices, some POS devices that do not use battery power typically use an external power source (such as DC_12V or USB_5V) to power the system. This results in two power sources existing at the same time. However, in this case, existing technology cannot achieve automatic switching between two power sources with different voltages without the system losing power, shutting down, or restarting. Utility Model Content

[0003] This utility model discloses a dual-power supply switching circuit to solve the technical problem that the existing technology is unable to achieve automatic switching between two power supplies with different voltages without the system losing power, shutting down, or restarting.

[0004] This utility model embodiment provides a dual-power supply switching circuit, including: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a pull-up resistor;

[0005] The gate of the first NMOS transistor is used to receive the first power supply, and the drain of the first NMOS transistor is connected to the gate of the first PMOS transistor. The drain of the first PMOS transistor is used to receive the first power supply.

[0006] The gate of the third NMOS transistor is used to receive the first power supply, and the drain of the third NMOS transistor is connected to the gate of the second NMOS transistor.

[0007] The drain of the second PMOS transistor is connected to one end of the pull-up resistor to receive the second power supply; the other end of the pull-up resistor is connected to the drain of the third NMOS transistor and the gate of the second NMOS transistor, respectively.

[0008] The drain of the second NMOS transistor is connected to the gate of the second PMOS transistor;

[0009] The source of the first PMOS transistor and the source of the second PMOS transistor are respectively used to connect to the input terminal of the powered device; the source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all grounded;

[0010] The voltage of the first power source is greater than the voltage of the second power source.

[0011] Optionally, it also includes a delay sub-circuit, the input of which is used to receive a first power supply;

[0012] The output terminal of the delay sub-circuit is connected to the gate of the first NMOS transistor and ground, respectively.

[0013] Optionally, the delay sub-circuit includes: a first delay resistor, a second delay resistor, and a first delay capacitor;

[0014] One end of the first delay resistor is used to connect to the first power supply;

[0015] The other end of the first delay resistor is connected to one end of the second delay resistor, one end of the first delay capacitor, and the gate of the first NMOS transistor, respectively.

[0016] The other end of the first delay capacitor and the other end of the second delay resistor are connected to the source of the first NMOS transistor and grounded.

[0017] Optionally, it also includes a first protection sub-circuit; the first protection sub-circuit includes: a first capacitor, a second capacitor, a first resistor, a first overvoltage protection chip, and a second resistor;

[0018] One end of the first capacitor is connected to the input terminal of the first overvoltage protection chip and is used to receive the first power supply; the other end of the first capacitor is grounded.

[0019] The threshold input terminal of the first overvoltage protection chip is connected to one end of the second capacitor and one end of the first resistor, respectively; the other end of the second capacitor is connected to the other end of the first resistor and grounded.

[0020] The grounding terminal of the first overvoltage protection chip is connected to ground;

[0021] The output terminal of the first overvoltage protection chip is connected to the drain of the first PMOS transistor;

[0022] The enable terminal of the first overvoltage protection chip is used to connect to the gate of the second NMOS transistor;

[0023] The status indicator terminal of the first overvoltage protection chip is connected to one end of the second resistor, and the other end of the second resistor is grounded.

[0024] Optionally, it also includes a second protection sub-circuit; the second protection sub-circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, a sixth capacitor, a seventh capacitor, an eighth resistor, and a second overvoltage protection chip;

[0025] One end of the fifth resistor is connected to the input terminal of the second overvoltage protection chip and is used to connect to the second power supply;

[0026] The other end of the fifth resistor is connected to one end of the sixth resistor and the threshold input terminal of the second overvoltage protection chip; the other end of the sixth resistor is grounded.

[0027] The enable terminal of the second overvoltage protection chip is connected to one end of the seventh resistor;

[0028] The other end of the seventh resistor is connected to the ground terminal of the second overvoltage protection chip and grounded;

[0029] The output terminal of the second overvoltage protection chip is connected to one end of the sixth capacitor, one end of the seventh capacitor, one end of the eighth resistor, one end of the pull-up resistor, and the drain of the second PMOS transistor, respectively.

[0030] The other end of the sixth capacitor, the other end of the seventh capacitor, and the other end of the eighth resistor are grounded.

[0031] Optionally, it may also include: a third capacitor, a third resistor, a fourth capacitor, a fifth capacitor, and a fourth resistor;

[0032] The source of the first PMOS transistor is connected to one end of the third capacitor, one end of the third resistor, one end of the fourth capacitor, and one end of the fifth capacitor, respectively.

[0033] The other end of the third capacitor is connected to the gate of the first PMOS transistor.

[0034] The other end of the third resistor is connected to the other end of the third capacitor and one end of the fourth resistor; the other end of the fourth resistor is connected to the drain of the first NMOS transistor.

[0035] The other end of the fourth capacitor and the other end of the fifth capacitor are both grounded.

[0036] Optionally, it may also include: a ninth resistor and a tenth resistor;

[0037] One end of the ninth resistor is used to connect to the first power source;

[0038] The other end of the ninth resistor is connected to one end of the tenth resistor and the gate of the third NMOS transistor, respectively.

[0039] The other end of the tenth resistor is grounded.

[0040] Optionally, it also includes: an eleventh resistor, a twelfth resistor, an eighth capacitor, and a thirteenth resistor;

[0041] One end of the eleventh resistor is connected to the enable terminal of the first overvoltage protection chip;

[0042] The other end of the eleventh resistor is connected to one end of the twelfth resistor, the other end of the pull-up resistor, and the drain of the third NMOS transistor, respectively.

[0043] The other end of the twelfth resistor is connected to one end of the eighth capacitor and the gate of the second NMOS transistor, respectively, and the other end of the eighth capacitor is grounded;

[0044] The drain of the second NMOS transistor is connected to the thirteenth resistor, and is also connected to the gate of the second PMOS transistor through the thirteenth resistor.

[0045] Optionally, it also includes: a fourteenth resistor and a ninth capacitor;

[0046] The two ends of the fourteenth resistor are respectively connected to the source and gate of the second PMOS transistor;

[0047] The ninth capacitor is connected in parallel across the fourteenth resistor.

[0048] Optionally, the power receiving device includes a voltage conversion module;

[0049] The input terminal of the voltage conversion module is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively.

[0050] The output terminal of the voltage conversion module is connected to the system to be powered, and is used to convert the received voltage into the target voltage. From the above technical solution, it can be seen that the embodiments of this utility model have the following advantages:

[0051] This utility model embodiment provides a dual-power supply switching circuit, including: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a pull-up resistor; the gate of the first NMOS transistor is used to receive a first power supply, and the drain of the first NMOS transistor is connected to the gate of the first PMOS transistor, and the drain of the first PMOS transistor is used to receive the first power supply; the gate of the third NMOS transistor is used to receive the first power supply, and the drain of the third NMOS transistor is connected to the gate of the second NMOS transistor; the drain of the second PMOS transistor is connected to one end of the pull-up resistor to receive a second power supply; the other end of the pull-up resistor is connected to the drain of the third NMOS transistor and the gate of the second NMOS transistor respectively; the drain of the second NMOS transistor is connected to the gate of the second PMOS transistor; the sources of the first PMOS transistor and the second PMOS transistor are respectively used to connect to the input terminal of the powered device; the sources of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all grounded; the voltage of the first power supply is greater than the voltage of the second power supply.

[0052] In this invention, the first NMOS transistor and the first PMOS transistor are connected to form the power transmission channel of the first power supply. The pull-up resistor, the second NMOS transistor, the third NMOS transistor, and the second PMOS transistor form the power transmission channel of the second power supply. The gates of the first NMOS transistor and the third NMOS transistor are respectively used to receive the first power supply. Therefore, connecting and disconnecting the first power supply can be used to switch the on and off states of the first NMOS transistor and the third NMOS transistor. Based on the connection relationship between the first NMOS transistor and the first PMOS transistor, the connection relationship between the third NMOS transistor and the second NMOS transistor, the connection relationship between the pull-up resistor and the second NMOS transistor, and the connection relationship between the second NMOS transistor and the second PMOS transistor, by connecting or disconnecting the first power supply, the on and off states of the first PMOS transistor and the second PMOS transistor are switched, thereby realizing the switching of the power transmission channel. Since both the first and second PMOS transistors have built-in body diodes, when either the first or second PMOS transistor is in the off state, if a corresponding power supply is connected to its drain, the received power can still drain to the source of the PMOS transistor through the internal body diode. Based on this, this invention allows the input terminal of the receiving module to remain powered during power switching, preventing the receiving device from shutting down or restarting due to power loss. Furthermore, in this embodiment, the voltage of the first power supply is greater than that of the second power supply. Therefore, when both power supplies are connected, the first power supply can prioritize powering the receiving device. When the first power supply is removed, it can automatically switch to the second power supply. When the second power supply is removed, the first power supply can continue to power the receiving device. Therefore, the dual-power supply switching circuit provided by this invention achieves automatic switching between two power supplies with different voltages without causing the receiving device to shut down or restart during the switching process. This solves the problem of existing technologies failing to achieve the goal of automatically switching between two power supplies with different voltages without causing the system to shut down or restart due to power loss. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is one of the structural schematic diagrams of a dual-power supply switching circuit provided in the embodiments of this utility model;

[0055] Figure 2 This is a second schematic diagram of a dual-power supply switching circuit provided in an embodiment of this utility model;

[0056] Figure 3 This is the third schematic diagram of a dual-power supply switching circuit provided in this embodiment of the present utility model;

[0057] Figure 4 This is a schematic diagram of the structure of the first protection sub-circuit provided in the embodiment of this utility model;

[0058] Figure 5 This is a schematic diagram of the structure of the second protection sub-circuit provided in the embodiment of this utility model;

[0059] Figure 6 This is a schematic diagram of the DC-DC step-down module provided in the embodiments of this utility model. Detailed Implementation

[0060] This utility model provides a dual-power supply switching circuit to solve the technical problem that existing technologies cannot achieve automatic switching between two power supplies with different voltages without the system losing power, shutting down, or restarting.

[0061] The technical solution of this utility model will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this utility model. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this utility model.

[0062] In the description of this utility model, it should be noted that the terms "front," "rear," "upper," "lower," "both ends," "center," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Relational terms such as "first," "second," etc., are only used to distinguish one entity from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities.

[0063] Unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0064] Please see Figure 1An embodiment of a dual-power supply switching circuit provided in this utility model includes: a first PMOS transistor 1, a first NMOS transistor 2, a second PMOS transistor 3, a second NMOS transistor 4, a third NMOS transistor 5, and a pull-up resistor R2833; the gate of the first NMOS transistor 2 is used to receive a first power supply, and the drain of the first NMOS transistor 2 is connected to the gate of the first PMOS transistor 1, and the drain of the first PMOS transistor 1 is used to receive the first power supply; the gate of the third NMOS transistor 5 is used to receive the first power supply, and the drain of the third NMOS transistor 5 is connected to the gate of the second NMOS transistor 4; the second PMOS transistor 5... The drain of MOS transistor 3 is connected to one end of the pull-up resistor R2833 to receive the second power supply; the other end of the pull-up resistor R2833 is connected to the drain of the third NMOS transistor 5 and the gate of the second NMOS transistor 4; the drain of the second NMOS transistor 4 is connected to the gate of the second PMOS transistor 3; the source of the first PMOS transistor 1 and the source of the second PMOS transistor 3 are respectively connected to the input terminal of the power receiving device 6; the sources of the first NMOS transistor 2, the second NMOS transistor 4, and the third NMOS transistor 5 are all grounded; the voltage of the first power supply is greater than the voltage of the second power supply.

[0065] It should be noted that the power receiving device 6 refers to the device that requires a power source.

[0066] In this embodiment, when only the first power supply is connected, the first NMOS transistor 2 is grounded and turned on, and the third NMOS transistor 5 is grounded and turned on. The turn-on of the third NMOS transistor 5 makes its drain voltage zero, thereby pulling down the gate voltage of the second NMOS transistor 4, causing the second NMOS transistor 4 to turn off, and consequently the second PMOS transistor 3 to turn off. The grounding and turning on of the first NMOS transistor 2 makes its drain voltage zero, thereby making the gate-source voltage of the first PMOS transistor 1 less than zero, and consequently turning on the first PMOS transistor 1. Therefore, the first power supply provides power to the powered device 6.

[0067] When both the first and second power supplies are connected, the third NMOS transistor 5 is grounded and conducts, making its drain voltage zero. This, in turn, makes the gate-source voltage of the second NMOS transistor 4 zero, putting it off. Consequently, the gate-source voltage of the second PMOS transistor 3 becomes zero, also putting it off. Since the second PMOS transistor 3 contains a body diode, with its anode connected to the drain and its cathode connected to the source, a voltage at the cathode less than the anode allows the body diode to conduct, enabling the second power supply voltage to drain through it to the source of the second PMOS transistor 3. The connection of the first power supply energizes the gate of the first NMOS transistor 2, making the gate-source voltage of the first PMOS transistor 1 less than zero, thus turning it on and outputting the first power supply. Therefore, if connected to the receiving device 6, the input voltage of the receiving device 6 can be the voltage of the first power supply. Since the sources of both the first PMOS transistor 1 and the second PMOS transistor 3 are used to connect to the input terminal of the powered device 6, the voltage at the source of the second PMOS transistor 3 is also the voltage of the first power supply. Since the voltage of the first power supply is greater than the voltage of the second power supply, the voltage at the cathode of the body diode in the second PMOS transistor 3 (the voltage of the first power supply) is greater than the voltage at the anode (the voltage of the second power supply), causing the body diode to be cut off. The voltage of the second power supply is only transmitted to the anode of the body diode in the second PMOS transistor 3. Therefore, when both the first power supply and the second power supply are connected, the first power supply can be used to provide power to the powered device 6 first.

[0068] With both the first and second power supplies connected, when the second power supply is disconnected and only the first power supply remains, the first power supply continues to provide power to the powered device 6.

[0069] With both the first and second power supplies connected, when the first power supply is disconnected and only the second power supply remains connected, the voltage at the anode of the body diode in the second PMOS transistor 3 is greater than the voltage at the cathode. This allows the voltage of the second power supply to drain rapidly through the body diode to the source terminal of the second PMOS transistor 3, thus continuously energizing the source terminal of the second PMOS transistor 3. Since the body diode itself has a voltage drop, the source terminal voltage of the second PMOS transistor 3 is equal to the voltage of the second power supply minus the voltage drop of the body diode. That is, when connected to the powered device 6, at the instant of power switching, the voltage at the input terminal of the powered device 6 drops from the voltage of the first power supply to the source terminal voltage of the second PMOS transistor 3, and it continues to be energized. Simultaneously, since the first power supply has been disconnected, the gate-source voltage of the third NMOS transistor 5 is zero, therefore the third NMOS transistor 5 is in the off state. At this time, the second power supply applies voltage to the second NMOS transistor 4 through the pull-up resistor R2833, turning on the second NMOS transistor 4. When the second NMOS transistor 4 is turned on, the voltage at the drain terminal of the second NMOS transistor 4 becomes zero, which in turn makes the gate-source voltage of the second PMOS transistor 3 less than zero. When the second PMOS transistor 3 is turned on, the voltage at the source terminal of the second PMOS transistor 3 becomes equal to the voltage of the second power supply, thus continuously supplying power to the powered device 6.

[0070] Therefore, when the first power supply and the second power supply are connected, the voltage change at the input terminal of the powered device 6 when the first power supply is disconnected is as follows: the voltage drops from the voltage of the first power supply to the voltage of the second power supply after being stepped down by the body diode, and then changes back to the voltage of the second power supply after being stepped down by the body diode. It can be seen that the input terminal of the powered device 6 is continuously powered during the power switching process.

[0071] With the second power supply connected, when the first power supply is connected again, the first NMOS transistor 2 turns on, which in turn turns on the first PMOS transistor 1. At this time, the source voltage of the first PMOS transistor 1 is the voltage of the first power supply. Simultaneously, the third NMOS transistor 5 turns on, causing the second NMOS transistor 4 to turn off, which in turn causes the second PMOS transistor 3 to turn off. Since the voltage of the first power supply is greater than the voltage of the second power supply, the voltage at the anode of the body diode in the second PMOS transistor 3 is less than the voltage at its cathode, and the body diode in the second PMOS transistor 3 turns off. The first power supply then provides power to the device 6. Therefore, with the second power supply connected, when the first power supply is connected again, this circuit can automatically switch to the first power supply to power the device 6, and during the switching process, the input terminal of the device 6 is continuously powered.

[0072] Therefore, the dual power supply switching circuit provided in this embodiment can automatically switch to one power supply when two power supplies are connected at the same time, and automatically switch to the other power supply when either power supply is removed. During the switching process, it ensures that the system will not lose power, shut down, or restart. This solves the technical problem in the prior art that most of them use a single power supply method and cannot achieve automatic switching between two different power supplies to ensure that the system will not lose power, shut down, or restart.

[0073] It is understandable that the voltage of the first power supply and the voltage of the second power supply can be set according to the power requirements of the powered device 6 and the voltage drop of the body diodes of the first PMOS transistor 1 and the second PMOS transistor 3, so that the voltage of the first power supply and the voltage of the second power supply, after being stepped down by the body diodes, still meet the power requirements of the powered device 6.

[0074] Therefore, the dual power supply switching circuit provided in this embodiment solves the technical problem that it is difficult to achieve automatic switching between two different power supplies to ensure that the system does not lose power, shut down, or restart. It realizes automatic switching between two power supplies with different voltages, and the switching does not cause the powered equipment to lose power, shut down, or restart.

[0075] In one specific embodiment, see Figure 2 It also includes a delay sub-circuit 7, the input of which is used to receive a first power supply;

[0076] The output terminal of the delay sub-circuit 7 is connected to the gate of the first NMOS transistor 2 and ground, respectively.

[0077] It should be noted that, as described in the foregoing embodiments, when the first power supply is connected, the first NMOS transistor 2 and the third NMOS transistor 5 are both turned on. The turn-on of the first NMOS transistor 2 causes the first PMOS transistor 1 to turn on, and the turn-on of the third NMOS transistor 5 causes the second PMOS transistor 3 to turn off. Therefore, in this embodiment, the delay sub-circuit 7 is connected to the first NMOS transistor 2, thereby delaying the time it takes for the first power supply to reach the gate of the first NMOS transistor 2 when the first power supply is connected, thus delaying the turn-on time of the first PMOS transistor 1. This makes the turn-on time of the first PMOS transistor 1 much longer than the turn-off time of the second PMOS transistor 3. As a result, when the first PMOS transistor 1 is turned on, the second PMOS transistor 3 is already in a turned-off state, preventing the first power supply from flowing back from the source of the first PMOS transistor 1 to the drain of the second PMOS transistor 3, thus improving the safety and reliability of the circuit.

[0078] Furthermore, when the first power supply is connected again after the second power supply is connected, due to the delay effect of the delay circuit 7, the first NMOS transistor 2 does not turn on immediately. Instead, it turns on after the delay time has elapsed. Therefore, the first NMOS transistor 2 remains off until the delay ends. When the first power supply is connected, the third NMOS transistor 5 turns on, causing the second NMOS transistor 4 to turn off, which in turn causes the second PMOS transistor 3 to turn off. Although the first PMOS transistor 1 is off, because it contains a body diode, the first power supply can drain to the source of the first PMOS transistor 1 through its drain and body diode. At this time, the voltage at the source of the first PMOS transistor 1 is the voltage of the first power supply minus the voltage drop across the body diode. Since the voltage at the source of the first PMOS transistor 1 is still greater than the voltage at the source of the second PMOS transistor 3, the power is still supplied to the powered device 6 by the voltage at the source of the first PMOS transistor 1. When the delay ends, the first NMOS transistor 2 turns on, which in turn turns on the first PMOS transistor 1. At this time, the voltage at the source of the first PMOS transistor 1 is the voltage of the first power supply. Therefore, the first power supply supplies power to the device 6 through the source of the first PMOS transistor 1.

[0079] Therefore, by setting the delay sub-circuit 7, this embodiment makes the conduction time of the first PMOS transistor 1 much longer than the turn-off time of the second PMOS transistor 3, thus avoiding the situation where the first power supply flows back to the second PMOS transistor 3 after it is connected, improving the safety and reliability of the circuit. At the same time, when the circuit is switched, the input terminal of the powered device 6 is continuously powered, and the system can be ensured not to lose power, shut down or restart during the switching process.

[0080] In one specific embodiment, see Figure 4 The delay sub-circuit includes: a first delay resistor R2848, a second delay resistor R2847, and a first delay capacitor C2861;

[0081] One end of the first delay resistor R2848 is used to connect to the first power supply;

[0082] The other end of the first delay resistor R2848 is connected to one end of the second delay resistor R2847, one end of the first delay capacitor C2861, and the gate of the first NMOS transistor Q2809, respectively.

[0083] The other end of the first delay capacitor C2861 and the other end of the second delay resistor R2847 are connected to the source of the first NMOS transistor Q2809 and grounded.

[0084] It should be noted that in this embodiment, a delay RC network is formed by the first delay resistor R2848, the second delay resistor R2847 and the first delay capacitor C2861 to delay the power-on time of the gate of the first NMOS transistor Q2809.

[0085] The specific delay time can be determined based on the values ​​of the first delay resistor R2848, the second delay resistor R2847, and the first delay capacitor C2861. These values ​​can be set according to actual requirements. For example, when the first power supply voltage is 12V, the delay sub-circuit can be configured with a 1-second delay by adjusting the values ​​of the first delay resistor R2848, the second delay resistor R2847, and the first delay capacitor C2861. This ensures that when the first power supply is connected, the first NMOS transistor Q2809 will turn on after a 1-second delay.

[0086] In one specific embodiment, see Figure 4 It also includes a first protection sub-circuit; the first protection sub-circuit includes: a first capacitor C2836, a second capacitor C2837, a first resistor R2812, a first overvoltage protection chip U2803, and a second resistor R2811;

[0087] One end of the first capacitor C2836 is connected to the input terminal of the first overvoltage protection chip U2803 and is used to receive the first power supply; the other end of the first capacitor C2836 is grounded.

[0088] The threshold input terminal of the first overvoltage protection chip U2803 is connected to one end of the second capacitor C2837 and one end of the first resistor R2812, respectively; the other end of the second capacitor C2837 is connected to the other end of the first resistor R2812 and grounded.

[0089] The grounding terminal of the first overvoltage protection chip U2803 is connected to ground;

[0090] The output terminal of the first overvoltage protection chip U2803 is connected to the drain of the first PMOS transistor Q2808;

[0091] The enable terminal of the first overvoltage protection chip U2803 is used to connect to the gate of the second NMOS transistor Q2805;

[0092] The status indicator terminal of the first overvoltage protection chip U2803 is connected to one end of the second resistor R2811, and the other end of the second resistor R2811 is grounded.

[0093] It should be noted that the first protection sub-circuit serves as overvoltage protection. The input terminal of the first overvoltage protection chip U2803 receives the first power supply. In practical applications, the threshold voltage inside the first overvoltage protection chip U2803 is set by adjusting the values ​​of the second capacitor C2837 and the first resistor R2812. The output terminal of the first overvoltage protection chip U2803 outputs the first power supply. In this embodiment, the first overvoltage protection chip U2803 detects the voltage of the first power supply and, when the voltage exceeds the threshold voltage, disconnects the input and output terminals, stopping the output of the first power supply and protecting the subsequent circuitry. Therefore, this embodiment further enhances the safety and reliability of the circuit by incorporating the first protection sub-circuit.

[0094] like Figure 4 As shown, the input terminals of the first overvoltage protection chip U2803 are IN_1 to IN_8, and each input terminal is connected to each other and connected to one end of the first capacitor C2836 to receive the first power supply.

[0095] The threshold input terminal VP of the first overvoltage protection chip U2803 is connected to the second capacitor C2837 and the first resistor R2812, respectively. Therefore, in practical applications, the threshold voltage in the first overvoltage protection chip U2803 can be set by adjusting the values ​​of the second capacitor C2837 and the first resistor R2812.

[0096] The output terminals of the first overvoltage protection chip U2803 are OUT_1 to OUT_5, and each output terminal is connected to the drain of the first PNMOS transistor for inputting the first power supply.

[0097] The grounding terminals of the first overvoltage protection chip U2803 are GND_1 and GND_2, and each grounding terminal is connected to each other and grounded.

[0098] The enable terminal ENN of the first overvoltage protection chip U2803 is connected to resistor R2850 via the lead DC_OVP_ENN.

[0099] The status indicator terminal FLAGN of the first overvoltage protection chip U2803 is connected to one end of the second resistor R2811.

[0100] In one specific embodiment, see Figure 4 It also includes: the third capacitor C2860, the third resistor R2845, the fourth capacitor C2835, the fifth capacitor C2856, and the fourth resistor R2846;

[0101] The source of the first PMOS transistor Q2808 is connected to one end of the third capacitor C2860, one end of the third resistor R2845, one end of the fourth capacitor C2835, and one end of the fifth capacitor C2856, respectively.

[0102] The other end of the third capacitor C2860 is connected to the gate of the first PMOS transistor Q2808;

[0103] The other end of the third resistor R2845 is connected to the other end of the third capacitor C2860 and one end of the fourth resistor R2846; the other end of the fourth resistor R2846 is connected to the drain of the first NMOS transistor Q2809.

[0104] The other end of the fourth capacitor C2835 and the other end of the fifth capacitor C2856 are both grounded.

[0105] It should be noted that, as Figure 4 As shown, the first PMOS transistor Q2808 has a body diode. The anode of the body diode is connected to the drain of the first PMOS transistor Q2808, and the body diode is connected to the source of the first PMOS transistor Q2808. Multiple pins are led out from the drain of the first PMOS transistor Q2808. These pins are pins 1 to 2 located on the lower left side of the first PMOS transistor Q2808, and pins 5 to 7 located on the upper left side of the first PMOS transistor Q2808. Pins 1 to 2 and pins 5 to 7 are interconnected and connected to the output terminal of the first overvoltage protection chip U2803. Two pins are led out from the source of the first PMOS transistor Q2808, pins 4 and 8 located on the upper right side. Pins 4 and 8 are interconnected and connected to the third capacitor C2860, the third resistor R2845, the fourth capacitor C2835, and the fifth capacitor C2856, respectively, serving as power output terminals and connected to the powered device through the line MB_VBUS_IN.

[0106] Pin 3 is led out from the gate of the first PMOS transistor Q2808. Pin 3 is connected to the fourth resistor R2846 and then connected to the drain of the first NMOS transistor Q2809 through the fourth resistor R2846.

[0107] In one specific embodiment, see Figure 5 It also includes a second protection sub-circuit; the second protection sub-circuit includes: a fifth resistor R2831, a sixth resistor R2830, a seventh resistor R2829, a sixth capacitor C2851, a seventh capacitor C2850, an eighth resistor R2834, and a second overvoltage protection chip U2806.

[0108] One end of the fifth resistor R2831 is connected to the input terminal of the second overvoltage protection chip U2806 and is used to connect to the second power supply;

[0109] The other end of the fifth resistor R2831 is connected to one end of the sixth resistor R2830 and the threshold input terminal of the second overvoltage protection chip U2806; the other end of the sixth resistor R2830 is grounded.

[0110] The enable terminal of the second overvoltage protection chip U2806 is connected to one end of the seventh resistor R2829;

[0111] The other end of the seventh resistor R2829 is connected to the ground terminal of the second overvoltage protection chip U2806 and grounded;

[0112] The output terminal of the second overvoltage protection chip U2806 is connected to one end of the sixth capacitor C2851, one end of the seventh capacitor C2850, one end of the eighth resistor R2834, one end of the pull-up resistor R2833, and the drain of the second PMOS transistor Q2804, respectively.

[0113] The other end of the sixth capacitor C2851, the other end of the seventh capacitor C2850, and the other end of the eighth resistor R2834 are grounded.

[0114] It should be noted that the second protection sub-circuit serves as overvoltage protection. The input terminal of the second overvoltage protection chip U2806 receives the second power supply. In practical applications, the threshold voltage inside the second overvoltage protection chip U2806 is set by adjusting the values ​​of the fifth resistor R2831 and the sixth resistor R2830. The output terminal of the second overvoltage protection chip U2806 outputs the second power supply. In this embodiment, the first overvoltage protection chip U2803 detects the voltage of the second power supply and, when the voltage exceeds the threshold voltage, disconnects the input and output terminals, stopping the output of the second power supply and protecting the subsequent circuitry. Therefore, this embodiment further enhances the safety and reliability of the circuit by incorporating the second protection sub-circuit.

[0115] like Figure 5 As shown, the input terminals of the second overvoltage protection chip U2806 are IN, IN-1, and IN-2, respectively. Each input terminal is interconnected and connected to one end of the fifth resistor R2831.

[0116] The threshold input terminal of the second overvoltage protection chip U2806 is connected to the other end of the fifth resistor R2831. The overvoltage protection threshold can be adjusted based on the voltage division effect of the fifth resistor R2831 and the sixth resistor R2830. Furthermore, the overvoltage protection threshold can be adjusted by setting the resistance values ​​of the fifth resistor R2831 and the sixth resistor R2830.

[0117] The enable terminal nEN of the second overvoltage protection chip U2806 is connected to the seventh resistor R2829.

[0118] The second overvoltage protection chip U2806 has three grounding terminals: GND, GND-1, and GND-2. Each grounding terminal is interconnected and grounded.

[0119] The output terminals of the second overvoltage protection chip U2806 are OUT, OUT-1, and OUT-2, respectively. Each output terminal is interconnected and connected to one end of the sixth capacitor C2851, one end of the seventh capacitor C2850, one end of the eighth resistor R2834, one end of the pull-up resistor R2833, and the drain of the second PMOS transistor Q2804.

[0120] In one specific embodiment, see Figure 5 It also includes: the ninth resistor R2849 and the tenth resistor R2835;

[0121] One end of the ninth resistor R2849 is used to connect to the first power supply;

[0122] The other end of the ninth resistor R2849 is connected to one end of the tenth resistor R2835 and the gate of the third NMOS transistor Q2806, respectively.

[0123] The other end of the tenth resistor R2835 is grounded.

[0124] It should be noted that the first power supply applies voltage to the gate of the third NMOS transistor Q2806 through the ninth resistor R2849 and the tenth resistor R2835.

[0125] In one specific embodiment, see Figure 5 It also includes: eleventh resistor R2850, twelfth resistor R2832, eighth capacitor C2858, and thirteenth resistor R2828;

[0126] One end of the eleventh resistor R2850 is connected to the enable terminal of the first overvoltage protection chip U2803;

[0127] The other end of the eleventh resistor R2850 is connected to one end of the twelfth resistor R2832, the other end of the pull-up resistor R2833, and the drain of the third NMOS transistor Q2806, respectively.

[0128] The other end of the twelfth resistor R2832 is connected to one end of the eighth capacitor C2858 and the gate of the second NMOS transistor Q2805, respectively, and the other end of the eighth capacitor C2858 is grounded;

[0129] The drain of the second NMOS transistor Q2805 is connected to the thirteenth resistor R2828, and is connected to the gate of the second PMOS transistor Q2804 through the thirteenth resistor R2828.

[0130] It should be noted that one end of the eleventh resistor R2850 is connected to the enable terminal ENN of the first overvoltage protection chip U2803 via the line DC_OVP_ENN. The gate lead-out pin 3 of the second PMOS transistor Q2804 is connected to the thirteenth resistor R2828, and is connected to the drain of the second NMOS transistor Q2805 via the thirteenth resistor R2828.

[0131] In one specific embodiment, see Figure 5 It also includes: the fourteenth resistor R2837 and the ninth capacitor C2857;

[0132] The two ends of the fourteenth resistor R2837 are respectively connected to the source and gate of the second PMOS transistor Q2804;

[0133] The ninth capacitor C2857 is connected in parallel across the fourteenth resistor R2837.

[0134] It should be noted that, as Figure 5 As shown, two pins, pin 4 and pin 8, are brought out from the source of the second PMOS transistor Q2804. Pins 4 and pin 8 are connected to each other and connected to the fourteenth resistor R2837 and the nineteenth capacitor, serving as the power output terminal. They are connected to the powered device through the line MB_VBUS_IN.

[0135] The second PMOS transistor Q2804 includes a body diode. The anode of the body diode is connected to the drain of the second PMOS transistor Q2804, and the body diode is connected to the source of the second PMOS transistor Q2804. Multiple pins are led out from the drain of the second PMOS transistor Q2804. These pins are pins 1 to 2 located to the lower left of the first PMOS transistor Q2808, and pins 5 to 7 located to the upper left of the first PMOS transistor. Pins 1 to 2 and pins 5 to 7 are interconnected and connected to a pull-up resistor R2833.

[0136] In another specific embodiment, a fifteenth resistor R2852 is also included, and the power transmission terminal of the second overvoltage protection chip U2806 is also connected to the fifteenth resistor R2852.

[0137] In one specific embodiment, see Figure 3 The power receiving device includes a voltage conversion module 61;

[0138] The input terminal of the voltage conversion module 61 is connected to the source of the first PMOS transistor 1 and the source of the second PMOS transistor 3, respectively.

[0139] The output of the voltage conversion module 61 is connected to the system to be powered 62 and is used to convert the received voltage into the target voltage.

[0140] It should be noted that the system to be powered 62 refers to a system that needs to receive electrical energy, and the target voltage refers to the voltage required for the system to be powered 62 to operate. For example, a smart POS device system. In this embodiment, the voltage conversion module 61 is used to convert the voltage provided by the first power source or the voltage provided by the second power source into the target voltage. It is understood that... Figure 3 In the diagram, DC_OVP represents the first protection sub-circuit; USB_OVP represents the first protection sub-circuit.

[0141] In one specific embodiment, the voltage conversion module may be a DC-DC buck module used to reduce the received voltage to the target voltage.

[0142] In one specific embodiment, see Figure 6 The DC-DC step-down module includes: anti-interference component B2801, tenth capacitor C2805, eleventh capacitor C2824, twelfth capacitor C2825, thirteenth capacitor C2803, fifteenth resistor R2803, sixteenth resistor R2804, step-down regulator U2801, fourteenth capacitor C2801, seventeenth resistor R2802, eighteenth resistor R2801, fifteenth capacitor C2826, first inductor L2801, sixteenth capacitor C2807, seventeenth capacitor C2808, eighteenth capacitor C2809, and anti-static chip D2811;

[0143] One end of the anti-interference element B2801 is connected to the line MB_VBUS_IN, and is connected to the source of the first PMOS transistor and the source of the second PMOS transistor respectively through MB_VBUS_IN.

[0144] The other end of the anti-interference element B2801 is connected to one end of the tenth capacitor C2805, one end of the eleventh capacitor C2824, one end of the twelfth capacitor C2825, one end of the thirteenth capacitor C2803, one end of the fifteenth resistor R2803, and the input terminal IN of the step-down regulator U2801.

[0145] The other end of the tenth capacitor C2805 is grounded, the other end of the eleventh capacitor C2824 is grounded, the other end of the twelfth capacitor C2825 is grounded, and the other end of the thirteenth capacitor C2803 is grounded.

[0146] The other end of the fifteenth resistor R2803 is connected to the enable terminal EN of the buck regulator U2801 and one end of the sixteenth resistor R2804, and the other end of the sixteenth resistor R2804 is grounded.

[0147] The grounding terminal GND of the buck regulator U2801 is grounded; the FB terminals of the buck regulator U2801 are connected to one end of the seventeenth resistor R2802, one end of the eighteenth resistor R2801, and one end of the fifteenth capacitor C2826, respectively.

[0148] The other end of the seventeenth resistor R2802 is grounded; the other end of the eighteenth resistor R2801 is connected to the other end of the fifteenth capacitor C2826 and the other end of the first inductor L2801, respectively.

[0149] The SW terminal of the step-down regulator is connected to one end of the fourteenth capacitor C2801 and one end of the first inductor L2801, respectively.

[0150] The BST terminal of the step-down regulator is connected to the other end of the fourteenth capacitor C2801;

[0151] The other end of the first inductor L2801 is connected to one end of the sixteenth capacitor C2807, one end of the seventeenth capacitor C2808, one end of the eighteenth capacitor C2809, and one end of the anti-static chip D2811.

[0152] The other end of the sixteenth capacitor C2807 is grounded, the other end of the seventeenth capacitor C2808 is grounded, the other end of the eighteenth capacitor C2809 is grounded, and the other end of the anti-static chip D2811 is grounded.

[0153] One end of the anti-static chip D2811 serves as the power output terminal, used to output the target voltage. For example... Figure 6 As shown, one end of the anti-static chip D2811 can be connected to the system being powered via the DC_4V_OUT line. The anti-interference component B2801 is used to suppress high-frequency noise, electromagnetic interference (EMI), and spike interference, improving power supply stability. In one example, the anti-interference component B2801 can be a high-current ferrite bead.

[0154] In one application example, taking a first power supply voltage of 12V, a second power supply voltage of 5V, and a target voltage of 4V as an example, the overall working principle of the dual power supply switching circuit provided by this utility model is explained as follows.

[0155] like Figures 4 to 6 As shown, DC_IN_12V represents the first power supply, and USB_5V_CON represents the second power supply.

[0156] When the DC_IN_12V power supply is plugged in, the third NMOS transistor Q2806 turns on. At this time, the drain voltage of the third NMOS transistor Q2806 is 0V, so the gate-source voltage Vgs of the second NMOS transistor Q2805 is 0V. When the second NMOS transistor Q2805 turns off, the gate-source voltage Vgs of the second PMOS transistor Q2804 is 0V, which in turn causes the second PMOS transistor Q2804 to also turn off.

[0157] Additionally, when the DC_IN_12V power supply is plugged in, the RC circuit (i.e., the delay sub-circuit) delays for 1 second, and then the first NMOS transistor Q2809 turns on, making the drain voltage of the first NMOS transistor Q2809 0V. As a result, the gate-source voltage Vgs of the first PMOS transistor Q2808 is less than 0V, and the first PMOS transistor Q2808 turns on, with its source outputting a 12V voltage, i.e., MB_VBUS_IN is 12V at this time.

[0158] Because the turn-off time of the second PMOS transistor Q2804 is much shorter than the turn-on time of the first PMOS transistor Q2808, the 12V voltage of MB_VBUS_IN will not flow back from the second PMOS transistor Q2804 to the second overvoltage protection chip U2806, thus improving the safety and reliability of the circuit. At this time, MB_VBUS_IN is 12V, which is stepped down to 4V by the buck regulator U2801 and output to the downstream power receiving system via DC_4V_OUT.

[0159] When both DC_IN_12V and USB_5V_CON are present, DC_IN_12V is higher than USB_5V_CON, so MB_VBUS_IN is 12V, and DC_IN_12V prioritizes powering the system. At this time, although the second PMOS transistor Q2804 is off, the 5V output from the second overvoltage protection chip U2806 can still leak to MB_VBUS_IN through the body diode of the second PMOS transistor Q2804. Since the body diode itself has a voltage drop of 0.4V, the leaked voltage is 4.6V. As mentioned above, MB_VBUS_IN is 12V, so DC_IN_12V powers the system. If the DC_IN_12V power supply is removed at this point, since the USB_5V_CON power supply is still in place, MB_VBUS_IN will drop from 12V to 4.6V. At this point, MB_VBUS_IN is 4.6V, which is then stepped down to 4V by the buck regulator U2801 to power the downstream system. Simultaneously, the gate-source voltage Vgs of the third NMOS transistor Q2806 is 0V, therefore, Q2806 is turned off, and the USB_5V_CON power supply... N is connected to the pull-up resistor R2833. At this time, the gate-source voltage Vgs of the second NMOS transistor Q2805 is 5V, which is greater than the turn-on voltage of the second NMOS transistor Q2805. Therefore, the second NMOS transistor Q2805 is turned on, which makes the second PMOS transistor Q2804 fully turned on as well. At this time, MB_VBUS_IN is 5V. The buck regulator U2801 converts the received 5V voltage into 4V voltage and outputs it to the downstream system to be powered, thus supplying power to the downstream system to be powered.

[0160] When the DC_IN_12V power is plugged in again, as mentioned above, the second PMOS transistor Q2804 is turned off. However, due to the 1-second delay of the delay sub-circuit 7, the first NMOS transistor Q2809 does not turn on immediately and remains off for the 1-second delay, thus keeping the first PMOS transistor Q2808 off as well. Due to the characteristics of the first overvoltage protection chip U2803, it only outputs 12V after 95ms of DC_IN_12V being input to it. Therefore, before 95ms, the MB_VBUS_IN voltage is provided by USB_5V_CON through the body diode of the second PMOS transistor Q2804. At this time, MB_VBUS_IN is 4.6V. Afterwards, the buck regulator U2801 converts the 4.6V voltage to 4V and outputs it to the downstream power receiving system. After 95ms, the first overvoltage protection chip U2803 outputs a 12V voltage. At this time, since the delay of the delay sub-circuit 7 has not yet ended, the first PMOS transistor Q2808 is still in the off state. Although the first PMOS transistor Q2808 is off, the 12V voltage can leak to MB_VBUS_IN through the body diode of the first PMOS transistor Q2808. Since the body diode itself has a voltage drop of 0.4V, the leaked voltage is 11.6V. Therefore, the voltage of MB_VBUS_IN will change from 4.6V to 11.6V. At this time, the buck regulator U2801 converts the 11.6V voltage to 4V and supplies the 4V voltage to the downstream system waiting to be powered. After 1 second, the first NMOS transistor Q2809 turns on, making the first PMOS transistor Q2808 fully turn on. At this time, the voltage of MB_VBUS_IN will change from 11.6V to 12V, and the buck regulator U2801 will step down the voltage to output 4V to supply the downstream system waiting to be powered.

[0161] As described above, the dual-power supply switching circuit provided by this utility model enables automatic switching between two power supplies with different voltages. During the switching process, the input terminal of the powered device remains continuously powered, preventing power loss, shutdown, or restart. This solves the problem of existing technologies struggling to achieve automatic switching between two power supplies with different voltages without system shutdown or restart. It provides a solution for POS and other smart devices to automatically switch between two external power supplies without battery power, ensuring the system doesn't shut down or restart. After using the circuit provided by this utility model, in actual production, the design of smart devices without battery power can share a common PCBA, saving costs. Furthermore, when POS devices equipped with the circuit provided by this utility model are mass-produced, users can more flexibly choose the power supply method, and the switching process will not affect the user experience of the POS device.

[0162] The above provides a detailed description of a dual-power supply switching circuit provided by this utility model. For those skilled in the art, based on the ideas of the embodiments of this utility model, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A dual-power supply switching circuit, characterized in that, include: First PMOS transistor, first NMOS transistor, second PMOS transistor, second NMOS transistor, third NMOS transistor, pull-up resistor; The gate of the first NMOS transistor is used to receive the first power supply, and the drain of the first NMOS transistor is connected to the gate of the first PMOS transistor. The drain of the first PMOS transistor is used to receive the first power supply. The gate of the third NMOS transistor is used to receive the first power supply, and the drain of the third NMOS transistor is connected to the gate of the second NMOS transistor. The drain of the second PMOS transistor is connected to one end of the pull-up resistor to receive the second power supply; the other end of the pull-up resistor is connected to the drain of the third NMOS transistor and the gate of the second NMOS transistor, respectively. The drain of the second NMOS transistor is connected to the gate of the second PMOS transistor; The source of the first PMOS transistor and the source of the second PMOS transistor are respectively used to connect to the input terminal of the powered device; the source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all grounded; The voltage of the first power source is greater than the voltage of the second power source.

2. The circuit according to claim 1, characterized in that, It also includes a delay sub-circuit, the input of which is used to receive a first power supply; The output terminal of the delay sub-circuit is connected to the gate of the first NMOS transistor and ground, respectively.

3. The circuit according to claim 2, characterized in that, The delay sub-circuit includes: a first delay resistor, a second delay resistor, and a first delay capacitor; One end of the first delay resistor is used to connect to the first power supply; The other end of the first delay resistor is connected to one end of the second delay resistor, one end of the first delay capacitor, and the gate of the first NMOS transistor, respectively. The other end of the first delay capacitor and the other end of the second delay resistor are connected to the source of the first NMOS transistor and grounded.

4. The circuit according to claim 1, characterized in that, It also includes a first protection sub-circuit; the first protection sub-circuit includes: a first capacitor, a second capacitor, a first resistor, a first overvoltage protection chip, and a second resistor; One end of the first capacitor is connected to the input terminal of the first overvoltage protection chip and is used to receive the first power supply; the other end of the first capacitor is grounded. The threshold input terminal of the first overvoltage protection chip is connected to one end of the second capacitor and one end of the first resistor, respectively; the other end of the second capacitor is connected to the other end of the first resistor and grounded. The grounding terminal of the first overvoltage protection chip is connected to ground; The output terminal of the first overvoltage protection chip is connected to the drain of the first PMOS transistor; The enable terminal of the first overvoltage protection chip is used to connect to the gate of the second NMOS transistor; The status indicator terminal of the first overvoltage protection chip is connected to one end of the second resistor, and the other end of the second resistor is grounded.

5. The circuit according to claim 1, characterized in that, It also includes a second protection sub-circuit; the second protection sub-circuit includes: a fifth resistor, a sixth resistor, a seventh resistor, a sixth capacitor, a seventh capacitor, an eighth resistor, and a second overvoltage protection chip; One end of the fifth resistor is connected to the input terminal of the second overvoltage protection chip and is used to connect to the second power supply; The other end of the fifth resistor is connected to one end of the sixth resistor and the threshold input terminal of the second overvoltage protection chip; the other end of the sixth resistor is grounded. The enable terminal of the second overvoltage protection chip is connected to one end of the seventh resistor; The other end of the seventh resistor is connected to the ground terminal of the second overvoltage protection chip and grounded; The output terminal of the second overvoltage protection chip is connected to one end of the sixth capacitor, one end of the seventh capacitor, one end of the eighth resistor, one end of the pull-up resistor, and the drain of the second PMOS transistor, respectively. The other end of the sixth capacitor, the other end of the seventh capacitor, and the other end of the eighth resistor are grounded.

6. The circuit according to claim 1, characterized in that, It also includes: a third capacitor, a third resistor, a fourth capacitor, a fifth capacitor, and a fourth resistor; The source of the first PMOS transistor is connected to one end of the third capacitor, one end of the third resistor, one end of the fourth capacitor, and one end of the fifth capacitor, respectively. The other end of the third capacitor is connected to the gate of the first PMOS transistor. The other end of the third resistor is connected to the other end of the third capacitor and one end of the fourth resistor; the other end of the fourth resistor is connected to the drain of the first NMOS transistor. The other end of the fourth capacitor and the other end of the fifth capacitor are both grounded.

7. The circuit according to claim 1, characterized in that, Also includes: Ninth resistor, tenth resistor; One end of the ninth resistor is used to connect to the first power source; The other end of the ninth resistor is connected to one end of the tenth resistor and the gate of the third NMOS transistor, respectively. The other end of the tenth resistor is grounded.

8. The circuit according to claim 4, characterized in that, Also includes: Eleventh resistor, twelfth resistor, eighth capacitor, thirteenth resistor; One end of the eleventh resistor is connected to the enable terminal of the first overvoltage protection chip; The other end of the eleventh resistor is connected to one end of the twelfth resistor, the other end of the pull-up resistor, and the drain of the third NMOS transistor, respectively. The other end of the twelfth resistor is connected to one end of the eighth capacitor and the gate of the second NMOS transistor, respectively, and the other end of the eighth capacitor is grounded; The drain of the second NMOS transistor is connected to the thirteenth resistor, and is also connected to the gate of the second PMOS transistor through the thirteenth resistor.

9. The circuit according to claim 1, characterized in that, Also includes: Fourteenth resistor, ninth capacitor; The two ends of the fourteenth resistor are respectively connected to the source and gate of the second PMOS transistor; The ninth capacitor is connected in parallel across the fourteenth resistor.

10. The circuit according to any one of claims 1-9, characterized in that, The power receiving device includes a voltage conversion module; The input terminal of the voltage conversion module is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, respectively. The output of the voltage conversion module is connected to the system to be powered, and is used to convert the received voltage into the target voltage.

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