Circuit board

Abstract

The utility model discloses a circuit board, and relates to the technical field of electronic circuit additive manufacturing. The circuit board comprises a base material, an inner side plating seed layer attached to the base material, and an outer side plating seed layer attached to the inner side plating seed layer, the inner side plating seed layer and the outer side plating seed layer are laminated and are consistent in pattern; and a metal plating layer covering the inner plating seed layer and the outer plating seed layer. According to the application, the patterned outer side plating seed layer is directly printed on the metal layer, then the metal layer which is not covered by the seed layer is etched, the inner side plating seed layer which is consistent with the pattern below the outer side plating seed layer is obtained, and during plating, the metal plating layer is simultaneously and integrally formed on the side wall of the inner side plating seed layer and the outer side plating seed layer in a growing manner; as the inner side plating seed layer is made of metal, stable anchoring points can be formed at the joint of the metal plating layer and the inner side plating seed layer, so that the overall combination stability of the metal plating layer is improved.

Description

Technical Field

[0001] This utility model belongs to the field of electronic circuit additive manufacturing technology, and particularly relates to a circuit board and its manufacturing method. Background Technology

[0002] Currently, electronic additive manufacturing has begun to be gradually applied and implemented. It mainly forms conductive patterns directly on the substrate through printing processes. Although it has advantages such as simple process, high efficiency and environmental protection compared to traditional etching, it still has shortcomings in terms of conductivity, solderability and oxidation resistance. Therefore, many manufacturers have begun to improve its process.

[0003] Among them, the improved scheme of first forming a patterned seed layer directly using the printing process, and then forming a patterned metal coating directly on the seed layer through the plating process can effectively solve the shortcomings of conductive paste in terms of conductivity, solderability, and oxidation resistance. However, the bonding stability of the metal coating on the printed seed layer still needs to be improved. Utility Model Content

[0004] In view of this, one objective of this utility model is to propose a method for manufacturing a circuit board to solve the problem of poor bonding stability of the metal plating layer on the printing seed layer, which affects the reliability of the circuit board.

[0005] In some illustrative embodiments, the method of manufacturing the circuit board includes: providing a metal laminate comprising: a substrate and a metal layer attached to the substrate; printing conductive paste on the metal layer to form a patterned outer plating seed layer, and etching the metal layer not covered by the outer plating seed layer to form an inner plating seed layer; wherein the inner plating seed layer and the outer plating seed layer are stacked and have the same pattern; and depositing a metal plating layer covering the inner plating seed layer and the outer plating seed layer on the exposed surfaces of the inner plating seed layer and the outer plating seed layer.

[0006] In some optional embodiments, the metal layer includes: a first metal layer attached to one side of the substrate and a second metal layer attached to the other side of the substrate; the fabrication method includes: printing a first conductive paste and a second conductive paste on the first metal layer and the second metal layer respectively to form a patterned first outer plating seed layer and a second outer plating seed layer, and etching the first metal layer and the second metal layer not covered by the first outer plating seed layer and the second outer plating seed layer to form a first inner plating seed layer and a second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; depositing a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer on the exposed surfaces of the first inner plating seed layer and the first outer plating seed layer, and depositing a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer on the exposed surfaces of the second inner plating seed layer and the second outer plating seed layer.

[0007] In some optional embodiments, the manufacturing method further includes: forming a blind hole through the substrate and the first metal layer to the second metal layer on the metal laminate; printing a third conductive paste in the blind hole to form a conductive pillar that realizes conductive interconnection between the first metal layer and the second metal layer; and then printing a first conductive paste on the first metal layer to form a first outer plating seed layer covering the conductive pillar; or, printing the first conductive paste on the first metal layer while simultaneously forming the conductive pillar and the first outer plating seed layer.

[0008] In some alternative embodiments, before forming the blind via, a second conductive paste is first printed on the second metal layer to form a second outer plating seed layer; wherein the second outer plating seed layer covers the position of the blind via relative to the second metal layer; wherein the blind via does not damage the second metal layer; or, the blind via damages but does not penetrate the second metal layer; or, the blind via damages and penetrates the second metal layer.

[0009] In some optional embodiments, after forming the first outer plating seed layer and the second outer plating seed layer, the method further includes: forming a through hole in the metal laminate that penetrates the substrate, the first metal layer, the second metal layer, the first outer plating seed layer, and the second outer plating seed layer, and forming a conductive structure at least on the hole wall of the through hole to achieve conductive interconnection between the first metal layer and the second metal layer; during the process of integrally forming a first metal plating layer covering both the first inner plating seed layer and the first outer plating seed layer on their exposed surfaces, and integrally forming a second metal plating layer covering both the second inner plating seed layer and the second outer plating seed layer on their exposed surfaces, the method further includes: plating a third metal plating layer on the conductive structure on the hole wall of the through hole; wherein the first metal plating layer, the second metal plating layer, and the third metal plating layer are an integral structure.

[0010] In some alternative embodiments, the conductive structure is one or more of a metal, conductive carbon black, and conductive graphene.

[0011] In some alternative embodiments, the metal layer is one or more of gold, silver, copper, iron, nickel, zinc, and aluminum; and / or, the metal layer is an ultrathin metal foil layer with a thickness of 1-10 μm; and / or, the conductive paste is a low-temperature conductive paste containing resin and conductive particles; and / or, the etching is a flash etching process.

[0012] Another objective of this invention is to provide a circuit board that addresses the problems existing in the prior art.

[0013] In some illustrative embodiments, the circuit board includes: a substrate, an inner plating seed layer attached to the substrate, and an outer plating seed layer attached to the inner plating seed layer; the inner plating seed layer and the outer plating seed layer are stacked and have the same pattern; and a metal plating layer covering the inner plating seed layer and the outer plating seed layer.

[0014] In some optional embodiments, the inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; the outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; a conductive post connects the first inner plating seed layer and the second inner plating seed layer through the substrate; the metal plating layer includes: a first metal plating layer covering the first inner plating seed layer and the first outer plating seed layer, and a second metal plating layer covering the second inner plating seed layer and the second outer plating seed layer.

[0015] In some optional embodiments, the inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate; the outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; wherein the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern; a through-hole is formed through the substrate, the first inner plating seed layer, the second inner plating seed layer, the first outer plating seed layer and the second outer plating seed layer, and at least a conductive structure is formed on the hole wall of the through-hole to realize the conductive interconnection between the first inner plating seed layer and the second inner plating seed layer;

[0016] The metal coating includes: a first metal coating covering the first inner plating seed layer and the first outer plating seed layer, a second metal coating covering the second inner plating seed layer and the second outer plating seed layer, and a third metal coating formed on the conductive structure on the wall of the through hole; wherein the first metal coating, the second metal coating and the third metal coating are an integral structure.

[0017] Compared with the prior art, this application has the following advantages:

[0018] This application directly prints a patterned outer plating seed layer on the metal layer, and then etches the metal layer not covered by the seed layer, thereby obtaining an inner plating seed layer on the metal layer that is stacked with the outer plating seed layer and has the same pattern. At this time, the sidewall of the inner plating seed layer is exposed. Therefore, the metal plating layer formed during plating will grow integrally with the sidewall of the inner plating seed layer and the outer plating seed layer at the same time. Since the inner plating seed layer is metal, the metal plating layer will form a stable anchor point at the junction with the inner plating seed layer, thereby improving the overall bonding stability of the metal plating layer. Attached Figure Description

[0019] Figure 1 This is a flowchart example of the circuit board manufacturing method in this utility model embodiment;

[0020] Figure 2 This is a process example of the circuit board manufacturing method in this utility model embodiment;

[0021] Figure 3 This is a second example of the manufacturing process of the circuit board in this utility model embodiment;

[0022] Figure 4 This is a third example of the process for manufacturing the circuit board in this utility model embodiment;

[0023] Figure 5 This is the fourth example of the process for manufacturing the circuit board in this utility model embodiment;

[0024] Figure 6 This is the fifth example of the process for manufacturing the circuit board in this utility model embodiment;

[0025] Figure 7 This is a sixth example of the process for manufacturing the circuit board in this utility model embodiment;

[0026] Figure 8 This is a structural example of the circuit board manufacturing method in this utility model embodiment;

[0027] Figure 9 This is a second structural example of the circuit board manufacturing method in this utility model embodiment. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0029] It should be noted that, where there is no conflict, the various technical features in the embodiments of this utility model can be combined with each other.

[0030] This utility model discloses a method for manufacturing a circuit board, specifically, as follows: Figure 1-2 As shown, Figure 1 This is a flowchart example of the circuit board manufacturing method in this utility model embodiment; Figure 2 This is a process example of a circuit board manufacturing method in this utility model embodiment; the manufacturing method includes:

[0031] Step S11: Provide a metal laminate 100; the metal laminate 100 includes: a substrate 10, and a metal layer 20 attached to the substrate 10;

[0032] Step S12: Print conductive paste on metal layer 20 to form patterned outer plating seed layer 30, and etch the metal layer 20 not covered by outer plating seed layer 30 to form inner plating seed layer 40.

[0033] Among them, the inner seed layer 40 and the outer seed layer 30 are stacked and have the same pattern;

[0034] Step S13: A metal plating layer 50 covering the inner and outer seed layers 40 is deposited on the exposed surfaces of the inner and outer seed layers 30.

[0035] The exposed surface of the outer seed layer 30 refers to the surface of the outer seed layer 30 other than the bonding surface with the inner seed layer 40 (i.e., the outer surface and sidewall), while the exposed surface of the inner seed layer 40 refers to the sidewall of the inner seed layer 40.

[0036] This application directly prints a patterned outer plating seed layer on the metal layer, and then etches the metal layer not covered by the seed layer, thereby obtaining an inner plating seed layer on the metal layer that is stacked with the outer plating seed layer and has the same pattern. At this time, the sidewall of the inner plating seed layer is exposed. Therefore, the metal plating layer formed during plating will grow integrally with the sidewall of the inner plating seed layer and the outer plating seed layer at the same time. Since the inner plating seed layer is metal, the metal plating layer will form a stable anchor point at the junction with the inner plating seed layer, thereby improving the overall bonding stability of the metal plating layer.

[0037] In this embodiment of the invention, the substrate is used to support a metal layer on its surface. The metal layer is an insulating material and can be used to make conductive structures, such as antennas, traces, pads, electrodes, etc. In this embodiment of the invention, the metal layer is mainly used to make an inner plated seed layer and serves as part of the main conductive structure.

[0038] In this embodiment of the invention, the metal layer in the metal laminate can be formed on the substrate by conventional methods such as deposition or lamination. The metal layer can be one or more of gold, silver, copper, iron, nickel, zinc, and aluminum. The substrate can be a rigid board or a flexible board. Rigid boards include, but are not limited to, FR-4, CEM-1, 22F, CEM-3, wood, glass, plastic, PMMA (acrylic), etc. Flexible boards include, but are not limited to, PET, PVC, PU, ​​PC, PP, PA, PI, CPI (transparent PI), TPE, TPU, TPV, etc. For example, the metal laminate is a copper-clad laminate, with copper foil as the metal layer and PI or PET as the substrate. The copper foil is not limited to being formed on PI or PET by adhesive lamination or chemical / physical deposition.

[0039] The thickness of the metal layer in this embodiment ranges from 0.1 to 100 μm, and can be selected according to product performance requirements or process requirements, including but not limited to 0.1 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 15 μm, 20 μm, 30 μm, 40 μm, 60 μm, 80 μm, and 100 μm.

[0040] In this embodiment of the utility model, there is no explicit limitation on the thickness range of the substrate. The thickness range is sufficient to meet the product performance requirements, and is usually between 0.1 and 500 μm, including but not limited to 0.1 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 200 μm, 250 μm, 300 μm, 400 μm, and 500 μm.

[0041] The conductive paste in this embodiment of the invention can be a low-temperature conductive paste with resin as the binder phase, or a high-temperature conductive paste with glass frit as the binder phase. For example, this embodiment of the invention uses a low-temperature conductive paste, which, compared to a high-temperature conductive paste, has the advantages of simpler processing, lower curing temperature, and a wider range of substrate options.

[0042] The low-temperature conductive paste in this embodiment mainly includes resin and conductive filler; wherein, the conductive filler is not limited to one or more of gold, silver, copper, iron, nickel, zinc, aluminum, palladium, conductive carbon black, and graphene; since the final conductive structure in this embodiment is a structure in which the inner seed layer is coated with a metal layer and the outer seed layer is wrapped within it, there are no special requirements for the resin in this embodiment, as long as it can stably adhere the outer seed layer to the metal layer during the etching and plating process. Also, because of the above structure, the adhesion of the resin can be sacrificed to a certain extent, thereby increasing the solid content of the conductive filler in the low-temperature conductive paste, thereby improving the plating quality and efficiency, as well as the conductivity of the final conductive structure.

[0043] The conductive filler in the low-temperature conductive slurry of this utility model embodiment may further include a low-melting-point metal / alloy that can form an alloy phase with the metal layer and / or metal plating, thereby increasing the bonding strength between it and the metal layer and / or metal plating; wherein, the low-melting-point metal / alloy includes, but is not limited to, SnBi, Sn, and Bi.

[0044] In this embodiment of the present invention, the first conductive paste, the second conductive paste, and the third conductive paste may be the same type of conductive paste, or they may be conductive pastes with different compositions. This application does not impose any restrictions on this.

[0045] In this embodiment of the invention, step S12, which involves printing conductive paste on the metal layer to form a patterned outer plating seed layer (and printed conductive layer), is not limited to printing methods such as screen printing or inkjet printing. It can directly form a printed pattern on the metal layer, and after curing, a patterned outer plating seed layer is obtained. The thickness of the outer plating seed layer in this embodiment can range from 0.1 to 100 μm; in a preferred embodiment, the maximum thickness of the outer plating seed layer does not exceed 35 μm, thereby improving the subsequent plating efficiency. Further, the thickness of the outer plating seed layer can be 1 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 22 μm, 25 μm, 30 μm, or 35 μm.

[0046] In this embodiment of the present invention, step S12, etching the metal layer not covered by the outer plating seed layer to form the inner plating seed layer, may specifically include:

[0047] Step S121: Form an etch protective layer on the outer seed layer that has the same pattern as the outer seed layer and covers the outer seed layer.

[0048] Step S122: Etch the metal layer to remove the metal layer not covered by the outer plating seed layer, forming an inner plating seed layer that is stacked with the outer plating seed layer and has the same pattern.

[0049] Step S123: Remove the etched protective layer to expose the outer seed layer.

[0050] The applicant discovered that an outer seed layer formed by a low-temperature conductive paste with a thickness of 2 μm can withstand low-level etching processes, namely flash etching (also known as differential etching or rapid etching process). During flash etching, it is essentially unaffected. Therefore, in some embodiments, the metal layer can be an ultra-thin metal foil layer with a thickness ranging from 0.1 to 10 μm (including but not limited to ultra-thin copper-clad laminates). Combined with the flash etching process, the outer seed layer can directly serve as an etching protection layer to protect the metal layer beneath its pattern from being flash-etched away. Therefore, there is no need to configure an additional etching protection layer on the outer seed layer, simplifying the process and reducing material consumption. Thus, in this embodiment, the thickness of the outer seed layer is not less than 2 μm.

[0051] The applicant also found that if the thickness of the metal layer is less than 1 μm, it will reduce the bonding force between the inner plating seed layer and the metal plating layer; while if it is greater than 3 μm, the material cost will increase significantly; therefore, the thickness of the metal layer in the preferred embodiment can be 1-3 μm.

[0052] Although there are corresponding definitions for conventional chemical etching and flash etching in the industry, in order to facilitate a quick understanding of this application by those skilled in the art, a brief description of the two is provided here:

[0053] For conventional etching, commonly used acidic etching solutions are mostly copper chloride (containing copper chloride, hydrochloric acid, and oxidant) and ferric chloride (containing ferric chloride and hydrochloric acid), while commonly used alkaline etching solutions are mostly ammonia. In order to ensure thorough etching, the etching solution concentration is relatively high, the etching speed is moderate, and it is suitable for thicker copper foils. The continuous etching time is usually from a few minutes to tens of minutes.

[0054] Flash etching often uses acidic etching solutions, such as sulfuric acid-hydrogen peroxide (containing sulfuric acid, hydrogen peroxide, and stabilizers). In order to achieve precise etching, the concentration of the etching solution is low and the etching speed is fast. It is suitable for ultra-thin copper foils, and the continuous etching time is usually from a few seconds to tens of seconds.

[0055] Those skilled in the art should understand that there are many formulation processes for implementing the above-mentioned conventional etching and flash etching processes. The above examples of etching solutions and etching parameters are only for the purpose of enabling those skilled in the art to quickly understand the differences between the two, and should not affect the scope of application of the technical solutions in this application.

[0056] Furthermore, in order to enable those skilled in the art to quickly distinguish between the two, the continuous etching time of flash etching in this application is limited to no more than 60 seconds, such as 5 seconds, 10 seconds, 15 seconds, 20 seconds, 30 seconds, 40 seconds, 50 seconds, and 60 seconds; the continuous etching time of conventional etching is limited to no less than 180 seconds.

[0057] The metal laminate in this embodiment of the present invention can be a single-sided metal laminate with a metal layer attached to one side of the substrate, or a double-sided metal laminate with metal layers attached to both opposite sides of the substrate. For the double-sided metal laminate, the above process can be performed on only one metal layer or on both metal layers to obtain the above structure on both sides.

[0058] In the case of a double-sided metal laminate, the metal layers on both sides may be made of the same metal composition or different metal compositions, and this application does not impose any restrictions on this.

[0059] The first metal coating, the second metal coating, and the third metal coating in this embodiment of the present invention may have the same metal composition or different metal compositions.

[0060] Specifically, such as Figure 3 As shown, Figure 3 This is a second example of the circuit board manufacturing process in this utility model embodiment; this utility model embodiment discloses an implementation example for a double-sided metal laminate; wherein, the metal layer 100 in the metal laminate includes: a first metal layer 21 attached to one side of the substrate 10, and a second metal layer 22 attached to the other side of the substrate 10; the manufacturing method includes:

[0061] Step S21: Provide the above-mentioned double-sided metal laminate 100;

[0062] Step S22: Print the first conductive paste and the second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and the second outer plating seed layer 32, and etch the first metal layer 21 and the second metal layer 22 that are not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and the second inner plating seed layer 42.

[0063] The first inner plated seed layer 41 and the first outer plated seed layer 31 are stacked and have the same pattern, and the second inner plated seed layer 42 and the second outer plated seed layer 32 are stacked and have the same pattern.

[0064] Step S23: A first metal plating layer 51 covering the first inner plated seed layer 41 and the first outer plated seed layer 31 is plated on the exposed surfaces of the first inner plated seed layer 41 and the first outer plated seed layer 31. A second metal plating layer 52 covering the second inner plated seed layer 42 and the second outer plated seed layer 32 is plated on the exposed surfaces of the second inner plated seed layer 42 and the second outer plated seed layer 32.

[0065] like Figure 4 As shown, Figure 4 This is a third example of the manufacturing process of the circuit board in this utility model embodiment; in some embodiments, the manufacturing method in this utility model embodiment may further include:

[0066] Step S31: Provide the above-mentioned double-sided metal laminate 100;

[0067] Step S32: Form a blind hole 60 on the metal laminate 100 that penetrates the substrate 10 and the first metal layer 21 and extends to the second metal layer 22; wherein, the blind hole 60 forming process is not limited to laser ablation or mechanical drilling;

[0068] Step S33: Print a third conductive paste in the blind hole 60 to form a conductive pillar 70 that realizes the conductive interconnection between the first metal layer 21 and the second metal layer 22;

[0069] Step S34: Print the first conductive paste and the second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and the second outer plating seed layer 32, and etch the first metal layer 21 and the second metal layer 22 that are not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and the second inner plating seed layer 42; wherein, the first outer plating seed layer 31 formed by the first conductive paste covers the surface of the conductive post 70 on this side.

[0070] The first inner plated seed layer 41 and the first outer plated seed layer 31 are stacked and have the same pattern, and the second inner plated seed layer 42 and the second outer plated seed layer 32 are stacked and have the same pattern.

[0071] Step S35: A first metal plating layer 51 covering the first inner plated seed layer 41 and the first outer plated seed layer 31 is plated on the exposed surfaces of the first inner plated seed layer 41 and the first outer plated seed layer 31. A second metal plating layer 52 covering the second inner plated seed layer 42 and the second outer plated seed layer 32 is plated on the exposed surfaces of the second inner plated seed layer 42 and the second outer plated seed layer 32.

[0072] In this embodiment, step S33 can be omitted, and the conductive pillar 70 and the first outer plating seed layer 31 are formed simultaneously with the printing of the first conductive paste on the first metal layer 21 in step S34. That is, both the conductive pillar 70 and the first outer plating seed layer 31 can be formed from the first conductive paste.

[0073] In this embodiment, conductive interconnection between the two sides of the substrate is achieved through a via-plugging method using conductive paste. Furthermore, since this via-plugging method is directly based on blind holes in the metal laminate, the process is simple and avoids issues such as ink leakage and contamination associated with through-holes, making it suitable for the production of flexible boards such as FPCs.

[0074] like Figure 5 As shown, Figure 5 This is a fourth example of the manufacturing method in this utility model embodiment; in some embodiments, the manufacturing method in this utility model embodiment may further include:

[0075] Step S41: Provide the above-mentioned double-sided metal laminate 100;

[0076] Step S42: Print the second conductive paste on the second metal layer 22 to form the second outer plating seed layer 32;

[0077] Step S43: A blind hole is formed on the metal laminate 100, penetrating the substrate 10 and the first metal layer 21 and reaching the second metal layer 22; wherein, the second outer plated seed layer 32 covers the position of the blind hole 60 relative to the second metal layer 22.

[0078] Wherein, the blind hole 60 may not damage the second metal layer 22; or, the blind hole 60 may damage but not penetrate the second metal layer 22; or, the blind hole 60 may damage and penetrate the second metal layer 22; wherein, the blind hole 60 forming process is not limited to laser ablation or mechanical drilling;

[0079] Step S44: Print a third conductive paste in the blind hole 60 to form a conductive pillar 70 that realizes the conductive interconnection between the first metal layer 21 and the second metal layer 22;

[0080] Step S45: Print a first conductive paste on the first metal layer 21 to form a patterned first outer plating seed layer 31, and etch the first metal layer 21 and the second metal layer 22 that are not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and the second inner plating seed layer 42; wherein, the first outer plating seed layer 31 formed by the first conductive paste covers the surface of the conductive post 70 on this side.

[0081] The first inner plated seed layer 41 and the first outer plated seed layer 31 are stacked and have the same pattern, and the second inner plated seed layer 42 and the second outer plated seed layer 32 are stacked and have the same pattern.

[0082] Step S46: A first metal plating layer 51 covering the first inner plated seed layer 41 and the first outer plated seed layer 31 is plated on the exposed surfaces of the first inner plated seed layer 41 and the first outer plated seed layer 31; a second metal plating layer 52 covering the second inner plated seed layer 42 and the second outer plated seed layer 32 is plated on the exposed surfaces of the second inner plated seed layer 42 and the second outer plated seed layer 32.

[0083] In this embodiment, step S44 can be omitted, and the conductive pillar 70 and the first outer plating seed layer 31 are formed simultaneously with the printing of the first conductive paste on the first metal layer 21 in step S34. That is, both the conductive pillar 70 and the first outer plating seed layer 31 can be formed from the first conductive paste.

[0084] In this embodiment, before the blind hole is formed, a second outer plating seed layer is printed on the corresponding position of the blind hole on the second metal layer. This can avoid the problem of laser ablation or mechanical drilling directly penetrating the second metal layer, which would cause the blind hole structure to fail. The second outer plating seed layer adds a layer of protection to the second metal layer, avoiding the increased difficulty of subsequent hole plugging and problems such as ink leakage and contamination. This is especially suitable for embodiments where the second metal layer uses an ultra-thin metal foil layer.

[0085] like Figure 6 As shown, Figure 6 This is a fifth example of the manufacturing method in this utility model embodiment; in other embodiments, after forming the first outer plating seed layer 31 and the second outer plating seed layer 32, the process may further include: forming a through hole 60' penetrating the substrate 10, the first metal layer 21, the second metal layer 22, the first outer plating seed layer 31 and the second outer plating seed layer 32 on the metal laminate 100, and forming a conductive structure 70' at least on the hole wall of the through hole 60' to achieve conductive interconnection between the first metal layer 21 and the second metal layer 22; during the process of integrally forming a first metal plating layer 51 covering both the first inner plating seed layer 41 and the first outer plating seed layer 31 on the exposed surfaces, and integrally forming a second metal plating layer 52 covering both the second inner plating seed layer 42 and the second outer plating seed layer 32 on the exposed surfaces, the process may further include: plating a third metal plating layer 53 on the conductive structure 70' on the hole wall of the through hole 60'; wherein, the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integral structure.

[0086] Specifically, the method for manufacturing the circuit board in this embodiment of the present invention may include:

[0087] Step S51: Provide the above-mentioned double-sided metal laminate 100;

[0088] Step S52: Print the first conductive paste and the second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and the second outer plating seed layer 32, and etch the first metal layer 21 and the second metal layer 22 that are not covered by the first outer plating seed layer 31 and the second outer plating seed layer 32 to form a first inner plating seed layer 41 and the second inner plating seed layer 42.

[0089] The first outer plating seed layer 31 and the second outer plating seed layer 32 have an overlapping area in the horizontal direction of the metal laminate 100.

[0090] Step S53: Form a through hole 60' on the metal laminate 100 that penetrates the substrate 10, the first inner plating seed layer 41, the second inner plating seed layer 42, the first outer plating seed layer 31, and the second outer plating seed layer 32, and form a conductive structure 70' at least on the hole wall of the through hole 60' to achieve conductive interconnection between the first inner plating seed layer 41 and the second inner plating seed layer 42;

[0091] Step S54: A first metal plating layer 51 covering the first inner seed layer 41 and the first outer seed layer 31 is integrally formed on their exposed surfaces; a second metal plating layer 52 covering the second inner seed layer 42 and the second outer seed layer 32 is integrally formed on their exposed surfaces; and a third metal plating layer 53 is plated on the conductive structure 70' on the wall of the through hole 60'. The first metal plating layer 51, the second metal plating layer 52, and the third metal plating layer 53 are integral structures.

[0092] The conductive structure 70' can also be formed simultaneously on the first inner plated seed layer 41, the second inner plated seed layer 42, the first outer plated seed layer 31, and the second outer plated seed layer 32.

[0093] In the embodiments, the conductive structure can be one or more of metal, conductive carbon black, and conductive graphene. It can be formed by a conductive paste containing one or more of metal particles (i.e., through-hole printing process), conductive carbon black (i.e., black hole process), and conductive graphene (i.e., shadowing process).

[0094] like Figure 7 As shown, Figure 7 This is a sixth example of the manufacturing process in the embodiments of this utility model; in other embodiments, the manufacturing method of the circuit board in the embodiments of this utility model may include:

[0095] Step S61: Provide the above-mentioned double-sided metal laminate 100;

[0096] Step S62: Print the first conductive paste and the second conductive paste on the first metal layer 21 and the second metal layer 22 respectively to form a patterned first outer plating seed layer 31 and the second outer plating seed layer 32.

[0097] The first outer plating seed layer 31 and the second outer plating seed layer 32 have an overlapping area in the horizontal direction of the metal laminate 100.

[0098] Step S63: Form a through hole 60' through the substrate 10, the first metal layer 21, the second metal layer 22, the first outer outer plating seed layer 31 and the second outer outer plating seed layer 32 on the metal laminate 100, and form a conductive interconnection structure 70' (conductive carbon black or conductive graphene) on the hole wall of the through hole 60' and on the surface of the first metal layer 21, the second metal layer 22, the first outer outer plating seed layer 31 and the second outer outer plating seed layer 32.

[0099] Step S64: Etch the first metal layer 21, the second metal layer 22 and the conductive carbon black or conductive graphene above them by a flash etching process to form the first inner plated seed layer 41 and the second inner plated seed layer 42.

[0100] At this time, conductive structures 70' of conductive carbon black or conductive graphene are formed on the walls of the first outer seed layer 31, the second outer seed layer 32, the first inner seed layer 41, the second inner seed layer 42, and the through hole 60', except for the sidewalls of the first inner seed layer 41 and the second inner seed layer 42 that are away from the through hole 60'.

[0101] Step S65: A first metal plating layer 51 covering the first inner plated seed layer 41 and the first outer plated seed layer 31 is integrally formed on their exposed surfaces; a second metal plating layer 52 covering the second inner plated seed layer 42 and the second outer plated seed layer 32 is integrally formed on their exposed surfaces; and a third metal plating layer 53 is plated on the conductive structure 70' on the hole wall of the through hole 60'. The first metal plating layer 51, the second metal plating layer 52, and the third metal plating layer 53 are integral structures.

[0102] In this embodiment, the blind via process can be replaced with a through-hole process, combined with the traditional black hole / shadow process, and then etched under flash etching to etch the first and second metal layers not covered by the first and second outer plating seed layers. No additional masks are required, and the formed first and second inner plating seed layers still have a metal bonding interface with the metal plating layer, serving as anchor points for the metal plating layer. Furthermore, since this embodiment uses a flash etching process, the first and second metal layers should be selected from the aforementioned ultra-thin metal foil layer range.

[0103] The conductive structure in the embodiments comprises one or more of conductive carbon black and conductive graphene. It can be formed by one or more conductive slurries selected from conductive carbon black (i.e., black hole process) and conductive graphene (i.e., black shadow process).

[0104] Another objective of this invention is to provide a circuit board that can be obtained by any of the manufacturing methods described above.

[0105] This utility model discloses a circuit board, specifically, as shown in the embodiment of the present invention. Figure 8 As shown, Figure 8 This is an example of the structure of a circuit board in this embodiment of the present invention; the circuit board includes: a substrate 10, an inner plating seed layer 40 attached to the substrate 10, and an outer plating seed layer 30 attached to the inner plating seed layer 40; the inner plating seed layer 40 and the outer plating seed layer 30 are stacked and have the same pattern; and a metal plating layer 50 covering the inner plating seed layer 40 and the outer plating seed layer 30. The metal plating layer 50 and the inner plating seed layer 40 have a metal bonding interface.

[0106] In some embodiments, the inner plating seed layer 40 may include: a first inner plating seed layer 41 attached to one side of the substrate 10, and a second inner plating seed layer 42 attached to the other side of the substrate 10; the outer plating seed layer 30 may include: a first outer plating seed layer 31 attached to the first inner plating seed layer 41, and a second outer plating seed layer 32 attached to the second inner plating seed layer 42; wherein the first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern; the metal plating layer includes: a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, and a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32.

[0107] In some embodiments, the circuit board may further include a conductive post 70 that penetrates the substrate 10 and connects the first inner plated seed layer 41 and the second inner plated seed layer 42.

[0108] This utility model embodiment also discloses a circuit board, specifically, as follows: Figure 9 As shown, Figure 9 This is a second example of the structure of the circuit board in this utility model embodiment; the circuit board includes: a substrate 10, a first inner plating seed layer 41 attached to one side of the substrate 10, and a second inner plating seed layer 42 attached to the other side of the substrate 10; a first outer plating seed layer 31 attached to the first inner plating seed layer 41, and a second outer plating seed layer 32 attached to the second inner plating seed layer 42; wherein the first inner plating seed layer 41 and the first outer plating seed layer 31 are stacked and have the same pattern, and the second inner plating seed layer 42 and the second outer plating seed layer 32 are stacked and have the same pattern; penetrating the substrate 10, the first inner plating seed layer 41, the second inner plating seed layer 42, and the first outer plating seed layer 32... The through-hole 60' of layer 31 and the second outer plating seed layer 32 has at least a conductive structure 70' formed on the hole wall of the through-hole 60' to achieve conductive interconnection between the first inner plating seed layer 41 and the second inner plating seed layer 42; the metal plating layer includes: a first metal plating layer 51 covering the first inner plating seed layer 41 and the first outer plating seed layer 31, a second metal plating layer 52 covering the second inner plating seed layer 42 and the second outer plating seed layer 32, and a third metal plating layer 53 formed on the conductive structure 70' on the hole wall of the through-hole 60'; wherein the first metal plating layer 51, the second metal plating layer 52 and the third metal plating layer 53 are an integral structure (i.e., a complete metal plating layer). A metal bonding interface is formed between the metal plating layer and the inner plating seed layer.

[0109] In some embodiments, the conductive structure may also cover the surfaces of the first outer seed layer and the second outer seed layer.

[0110] The material selection and related dimensional parameters of the circuit board in this embodiment can be referred to the embodiments in the manufacturing method of this utility model, and will not be repeated here.

[0111] In this embodiment of the invention, "the inner and outer seed layers have consistent patterns" mainly refers to the fact that the graphic outlines of the inner and outer seed layers are basically consistent. This may be affected by the process type and process precision (and side etching). For example, when the outer seed layer is used as a mask for the metal layer in a flash etching process, excluding the influence of process precision (and side etching), the patterns of the inner and outer seed layers can be considered completely consistent. However, when a conventional etch protective layer is formed on the outer seed layer as a mask for the metal layer in a conventional etching process, excluding the influence of process precision (and side etching) and assuming the etch protective layer completely covers the sidewalls of the outer seed layer, the inner seed layer is slightly larger than the pattern of the outer seed layer due to the influence of the thickness of the etch protective layer, and the thickness of the etch protective layer is usually extremely thin and its influence can be ignored. In some embodiments, for the above situation, the range of the outline of the outer seed layer plus the thickness of the etch protective layer can be considered consistent with the pattern of the inner seed layer.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A circuit board, characterized in that, include: A substrate, an inner plating seed layer attached to the substrate, and an outer plating seed layer attached to the inner plating seed layer; the inner plating seed layer and the outer plating seed layer are stacked and have the same pattern; and a metal plating layer covering the inner plating seed layer and the outer plating seed layer.

2. The circuit board according to claim 1, characterized in that, The inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate. The outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; Wherein, the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern. A conductive post that penetrates the substrate and connects the first inner plated seed layer and the second inner plated seed layer; The metal coating includes: a first metal coating covering the first inner plating seed layer and the first outer plating seed layer, and a second metal coating covering the second inner plating seed layer and the second outer plating seed layer.

3. The circuit board according to claim 1, characterized in that, The inner plating seed layer includes: a first inner plating seed layer attached to one side of the substrate, and a second inner plating seed layer attached to the other side of the substrate. The outer plating seed layer includes: a first outer plating seed layer attached to the first inner plating seed layer, and a second outer plating seed layer attached to the second inner plating seed layer; Wherein, the first inner plating seed layer and the first outer plating seed layer are stacked and have the same pattern, and the second inner plating seed layer and the second outer plating seed layer are stacked and have the same pattern. A through-hole is formed through the substrate, the first inner plating seed layer, the second inner plating seed layer, the first outer plating seed layer and the second outer plating seed layer, to form at least a conductive structure on the hole wall of the through-hole to realize the conductive interconnection between the first inner plating seed layer and the second inner plating seed layer. The metal coating includes: a first metal coating covering the first inner plating seed layer and the first outer plating seed layer, and a metal coating covering the second inner plating seed layer and the second outer plating seed layer. A second metal plating layer, and a third metal plating layer formed on the conductive structure on the wall of the through hole; wherein... The first metal coating, the second metal coating, and the third metal coating are an integral structure.

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