Decoupling circuit applied to MOSFET avalanche test

Abstract

The utility model discloses a decoupling circuit applied to an MOSFET avalanche test, relates to the technical field of avalanche tests, and solves the technical problem that a test result has a large error during the avalanche test. The circuit comprises a driving unit and a testing unit, the testing unit comprises an MOS transistor Q1, an MOS transistor Q2, an inductor L1 and a diode D1 which are connected in series, the MOS transistor Q1 is connected with a power supply VCC, the MOS transistor Q2 is a tested MOS transistor for avalanche testing, and the MOS transistor Q2, the inductor L1 and the diode D1 form a loop; the driving unit controls grid level signals of the MOS tube Q1 and the MOS tube Q2 through PWM signals, so that the MOS tube Q1 and the MOS tube Q2 are turned on or off at the same time. According to the utility model, after the MOS tube Q1 is turned off, the influence of VCC on the test of the MOS tube Q2 is directly isolated, the influence of power supply energy is well eliminated, and the avalanche test precision is improved by the decoupling circuit.

Description

TECHNICAL FIELD

[0001] The utility model relates to avalanche test technical field especially, relates to a decoupling circuit for MOSFET avalanche test. BACKGROUND

[0002] Avalanche test is an important means for evaluating the performance and reliability of power MOSFET under non-clamping inductive switching condition. A pulse signal is given to power MOSFET, when the device is turned on, the inductor is charged, when the device is turned off, due to the influence of stray inductance, the current does not disappear immediately, but continues to flow, the maximum value of the device that can withstand the current provided by the inductor without damage is the avalanche resistance. But because the current continues to flow after turning off, the large power supply on the inductor and DS is not powered off, so part of the energy provided by the large power supply will also pass through the MOSFET, and these energies are not avalanche energies.

[0003] The prior art has two parts of energy impacting MOSFET during avalanche test: one is the energy from the inductor, which accounts for a large proportion; the other is the energy from the power supply, which accounts for a small proportion, but this part of energy has a great influence on the overall test accuracy, which will cause the judgment error of the device's bearing capacity when designing the circuit, and has an adverse effect on the overall operation of the circuit.

[0004] In the process of realizing the utility model, the applicant finds that there are at least the following problems in the prior art:

[0005] When the prior art performs power MOSFET avalanche test, part of the impact energy comes from the inductive energy and part of the impact energy comes from the power supply energy, resulting in a large error in the final test result. UTILITY MODEL CONTENTS

[0006] The utility model aims at providing a decoupling circuit for MOSFET avalanche test to solve the technical problem that part of the impact energy comes from the inductive energy and part of the impact energy comes from the power supply energy when the prior art performs power MOSFET avalanche test, resulting in a large error in the final test result. The preferred technical solutions in many technical solutions provided by the utility model can produce many technical effects, which are described in detail below.

[0007] To achieve the above-mentioned purpose, the utility model provides the following technical solutions:

[0008] The utility model provides a kind of decoupling circuit applied to MOSFET avalanche test, including drive unit, test unit, the test unit includes mutually series-connected MOS Q1, MOS Q2 inductance L1 and diode D1, the MOS Q1 connects power supply VCC, the MOS Q2 is the MOS to be measured for carrying out avalanche test, MOS Q2 inductance L1 and diode D1 form loop;The drive unit controls the gate level signal of the MOS Q1, MOS Q2 by PWM signal, so that the MOS Q1, MOS Q2 is simultaneously turned on or turned off.

[0009] Preferably, the source of the MOS Q2 is grounded and connected to the anode of the diode D1, and the drain of the MOS Q2 is connected to one end of the inductance L1; the source of the MOS Q1 is connected to the other end of the inductance L1 and the cathode of the diode D1, and the drain of the MOS Q1 is connected to the power supply VCC.

[0010] Preferably, the test unit further includes capacitors C1, C2 and C3, which are connected in parallel to each other, and the first plates of the capacitors C1, C2 and C3 are connected to the power supply VCC, and the second plates are grounded.

[0011] Preferably, the MOS Q1 and Q2 are NMOS, the diode D1 is a freewheeling diode, and the inductance L1 is an energy storage inductor.

[0012] Preferably, the drive unit includes drive chips U1 and U2, a transistor Q3, a diode D2 and a radio frequency coaxial connector; the IN+ pin of the drive chips U1 and U2 is connected to the PWM signal, the OUT-SRC pin and OUT-SNK pin of the drive chip U1 are connected to the diode D2 and the transistor Q3; the base of the transistor Q3 is connected to the OUT-SRC pin and OUT-SNK pin of the drive chip U1 and the anode of the diode D2, the collector of the transistor Q3 is grounded, and the emitter of the transistor Q3 is connected to the cathode of the diode D2 and the gate of the MOS Q2; the radio frequency coaxial connector is connected to a signal generator for generating the PWM signal of the drive chips U1 and U2.

[0013] Preferably, the decoupling circuit further includes an isolation unit connected to the drive unit and the test unit, and the isolation unit includes an isolation power supply chip U3, the -VOUT pin and +VOUT pin of the isolation power supply chip U3 are connected to the drive unit, and the COM pin of the isolation power supply chip U3 is connected to the cathode of the inductance L1 and diode D1 of the test unit, so that the MOS Q1 is stably turned on or turned off.

[0014] Preferably, the driving unit further comprises a triode Q4, a triode Q5, the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 are connected with the triode Q4 and the triode Q5; the base of the triode Q4 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U2, the collector of the triode Q4 is connected with the-VOUT pin of the isolation power supply chip U3, the emitter of the triode Q4 is connected with the emitter of the triode Q5 and the gate of the MOS tube Q1; the base of the triode Q5 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U1, the collector of the triode Q5 is connected with the+VOUT pin of the isolation power supply chip U3, and the emitter of the triode Q5 is connected with the emitter of the triode Q4 and the gate of the MOS tube Q1.

[0015] Preferably, the model of the driving chip U1 and the driving chip U2 is 1EDN7511B, the model of the isolation power supply chip U3 is QA04, the triode Q3 and the triode Q4 are PNP type triodes, the triode Q5 is an NPN type triode, and the diode D2 is a fast recovery diode.

[0016] Preferably, the driving unit further comprises a capacitor C4, the first plate of the capacitor C4 is connected with the VDD pin of the driving chip U1 and the driving chip U2; and the second plate of the capacitor C4 is connected with the IN- pin and the GND pin of the driving chip U1 and the driving chip U2 and grounded.

[0017] Preferably, the driving unit comprises a driving chip U2, a triode Q6 and a diode D3; the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 are connected with the diode D3 and the triode Q6 respectively; the base of the triode Q6 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 and the anode of the diode D3, the collector of the triode Q6 is grounded, and the emitter of the triode Q6 is connected with the cathode of the diode D3 and the gate of the MOS tube Q1.

[0018] The above technical solutions of the present application have the following advantages or beneficial effects:

[0019] The utility model discloses, MOS tube Q1 is closed, directly isolated VCC is affected to MOS tube Q2 test, the energy that MOS tube Q2 suffers the impact is only provided by inductance L1, thereby very good elimination power energy's influence, improved MOS tube avalanche test precision. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the technical scheme of the embodiments of the utility model clearer, the following will briefly introduce the drawings needed in the embodiment description, obviously, the drawings in the following description are only some embodiments of the utility model, for the ordinary skilled in the art, under the premise of not creating the creative labor, can also obtain other drawings according to these drawings, and in the drawings,

[0021] Figure 1 It is a decoupling circuit for MOSFET avalanche test of the utility model embodiment one;

[0022] Figure 2 It is a decoupling circuit for MOSFET avalanche test of the utility model embodiment two. DETAILED DESCRIPTION

[0023] In order to make the technical scheme of the embodiments of the utility model clearer, the following will briefly introduce the drawings needed in the embodiment description, obviously, the drawings in the following description are only some embodiments of the utility model, for the ordinary skilled in the art, under the premise of not creating the creative labor, can also obtain other drawings according to these drawings, and in the drawings,

[0024] In the description of the utility model, need understanding is, the term "center", "longitudinal", "lateral" etc. Indicate is based on the orientation or positional relationship shown in the drawing, is only for the convenience of describing the utility model and simplifying the description, and is not indicating or implying that the indicated element must have a specific orientation, structure and operation. The term "first", "second" etc. Is only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The term "a plurality of" means two or more. The term "connected", "connected" should be broadly understood, for example, it can be fixed connection, detachable connection, integral connection, mechanical connection, electrical connection, communication connection, direct connection, indirect connection through intermediate medium, it can be the internal communication of two elements or the interaction relationship of two elements. The term "and / or" includes any and all combinations of one or more related listed items. For ordinary skilled in the art, the specific meaning of the above terms in the utility model can be understood according to the specific circumstances.

[0025] In order to illustrate the technical scheme of the utility model, the following specific embodiments are described, only the part related to the embodiment of the utility model is shown.

[0026] Embodiment one:

[0027] As Figure 1The utility model provides a kind of decoupling circuit applied to MOSFET avalanche test, including drive unit, test unit, test unit includes mutually series-connected MOS Q1, MOS Q2 inductance L1 and diode D1, MOS Q1 connects power supply VCC, MOS Q2 is the MOS of being measured for carrying out avalanche test, so that MOS Q2 is not directly connected with power supply VCC, but is separated by MOS Q1.MOS Q2 inductance L1 and diode D1 form loop, form loop after energy release of inductance L to MOS Q2 is facilitated.MOS Q1, MOS Q2 gate level signal of drive unit by PWM signal control, i.e.PWM signal realizes the conduction or cut-off of MOS Q1, MOS Q2 by the switching of high-low level, and makes MOS Q1, MOS Q2 simultaneously open or shut down, and simultaneously open or shut down is facilitated to test.MOS Q1 cut-off, directly isolates the influence of VCC on MOS Q2 test, after two MOS simultaneously cut off, MOS Q1 disconnects power supply and the MOS of being measured Q2 connection, the energy that MOS Q2 suffers from impact is only provided by inductance L1, so that the influence of power supply energy is well eliminated.After MOS Q1, MOS Q2 in test unit are turned on, VCC charges inductance L1, after MOS Q1, MOS Q2 cut off, energy impact Q2 is continued to release by the characteristic of inductance L at this time, and current passes through MOS Q2 and diode D1.The circuit of this embodiment improves the switching speed of MOS, reduces the influence on test result due to the excessively long open and shut down time, improves MOS avalanche test precision, facilitates accurate judgment on the bearing capacity of MOS when designing circuit, and effectively ensures the overall stable operation of circuit.

[0028] As optional implementation, the source of MOS Q2 is connected to ground and the anode of diode D1, and the drain of MOS Q2 is connected to one end of inductance L1; the source of MOS Q1 is connected to the other end of inductance L1 and the cathode of diode D1, and the drain of MOS Q1 is connected to power supply VCC. Thus, after MOS Q1 is cut off, the MOS Q2 being measured will not be affected by power supply VCC, and MOS Q1 and MOS Q2 are mutually isolated.

[0029] As optional implementation, the test unit further includes capacitors C1, C2 and C3, which are connected in parallel to each other, the first plates of capacitors C1, C2 and C3 are connected to power supply VCC, and the second plates are connected to ground. Capacitors C1, C2 and C3 are connected in parallel to each other to achieve the purpose of energy storage and filtering, to make the voltage of power supply VCC stable, and to make the avalanche test result of MOS Q2 more accurate.

[0030] As an optional implementation, the MOS tube Q1 and the MOS tube Q2 are NMOS tubes, the diode D1 is a freewheeling diode, and the inductor L1 is an energy storage inductor. The energy storage inductor facilitates avalanche testing. When the freewheeling diode D1 is used in cooperation with the energy storage inductor, if the current of the inductor load suddenly changes or decreases, a sudden voltage will be generated across the inductor, which may damage other components. When the freewheeling diode is used, the current can change more gently, and the occurrence of a sudden voltage can be avoided. Thus, the MOS tube is less disturbed during avalanche testing, and the test result is more accurate.

[0031] As an optional implementation, the driving unit includes a driving chip U1, a driving chip U2, a transistor Q3, a diode D2, and a radio frequency coaxial connector. The IN+ pin of the driving chip U1 and the IN+ pin of the driving chip U2 are connected to a PWM signal. The OUT-SRC pin and the OUT-SNK pin of the driving chip U1 are connected to the diode D2 and the transistor Q. The base of the transistor Q3 is connected to the OUT-SRC pin, the OUT-SNK pin of the driving chip U1, and the anode of the diode D2. The collector of the transistor Q3 is grounded. The emitter of the transistor Q3 is connected to the cathode of the diode D2 and the gate of the MOS tube Q2. The radio frequency coaxial connector is connected to a signal generator, which is used to generate the PWM signal of the driving chip U1 and the driving chip U2. Specifically, the signal generator outputs a PWM signal through the pin 1 of the radio frequency coaxial connector. The pin 2, the pin 3, and the pin 4 of the radio frequency coaxial connector are all grounded.

[0032] As an optional implementation, the decoupling circuit further includes an isolation unit connected to the driving unit and the testing unit. The isolation unit includes an isolation power supply chip U3. The -VOUT pin and the +VOUT pin of the isolation power supply chip U3 are connected to the driving unit. The COM pin of the isolation power supply chip U3 is connected to the inductor L1 of the testing unit and the cathode of the diode D1. Thus, the COM pin is also connected to the source of the MOS tube Q1, so that the MOS tube Q1 can be stably turned on or turned off. The +VIN pin of the isolation power supply chip U3 is connected to a +10V power supply, and the GND pin is grounded. A capacitor C5 is further connected between the +VIN pin and the GND pin, which is used to filter a sharp voltage. The addition of the isolation unit makes the source of the MOS tube Q1 connected to the COM pin at 0 potential (0 potential does not mean grounded), so that the Vgs of the MOS tube Q1 can be stably turned on or turned off. At the same time, the pulse drain current IDM of the MOS tube Q1 increases with the increase of Vgs, which indicates that the upper limit of the pulse drain current IDM of the MOS tube Q1 with Vgs=15V is higher than the upper limit of the pulse drain current IDM of the MOS tube Q2 with Vgs=10V. Thus, the turning on or turning off of the MOS tube Q1 will not affect the avalanche testing of the MOS tube Q2.

[0033] As an optional embodiment, the driving unit further comprises a transistor Q4, a transistor Q5, an OUT-SRC pin and an OUT-SNK pin of the driving chip U2 connected to the transistor Q4 and the transistor Q5. Specifically, a base of the transistor Q4 is connected to the OUT-SRC pin and the OUT-SNK pin of the driving chip U2, a collector of the transistor Q4 is connected to a -VOUT pin of the isolation power supply chip U3, and an emitter of the transistor Q4 is connected to an emitter of the transistor Q5 and a gate of the MOS transistor Q1. A base of the transistor Q5 is connected to the OUT-SRC pin and the OUT-SNK pin of the driving chip U1, a collector of the transistor Q5 is connected to a +VOUT pin of the isolation power supply chip U3, and an emitter of the transistor Q5 is connected to the emitter of the transistor Q4 and the gate of the MOS transistor Q1. When the IN+ pin of the driving chip U2 receives a high-level signal, the OUT-SRC pin outputs a 10V voltage signal, the base of the transistor Q4 is at a high level, the collector and the emitter are in an off state, and the signal is transmitted to the gate of the transistor Q3; when the IN+ pin of the driving chip U2 receives a low-level signal, the OUT-SNK pin outputs a low level, the base of the transistor Q4 is at a low level, the collector and the emitter are turned on, the gate of the MOS transistor Q1 is grounded and rapidly pulled down to a low potential, thereby realizing the on-off control of the MOS transistor Q1. The working principle of the driving chip U1 for controlling the MOS transistor Q2 is similar to the above.

[0034] As an optional embodiment, the driving chip U2 is further connected to a resistor Rg3 and a resistor Rg4, the resistor Rg3 is connected to the OUT-SRC pin of the driving chip U2, and the resistor Rg4 is connected to the OUT-SNK pin of the driving chip U2; the driving chip U2 is further connected to a resistor Rg1 and a resistor Rg2, the resistor Rg1 is connected to the OUT-SRC pin of the driving chip U1, and the resistor Rg2 is connected to the OUT-SNK pin of the driving chip U1. The resistors Rg1, Rg2, Rg3 and Rg4 achieve the purpose of current limiting, and ensure the normal and stable work of the diode D2, the transistor Q3 and the transistor Q4.

[0035] As an optional implementation, the model of the driving chip U1 and the driving chip U2 is both 1EDN7511B, which has fast connection efficiency and high propagation delay accuracy, thereby facilitating the avalanche test of the MOS tube. The model of the isolation power supply chip U3 is QA04, which is a DC-DC module power supply specially designed for IGBT drivers. The internal asymmetric voltage output form is adopted to minimize the driving loss of the IGBT, and the output short-circuit protection and self-recovery capability are provided, thereby facilitating the avalanche test. The triode Q3 and the triode Q4 are both PNP type triodes, the triode Q5 is an NPN type triode, and the diode D2 is a fast recovery diode. The fast recovery diode has the advantages of good switching characteristics and short reverse recovery time, thereby facilitating the fast conduction and cutoff of the triode Q1 and the triode Q2, and achieving the purpose of fast test.

[0036] As an optional implementation, the driving unit further includes a capacitor C4, a first plate of the capacitor C4 is connected with a VDD pin of the driving chip U1 and the driving chip U2, and the VDD pin is connected with a +10V working voltage; a second plate of the capacitor C4 is connected with an IN- pin and a GND pin of the driving chip U1 and the driving chip U2 and grounded, that is, the IN- pin and the GND pin of the driving chip U1 and the driving chip U2 are grounded together. The capacitor C4 filters the power supply, so that the working voltage of the driving chip U1 and the driving chip U2 is more stable.

[0037] The test process of the embodiment is as follows: ① provide 10V power supply for the driving unit, so that the driving chip U1 and the driving chip U2 can work normally, and then provide VCC large power supply; ② RF1 outputs a pulse square wave; ③ the IN+ of the driving chip U2 receives a high level signal, the OUT-SRC outputs a 10V voltage signal, the B of the transistor Q4 and the transistor Q5 are high level, the CE is in the off state, and the signal is transmitted to the gate of the MOS tube Q1; ④ the IN+ of the driving chip U2 receives a low level signal, the OUT-SNK outputs a low level, the B of the transistor Q4 and the transistor Q5 are low level, the CE is turned on, and the signal is transmitted to the gate of the MOS tube Q1; ⑤ the driving circuit corresponding to the driving chip U1 is similar to the above working logic, when the IN+ of the driving chip U1 receives a high level signal, the OUT-SRC outputs a 10V voltage signal, the diode D2 is in the positive bias conduction state, the B of the transistor Q3 is high level, the CE is in the off state, and the diode D2 transmits the signal to the gate of the MOS tube Q2; when the IN+ of the driving chip U1 receives a low level signal, the OUT-SNK outputs a low level, since the anode of the diode D2 is low level and the cathode is high level, it is in the reverse bias cutoff state and does not conduct, the B of the transistor Q2 is low level, the CE is turned on, and the gate of the transistor Q2 is grounded and the potential is rapidly lowered; and the MOS tube Q1 and the MOS tube Q2 are turned on or turned off at the same time; ⑥ in the test unit, the gate of the MOS tube Q1 and the MOS tube Q2 is high level, the VCC charges the inductor L1, the gate of the MOS tube Q1 and the MOS tube Q2 is low level, at this time, due to the characteristics of the inductor, the energy will continue to be released to impact the MOS tube Q2, that is, the MOS to be tested, and the current passes through the MOS tube Q2 and the diode D1.

[0038] Example two

[0039] The difference between the embodiment and the embodiment one is that the isolation unit in the embodiment one is not arranged, and the external connection relationship of the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 and the external connection relationship of the test unit are changed. Specifically, the driving unit comprises the driving chip U2, a triode Q6 and a diode D3, the triode Q6 is a PNP type triode, and the diode D3 is a fast recovery diode. The OUT-SRC pin and the OUT-SNK pin of the driving chip U2 are connected with the diode D3 and the triode Q6 respectively. The base of the triode Q6 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 and the anode of the diode D3, the collector of the triode Q6 is grounded, the emitter of the triode Q6 is connected with the cathode of the diode D3 and the gate of the MOS Q1, and the inductor L1 and the diode D1 in the test unit are no longer directly connected with the external unit. When the IN+ pin of the driving chip U2 receives a high level signal, the OUT-SRC pin outputs a +10V voltage signal, the diode D3 is in a positive bias conduction state, the base of the triode Q6 is in a high level, the collector and the emitter are in an off state, and the diode D3 transmits the signal to the gate of the MOS Q3; when the IN+ pin of the driving chip U2 receives a low level signal, the OUT-SNK pin outputs a low level, the anode of the diode D3 is in a low level, the cathode is in a high level, the diode Q6 is in a reverse bias cut-off state and is not conductive, the base of the diode Q6 is in a low level, the collector and the emitter are conductive, the gate of the MOS Q1 is grounded and rapidly pulled down to a low potential, and the conduction and cut-off control of the MOS Q1 is realized.

[0040] The embodiment is only a specific example, and does not indicate that the utility model is in this way.

[0041] The above is only a preferred embodiment of the utility model, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and range of the utility model. In addition, the features and embodiments can be modified to adapt to specific conditions and materials under the guidance of the utility model without departing from the spirit and range of the utility model. Therefore, the utility model is not limited by the specific embodiments disclosed here, and all embodiments falling within the scope of the claims of the present application belong to the protection range of the utility model.

Claims

1. A decoupling circuit for MOSFET avalanche testing, comprising: The test unit comprises MOS tube Q1, MOS tube Q2, inductor L1 and diode D1 connected in series, the MOS tube Q1 is connected with power supply VCC, the MOS tube Q2 is the MOS tube to be tested for avalanche test, the MOS tube Q2, inductor L1 and diode D1 form a loop; the driving unit controls the gate level signal of the MOS tube Q1 and MOS tube Q2 through PWM signal, so that the MOS tube Q1 and MOS tube Q2 are turned on or turned off at the same time.

2. The decoupling circuit for MOSFET avalanche testing of claim 1, wherein, The source of the MOS tube Q2 is connected with the anode of the diode D1, and the drain of the MOS tube Q2 is connected with one end of the inductor L1; the source of the MOS tube Q1 is connected with the other end of the inductor L1, and the cathode of the diode D1, and the drain of the MOS tube Q1 is connected with power supply VCC.

3. The decoupling circuit for MOSFET avalanche testing of claim 2, wherein, The test unit further comprises capacitor C1, capacitor C2 and capacitor C3 connected in parallel, the first plate of the capacitor C1, capacitor C2 and capacitor C3 is connected with power supply VCC, and the second plate is grounded.

4. The decoupling circuit for MOSFET avalanche testing of claim 2, wherein, The MOS tube Q1 and MOS tube Q2 are NMOS tubes, the diode D1 is a freewheeling diode, and the inductor L1 is an energy storage inductor.

5. The decoupling circuit for avalanche testing of MOSFET according to any one of claims 1-4, characterized in that, The driving unit comprises driving chip U1, driving chip U2, triode Q3, diode D2 and RF coaxial connector; the IN+ pin of the driving chip U1 and driving chip U2 is connected with PWM signal, the OUT-SRC pin and OUT-SNK pin of the driving chip U1 is connected with diode D2 and triode Q3; the base of the triode Q3 is connected with the OUT-SRC pin and OUT-SNK pin of the driving chip U1 and the anode of the diode D2, the collector of the triode Q3 is grounded, and the emitter of the triode Q3 is connected with the cathode of the diode D2 and the gate of the MOS tube Q2; the RF coaxial connector is connected with signal generator for generating PWM signal of the driving chip U1 and driving chip U2.

6. The decoupling circuit for MOSFET avalanche testing of claim 5, wherein, The decoupling circuit further comprises isolation unit connected with the driving unit and test unit, the isolation unit comprises isolation power supply chip U3, the -VOUT pin and +VOUT pin of the isolation power supply chip U3 is connected with the driving unit, and the COM pin of the isolation power supply chip U3 is connected with the cathode of the inductor L1 and diode D1 of the test unit, so that the MOS tube Q1 is turned on or turned off stably.

7. The decoupling circuit for MOSFET avalanche testing of claim 6, wherein, The driving unit further comprises a transistor Q4, a transistor Q5, OUT-SRC pin and OUT-SNK pin of the driving chip U2 connected with the transistor Q4 and the transistor Q5; the base of the transistor Q4 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U2, the collector of the transistor Q4 is connected with the-VOUT pin of the isolation power supply chip U3, and the emitter of the transistor Q4 is connected with the emitter of the transistor Q5 and the gate of the MOS tube Q1; the base of the transistor Q5 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U1, the collector of the transistor Q5 is connected with the+VOUT pin of the isolation power supply chip U3, and the emitter of the transistor Q5 is connected with the emitter of the transistor Q4 and the gate of the MOS tube Q1.

8. The decoupling circuit for MOSFET avalanche testing of claim 7, wherein, The model of the driving chip U1 and the driving chip U2 is 1EDN7511B, the model of the isolation power supply chip U3 is QA04, the transistor Q3 and the transistor Q4 are PNP type transistors, the transistor Q5 is an NPN type transistor, and the diode D2 is a fast recovery diode.

9. The decoupling circuit for MOSFET avalanche testing of claim 5, wherein, The driving unit further comprises a capacitor C4, the first plate of the capacitor C4 is connected with the VDD pin of the driving chip U1 and the driving chip U2; and the second plate of the capacitor C4 is connected with the IN- pin and the GND pin of the driving chip U1 and the driving chip U2 and grounded.

10. The decoupling circuit for MOSFET avalanche testing of claim 5, wherein, The driving unit further comprises a transistor Q6 and a diode D3; the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 are connected with the diode D3 and the transistor Q6 respectively; the base of the transistor Q6 is connected with the OUT-SRC pin and the OUT-SNK pin of the driving chip U2 and the anode of the diode D3, the collector of the transistor Q6 is grounded, and the emitter of the transistor Q6 is connected with the cathode of the diode D3 and the gate of the MOS tube Q1.

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