POE protection circuit

Abstract

The utility model provides a POE protection circuit which comprises an input end used for inputting an electric signal and an output end used for supplying power to a POE internal chip, a PMOS tube is connected between the input end and the output end, a source electrode and a drain electrode of the PMOS tube are connected with the input end and the output end respectively, a grid electrode of the PMOS tube is connected with a first grounding end, and a second grounding end is connected with a second grounding end. The first current-limiting voltage-stabilizing assembly, the first voltage-regulating assembly and the NMOS tube are connected in sequence, one end, far away from the first voltage-regulating assembly, of the first current-limiting voltage-stabilizing assembly is connected between the input end and a source electrode of the PMOS tube, a drain electrode of the NMOS tube is connected between a grid electrode of the PMOS tube and the first grounding end, a source electrode of the NMOS tube is connected with the first voltage-regulating assembly, and the first voltage-regulating assembly is connected with the NMOS tube. The grid electrode of the NMOS tube is connected between the first voltage regulating assembly and the first current-limiting voltage-stabilizing assembly. According to the invention, the possibility that the chip in the POE is damaged when the current is too large is reduced, and the normal use of the POE is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of POE circuit, and particularly relates to a POE protection circuit. BACKGROUND

[0002] POE (Power over Ethernet) is a technology for transmitting data and power through a network cable, which enables remote devices to obtain power supply without additional cables. The technology is widely used in network devices such as VoIP phones, wireless phones and monitoring cameras. With the further development of science and technology, POE is not only used in traditional network devices, but also plays an important role in the field of Internet of Things and smart buildings.

[0003] The current POE design in the electronic industry is basically dependent on the chip integrated in the POE. Many POEs do not have a circuit for protecting the chip inside. When the input current of the input end of the POE is too large, the chip inside the POE is often damaged. The POE chip is not easy to repair, and the chip price is high, the repair cost is also high, which greatly affects the use of the POE. CONTENT OF THE INVENTION

[0004] In order to overcome the defect that the chip inside the POE is damaged when the input current of the input end of the existing POE is too large, the present application provides a POE protection circuit.

[0005] The present application provides a POE protection circuit, which comprises an input end for inputting an electrical signal and an output end for supplying power to a chip inside the POE. The input end and the output end are connected by a PMOS tube. The source and the drain of the PMOS tube are connected to the input end and the output end respectively. The gate of the PMOS tube is connected to a first ground end. The POE protection circuit further comprises an overcurrent protection assembly. The overcurrent protection assembly comprises a first current-limiting voltage-stabilizing assembly, a first voltage-regulating assembly and an NMOS tube connected in sequence. The end of the first current-limiting voltage-stabilizing assembly away from the first voltage-regulating assembly is connected between the input end and the source of the PMOS tube. The drain of the NMOS tube is connected between the gate of the PMOS tube and the first ground end. The source of the NMOS tube is connected to the first voltage-regulating assembly. The gate of the NMOS tube is connected between the first voltage-regulating assembly and the first current-limiting voltage-stabilizing assembly. The first voltage-regulating assembly is used to adjust the conduction and disconnection of the NMOS tube. When the current of the input end is greater than a preset current value, the NMOS tube is disconnected.

[0006] In some embodiments, the first voltage regulating component comprises an NPN triode and a first regulating resistor for regulating a preset current value, two ends of the first regulating resistor are connected with an emitter and a base of the NPN triode respectively, a collector of the NPN triode is connected with the first current-limiting voltage stabilizing component, the base of the NPN triode is connected between the first regulating resistor and a source of the NMOS tube, and the emitter of the NPN triode is connected with a second grounding end.

[0007] In some embodiments, the POE protection circuit further comprises an under-voltage protection component, one end of the under-voltage protection component is communicated with the gate of the NMOS tube, and the other end is communicated with the source of the NMOS tube, and when the input voltage of the input end is less than the first preset voltage value, the NMOS tube is disconnected.

[0008] In some embodiments, the under-voltage protection component comprises a second regulating resistor and a first diode connected in parallel with each other, a positive electrode of the first diode is connected with the gate of the NMOS tube, and a negative electrode of the first diode is connected with the source of the NMOS tube.

[0009] In some embodiments, the under-voltage protection component further comprises a filter device connected in parallel with the second regulating resistor.

[0010] In some embodiments, the first current-limiting voltage stabilizing component comprises a first current-limiting resistor and a first voltage stabilizing diode connected in series with each other, a positive electrode of the first voltage stabilizing diode is connected with the first current-limiting resistor, and a negative electrode of the first voltage stabilizing diode is connected with the collector of the NPN triode.

[0011] In some embodiments, the POE protection circuit further comprises an over-voltage protection component, the over-voltage protection component comprises a second current-limiting voltage stabilizing component connected in parallel with the over-current protection circuit and a second voltage regulating component connected between the second current-limiting voltage stabilizing component and the PMOS tube, one end of the second current-limiting voltage stabilizing component is connected between the source of the PMOS tube and the input end, the other end is connected between the drain of the NMOS tube and the first grounding end, one end of the second voltage regulating component is connected between the gate of the PMOS tube and the first grounding end, and the other end is connected between the source of the PMOS tube and the input end, and when the input voltage of the input end is greater than the second preset voltage value, the PMOS tube is disconnected.

[0012] In some embodiments, the second current-limiting voltage stabilizing component comprises a second current-limiting resistor and a second voltage stabilizing diode connected in series with each other, a negative electrode of the second voltage stabilizing diode is connected between the drain of the NMOS tube and the first grounding end, a positive electrode of the second voltage stabilizing diode is connected with the second current-limiting resistor, and one end of the second current-limiting resistor away from the second voltage stabilizing diode is connected between the input end and the source of the PMOS tube.

[0013] In some embodiments, the second voltage regulating component includes a PNP triode, a base of the PNP triode is connected between the second current limiting resistor and the second voltage stabilizing diode, an emitter of the PNP triode is connected between the input end and the source of the PMOS, a collector of the PNP triode is connected between the gate of the PMOS and the first ground end, the second voltage regulating component further includes a first voltage regulating resistor connected between the second current limiting resistor and the base of the PNP triode, a second voltage regulating resistor connected between the collector of the PNP triode and the source of the PMOS, and a third voltage regulating resistor connected between the gate of the PMOS and the second voltage stabilizing diode, one end of the first voltage regulating resistor away from the PNP triode is connected between the second current limiting resistor and the second voltage stabilizing diode, one end of the second voltage regulating resistor away from the PNP triode is connected between the input end and the source of the PMOS, and the collector of the PNP triode is connected between the PMOS and the third voltage regulating resistor and between the second regulating resistor and the third regulating resistor.

[0014] In some embodiments, the first regulating resistor, the second regulating resistor and the third regulating resistor have the same resistance.

[0015] The technical scheme of the present application has at least the following advantages:

[0016] 1. The POE protection circuit of the present application, when the input current is less than or equal to the preset current value, adjusts the voltage between the gate and the source of the NMOS through the first voltage regulating component, so that the gate voltage of the NMOS is greater than the source voltage, the NMOS is turned on, at this time the PMOS is turned on, the input end of the POE can normally supply power to the internal chip of the POE, that is, the POE can normally supply power. When the input current is greater than the preset current value, the gate voltage of the NMOS is pulled down under the action of the first voltage regulating component, the NMOS is turned off, at this time the PMOS is turned off, the input end of the POE no longer supplies power to the internal chip, reducing the possibility of damage to the internal chip of the POE when the current is too large, and ensuring the normal use of the POE.

[0017] 2. Not only the excessive current can cause damage to the internal chip of the POE, but also the existing POE can damage the internal chip when the input end voltage is too small (under-voltage) or too large (over-voltage), affecting the use of the POE. The under-voltage protection component reduces the possibility of damage to the internal chip of the POE when the input end voltage is too small, and the over-voltage protection component reduces the possibility of damage to the internal chip of the POE when the input voltage is too high, thereby protecting the internal chip of the POE when over-voltage. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments or the prior art of the present application, the accompanying drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0019] Figure 1 A schematic diagram of a POE protection circuit provided for an exemplary embodiment of the present application.

[0020] Label explanation:

[0021] 1, input end; 2, output end; 3, filter device; 4, first ground terminal; 5, second ground terminal; Q1, PMOS tube; Q2, NMOS tube; Q3, NPN triode; Q4, PNP triode; R1, first adjusting resistor; R2, second adjusting resistor; R3, first current limiting resistor; R4, second current limiting resistor; R5, first voltage regulating resistor; R6, second voltage regulating resistor; R7, third voltage regulating resistor; D1, first diode; D2, first voltage stabilizing diode; D3, second voltage stabilizing diode. Specific embodiments

[0022] The technical solutions in the present application will be described clearly and completely in combination with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of protection of the present application.

[0023] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0024] In the description of the present application, it should be noted that unless specifically stated and limited otherwise, the terms "mounting", "connected", "connection" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can also be the internal communication of two elements, can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict between them.

[0026] Referring to Figure 1 The present application provides a POE protection circuit, which comprises an input end 1 for inputting an electrical signal and an output end 2 for supplying power to a POE internal chip, a PMOS tube Q1 is connected between the input end 1 and the output end 2, the source and the drain of the PMOS tube Q1 are connected to the input end 1 and the output end 2 in sequence, and the gate of the PMOS tube Q1 is connected with a first ground end 4. The POE protection circuit further comprises an overcurrent protection assembly, which comprises a first current-limiting voltage stabilizing assembly, a first voltage regulating assembly and an NMOS tube Q2 connected in sequence. The first current-limiting voltage stabilizing assembly is connected between the input end 1 and the source of the PMOS tube Q1 away from the first voltage regulating assembly. The drain of the NMOS tube Q2 is connected between the gate of the PMOS tube Q1 and the first ground end 4. The source of the NMOS tube Q2 is connected with the first voltage regulating assembly. The gate of the NMOS tube Q2 is connected between the first voltage regulating assembly and the first current-limiting voltage stabilizing assembly. The first voltage regulating assembly is used to adjust the conduction and disconnection of the NMOS tube Q2. When the current of the input end 1 is greater than a preset current value, the NMOS tube Q2 is disconnected.

[0027] The POE protection circuit described above, when the input current is less than or equal to the preset current value, the voltage at the gate and the source of the NMOS tube Q2 is adjusted by the first voltage regulating assembly, so that the gate voltage of the NMOS tube Q2 is greater than the source voltage, the NMOS tube Q2 is turned on, at this time the PMOS tube Q1 is turned on, the input end 1 of the POE can normally supply power to the internal chip of the POE, that is, the POE can normally supply power. When the input current is greater than the preset current value, the gate voltage of the NMOS tube Q2 is pulled down under the action of the first voltage regulating assembly, the NMOS tube Q2 is disconnected, at this time the PMOS tube Q1 is disconnected, the input end 1 of the POE no longer supplies power to the internal chip, reducing the possibility of damage to the internal chip of the POE when the current is too large, and ensuring the normal use of the POE.

[0028] In some embodiments, referring to Figure 1The first voltage regulating component includes an NPN transistor Q3 and a first regulating resistor R1 for regulating a preset current value. The first regulating resistor R1 is connected to the emitter and the base of the NPN transistor Q3 respectively. The collector of the NPN transistor Q3 is connected to the first current limiting and voltage stabilizing component. The base of the NPN transistor Q3 is connected between the first regulating resistor R1 and the source of the NMOS transistor Q2. The emitter of the NPN transistor Q3 is connected to the second ground terminal 5. When the input current of the input terminal 1 is less than or equal to the preset current value, the NPN transistor Q3 is turned off, and the NMOS transistor Q2 and the PMOS transistor Q1 are turned on. At this time, the POE is normally powered. When the input current of the input terminal 1 is greater than the preset current value, the base voltage of the NPN transistor Q3 is greater than the emitter voltage. At this time, the NPN transistor Q3 is turned on, and the emitter and the collector of the NPN transistor Q3 are connected to the ground, which lowers the gate voltage of the NMOS transistor Q2. The NMOS transistor Q2 is turned off, and the input terminal 1 of the POE no longer supplies power to the internal chip of the POE, which can prevent the internal chip of the POE from being damaged by excessive current. Specifically, by adjusting the resistance of the first regulating resistor R1, the size of the current threshold value, i.e., the size of the overcurrent, can be adjusted.

[0029] In some embodiments, with reference to Figure 1 The first current limiting and voltage stabilizing component includes a first current limiting resistor R3 and a first voltage stabilizing diode D2 connected in series. The positive electrode of the first voltage stabilizing diode D2 is connected to the first current limiting resistor R3, and the negative electrode of the first voltage stabilizing diode D2 is connected to the collector of the NPN transistor Q3. The first current limiting resistor R3 functions to limit current, which improves the stability of the protection circuit. The first voltage stabilizing diode D2 is used to determine the size of the input voltage. Specifically, the first voltage stabilizing diode D2 is a 30V voltage stabilizing diode, the resistance of the first current limiting resistor R3 is 10kΩ, and the resistance of the first regulating resistor R1 is 0.25Ω.

[0030] Not only excessive current can cause damage to the internal chip of the POE, but also the existing POE can be damaged when the voltage of the input terminal 1 is too small (under-voltage) or too large (over-voltage), which affects the use of the POE.

[0031] In some embodiments, with reference to Figure 1The protection circuit further comprises an under-voltage protection component, one end of the under-voltage protection component is communicated with the gate of the NMOS tube Q2, and the other end is communicated with the source of the NMOS tube Q2. When the input voltage of the input end 1 is less than the first preset voltage, the NMOS tube Q2 is disconnected. When the value of the input voltage is less than the conduction voltage of the first voltage stabilizing diode D2, the first voltage stabilizing diode D2 cannot be turned on, and the POE cannot be normally powered. When the input voltage is greater than the conduction value of the first voltage stabilizing diode D2 and less than the first preset voltage, the gate voltage of the NMOS tube Q2 is lower than the conduction voltage of the NMOS tube Q2, the NMOS tube Q2 is disconnected, and the POE cannot be normally powered, thereby reducing the possibility of damage of the internal chip of the POE when the voltage of the input end 1 is too low.

[0032] Further, referring to Figure 1 The under-voltage protection component comprises a second adjusting resistor R2 and a first diode D1 which are connected in parallel. The anode of the first diode D1 is connected with the gate of the NMOS tube Q2, and the cathode is connected with the source of the NMOS tube Q2. When the input voltage of the input end 1 is greater than the conduction voltage of the first voltage stabilizing diode D2 and less than the first preset voltage, the first voltage stabilizing diode D2 is turned on, and the voltage cannot break through the first diode D1 after being turned on. The gate voltage of the NMOS tube Q2 is lower than the conduction voltage of the NMOS tube Q2, the NMOS tube Q2 is disconnected, and the POE cannot supply power to the internal chip, thereby reducing the possibility of damage of the internal chip of the POE when the voltage of the input end 1 is too low. When the input voltage is greater than or equal to the first preset voltage, the first voltage stabilizing diode D2 is turned on, the NMOS tube Q2 is turned on, and the PMOS tube Q1 is turned on. The input end 1 of the POE can normally supply power to the internal chip, and the POE can normally supply power. When the input voltage is greater than or equal to the first preset voltage and the voltage after the first voltage stabilizing diode D2 is turned on can break through the first diode D1, the first diode D1 is turned on, the gate voltage of the NMOS tube Q2 reaches the conduction voltage of the NMOS tube Q2 and is stabilized at the conduction voltage of the first diode D1, and the NMOS tube Q2 and the PMOS tube Q1 are both turned on, so that the POE can stably supply power to the internal chip, thereby improving the stability of the POE power supply.

[0033] Specifically, taking the conduction voltage of the first diode D1 as 12V as an example, when the input voltage of the input end 1 is greater than 30V and lower than 33V, the first voltage stabilizing diode D2 is turned on, the voltage after being turned on cannot break through the first diode D1, the gate voltage of the NMOS tube Q2 is lower than 3V, the NMOS tube Q2 is turned off, and the POE cannot be normally powered. When the voltage of the input end 1 is greater than or equal to 33V and the input voltage is less than 12V, the gate voltage of the NMOS tube Q2 is greater than or equal to the conduction voltage of the NMOS tube Q2, the NMOS tube Q2 is turned on, and the POE can be normally powered. Further, when the voltage of the input end 1 is greater than or equal to 42V, the first voltage stabilizing diode D2 is turned on, the voltage after being turned on can make the gate voltage of the NMOS tube Q2 stable at 12V, so that the POE can stably supply power to the internal chip, and the stability of the POE power supply is improved. By adjusting the value of the conduction voltage of the first voltage stabilizing diode D2, the voltage undervoltage protection value of the undervoltage protection assembly can be changed.

[0034] In some embodiments, the undervoltage protection assembly further comprises a filtering device 3 connected in parallel with the second adjusting resistor R2. The filtering device 3 is a capacitor, which has the effect of delaying the opening of the NMOS tube Q2. When the protection circuit is powered on, the filtering device 3 will be charged first, making the gate voltage of the NMOS tube Q2 rise linearly, preventing the current from being too large at the moment of power-on and burning out other devices, and further improving the stability of the POE power supply.

[0035] In some embodiments, referring to Figure 1 , the POE protection circuit further comprises an overvoltage protection assembly, the overvoltage protection assembly comprises a second current-limiting voltage stabilizing assembly connected in parallel with the overcurrent protection circuit and a second voltage regulating assembly connected between the second current-limiting voltage stabilizing assembly and the PMOS tube Q1, one end of the second current-limiting voltage stabilizing assembly is connected between the source of the PMOS tube Q1 and the input end 1, and the other end is connected between the drain of the NMOS tube Q2 and the first ground end 4, one end of the second voltage regulating assembly is connected between the gate of the PMOS tube Q1 and the first ground end 4, and the other end is connected between the source of the PMOS tube Q1 and the input end 1, and when the input voltage of the input end 1 is greater than a second preset voltage, the PMOS tube Q1 is turned off.

[0036] When the input voltage of the input end 1 is greater than the second preset voltage, the PMOS tube Q1 is turned off, and the POE input end 1 cannot normally supply power to the POE internal chip, thereby reducing the possibility of damage to the POE internal chip when the input voltage is too high, and thereby protecting the POE internal chip when the voltage is too high.

[0037] In some embodiments, referring to Figure 1The second current-limiting voltage stabilizing component comprises a second current-limiting resistor R4 and a second voltage stabilizing diode D3 connected in series with each other, the negative electrode of the second voltage stabilizing diode D3 is connected between the drain of the NMOS tube Q2 and the first ground terminal 4, the positive electrode of the second voltage stabilizing diode D3 is connected with the second current-limiting resistor R4, and the end of the second current-limiting resistor R4 away from the second voltage stabilizing diode D3 is connected between the input terminal 1 and the source of the PMOS tube Q1. The second voltage regulating component comprises a PNP transistor Q4, the base of the PNP transistor Q4 is connected between the second current-limiting resistor R4 and the second voltage stabilizing diode D3, the emitter of the PNP transistor Q4 is connected between the input terminal 1 and the source of the PMOS tube Q1, the collector of the PNP transistor Q4 is connected between the gate of the PMOS tube Q1 and the first ground terminal 4, and the second voltage regulating component further comprises a first voltage regulating resistor R5 connected between the second current-limiting resistor R4 and the base of the PNP transistor Q4, a second voltage regulating resistor R6 connected between the collector of the PNP transistor Q4 and the source of the PMOS tube Q1, and a third voltage regulating resistor R7 connected between the gate of the PMOS tube Q1 and the second voltage stabilizing diode D3, the end of the first voltage regulating resistor R5 away from the PNP transistor Q4 is connected between the second current-limiting resistor R4 and the second voltage stabilizing diode D3, the end of the second voltage regulating resistor R6 away from the PNP transistor Q4 is connected between the input terminal 1 and the source of the PMOS tube Q1, and the collector of the PNP transistor Q4 is connected between the PMOS tube Q1 and the third voltage regulating resistor R7 and between the second regulating resistor R2 and the third regulating resistor R7 at the same time. The first regulating resistor R1, the second regulating resistor R2 and the third regulating resistor have the same resistance value.

[0038] Specifically, the on voltage of the second voltage stabilizing diode D3 is a voltage second preset value, when the input voltage is lower than the voltage second preset value, the second voltage stabilizing diode D3 cannot be turned on, at this time, the base voltage of the PNP transistor Q4 is equal to the emitter voltage, the PNP transistor Q4 is cut off, the source voltage of the PMOS tube Q1 is higher than the gate voltage, the PMOS tube Q1 is normally turned on, the input terminal 1 of the POE normally supplies power to the internal chip of the POE, and the POE normally supplies power. When the input voltage is greater than or equal to the voltage second preset value, the second voltage stabilizing diode D3 is turned on, the base voltage of the PNP transistor Q4 is less than the emitter voltage, the PNP transistor Q4 is turned on, at this time, the voltage of the second voltage regulating resistor R6 and the third voltage regulating resistor R7 is pulled up to the voltage value of the input terminal 1 by the PNP transistor Q4, the gate voltage of the PMOS tube Q1 is equal to the source voltage, the PMOS tube Q1 is disconnected, the input terminal 1 of the POE cannot normally supply power to the internal chip of the POE, and the possibility of damage to the internal chip of the POE when the input voltage is too high is reduced, thereby protecting the internal chip of the POE when the voltage is too high.

[0039] Specifically, the conduction voltage of the second voltage stabilizing diode D3 can be 58V, and the voltage overvoltage protection value of the overvoltage protection assembly can be adjusted by adjusting the conduction voltage value of the second voltage stabilizing diode D3.

[0040] Obviously, the above embodiments are merely exemplary and are not intended to limit the implementation. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the implementations are not required or possible to be exhausted. The obvious changes or variations derived therefrom are still within the protection scope of the present application.

Claims

1. A POE protection circuit, characterized by, The POE protection circuit comprises an input end for inputting an electric signal and an output end for supplying power to an internal chip of the POE, a PMOS tube is connected between the input end and the output end, the source and the drain of the PMOS tube are connected to the input end and the output end respectively, and the gate of the PMOS tube is connected to a first grounding end.

2. The POE protection circuit of claim 1, wherein, The first voltage regulating component comprises an NPN triode and a first adjusting resistor for adjusting the preset value of the current, the two ends of the first adjusting resistor are connected to the emitter and the base of the NPN triode respectively, the collector of the NPN triode is connected to the first current-limiting and voltage-stabilizing component, the base of the NPN triode is connected between the first adjusting resistor and the source of the NMOS tube, and the emitter of the NPN triode is connected to a second grounding end.

3. A POE protection circuit according to claim 2, wherein, The POE protection circuit further comprises an under-voltage protection component, one end of the under-voltage protection component is communicated with the gate of the NMOS tube, and the other end of the under-voltage protection component is communicated with the source of the NMOS tube, and the NMOS tube is turned off when the input voltage of the input end is less than a first preset value of voltage.

4. The POE protection circuit of claim 3, wherein, The under-voltage protection component comprises a second adjusting resistor and a first diode which are connected in parallel to each other, the anode of the first diode is connected to the gate of the NMOS tube, and the cathode of the first diode is connected to the source of the NMOS tube.

5. A POE protection circuit according to claim 4, wherein, The under-voltage protection component further comprises a filter device connected in parallel to the second adjusting resistor.

6. The POE protection circuit of claim 3, wherein, The first current-limiting and voltage-stabilizing component comprises a first current-limiting resistor and a first voltage stabilizing diode which are connected in series to each other, the anode of the first voltage stabilizing diode is connected to the first current-limiting resistor, and the cathode of the first voltage stabilizing diode is connected to the collector of the NPN triode.

7. A POE protection circuit according to claim 5, wherein, The POE protection circuit further comprises an over-voltage protection component, the over-voltage protection component comprises a second current-limiting and voltage-stabilizing component connected in parallel to the over-current protection circuit and a second voltage regulating component connected between the second current-limiting and voltage-stabilizing component and the PMOS tube, one end of the second current-limiting and voltage-stabilizing component is connected between the source of the PMOS tube and the input end, the other end of the second current-limiting and voltage-stabilizing component is connected between the drain of the NMOS tube and the first grounding end, one end of the second voltage regulating component is connected between the gate of the PMOS tube and the first grounding end, and the other end of the second voltage regulating component is connected between the source of the PMOS tube and the input end, and the PMOS tube is turned off when the input voltage of the input end is greater than a second preset value of voltage.

8. A POE protection circuit according to claim 7, wherein, The second current-limiting and voltage-stabilizing component comprises a second current-limiting resistor and a second voltage stabilizing diode which are connected in series to each other, the cathode of the second voltage stabilizing diode is connected between the drain of the NMOS tube and the first grounding end, the anode of the second voltage stabilizing diode is connected to the second current-limiting resistor, and one end of the second current-limiting resistor away from the second voltage stabilizing diode is connected between the input end and the source of the PMOS tube.

9. A POE protection circuit according to claim 8, wherein, The second voltage regulating component comprises a PNP triode, a base of the PNP triode is connected between the second current limiting resistor and the second voltage stabilizing diode, an emitter of the PNP triode is connected between the input end and a source of the PMOS, a collector of the PNP triode is connected between a gate of the PMOS and the first ground end, the second voltage regulating component further comprises a first voltage regulating resistor connected between the second current limiting resistor and the base of the PNP triode, a second voltage regulating resistor connected between the collector of the PNP triode and the source of the PMOS, and a third voltage regulating resistor connected between the gate of the PMOS and the second voltage stabilizing diode, one end of the first voltage regulating resistor away from the PNP triode is connected between the second current limiting resistor and the second voltage stabilizing diode, one end of the second voltage regulating resistor away from the PNP triode is connected between the input end and the source of the PMOS, and the collector of the PNP triode is connected between the PMOS and the third voltage regulating resistor and between the second regulating resistor and the third regulating resistor.

10. The POE protection circuit of claim 8, wherein, The first regulating resistor, the second regulating resistor and the third regulating resistor have the same resistance.

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