Circuit structure
By designing microstrip line circuits on the chip substrate, the problem of the inability to integrate attenuation filter circuits was solved, achieving miniaturization and high-efficiency EMC performance improvement, simplifying the process flow, and enhancing the chip's anti-interference capability.
Patent Information
- Application Number
- CN202520142976.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2035-01-21
AI Technical Summary
Existing attenuation filter circuits are large in size and cannot be integrated into the chip. Furthermore, the selection of discrete components requires knowledge of the frequency points where the chip's radiation exceeds the limit, which is quite troublesome.
Design a microstrip line circuit, integrated on or below a chip substrate, with its input connected to the core circuit and its output grounded to dissipate the energy radiated by the core circuit. The microstrip line includes resistors, inductors, and capacitors, and its process is compatible with semiconductor manufacturing, integrated on a packaging substrate.
The miniaturized filter circuit improves the chip's EMC performance, reduces space occupation, simplifies peripheral wiring, facilitates manufacturing processes, and enhances the chip's anti-interference capability.
Smart Images
Figure CN223885631U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and in particular to a circuit structure. BACKGROUND
[0002] With the application environment of electronic devices becoming more and more complex, electromagnetic interference on electronic devices is becoming more and more serious, and therefore the requirement for the anti-interference performance of chips is also becoming higher and higher. According to the standard of electromagnetic interference, the radiation performance of the chip needs to be strictly controlled. At present, the improvement of the chip-level radiation performance mainly uses discrete components such as inductors, capacitors, resistors, and magnetic beads to build an attenuation filter circuit to filter out the frequency points that exceed the standard. These attenuation filter circuits have relatively large sizes and cannot be integrated inside the chip. In addition, the selection of these discrete components needs to know the frequency points that exceed the standard of the chip, which is relatively troublesome. CONTENT OF THE UTILITY MODEL
[0003] The purpose of the present application is to provide a circuit structure to solve the problem of large size of the existing attenuation filter circuit and the problem of being unable to be integrated inside the chip.
[0004] In order to achieve the above purpose, the present application provides a circuit structure, characterized in that it comprises:
[0005] a chip substrate, the upper or lower side of the chip substrate having a core circuit; and
[0006] a microstrip line circuit formed on the chip substrate, the input end of the microstrip line circuit being connected to the core circuit, and the output end of the microstrip line circuit being grounded to consume the energy radiated by the core circuit.
[0007] Optionally, the microstrip line circuit comprises a plurality of microstrip lines connected to each other, and the microstrip lines comprise a resistive microstrip line, an inductive microstrip line, and a capacitive microstrip line.
[0008] Optionally, the chip substrate is a PCB packaging substrate, and the microstrip line circuit is an on-board circuit on the PCB packaging substrate.
[0009] Optionally, the core circuit has at least one circuit interface, and the input end of the microstrip line circuit is connected to the circuit interface.
[0010] Optionally, the circuit structure is a chip, the core circuit is formed on a die of the chip, and the chip substrate is a packaging substrate of the chip.
[0011] Optionally, the core circuit has at least one lead-out end, and the input end of the microstrip line circuit is connected to the lead-out end.
[0012] Optionally, the core circuit has at least one lead-out terminal and at least one switch, and the input terminal of the microstrip line circuit is connected to the lead-out terminal through the switch.
[0013] Optionally, the circuit structure is a packaged chip, and the packaged chip includes at least two dies and at least one packaging substrate, the core circuit is formed on each of the dies, and the chip substrate is at least one of the packaging substrates in the packaged chip.
[0014] Optionally, each of the dies has a ground lead-out terminal, and the input terminal and the output terminal of the microstrip line circuit are connected to the ground lead-out terminals of the two dies respectively.
[0015] Optionally, the die has at least one lead-out terminal, and the input terminal of the microstrip line circuit is connected to the lead-out terminal of the die.
[0016] Optionally, the die has at least one lead-out terminal and at least one switch, and the input terminal of the microstrip line circuit is connected to the lead-out terminal of the die through the corresponding switch.
[0017] Optionally, the microstrip line circuit is formed in a free area of the chip substrate, or the microstrip line circuit is integrated in a redistribution layer of the chip substrate.
[0018] The application provides a circuit structure including a chip substrate and a microstrip line circuit, the chip substrate has a core circuit thereon, the microstrip line circuit is formed above or below the chip substrate, the input terminal of the microstrip line circuit is connected to the core circuit, and the output terminal of the microstrip line circuit is connected to the ground to consume the energy radiated by the core circuit. The application designs the large-sized attenuation filter circuit into a small-sized microstrip line circuit, the microstrip line circuit can consume the energy radiated by the core circuit, reserves the radiation margin for the circuit structure, improves the EMC performance of the circuit structure, and integrates the microstrip line circuit on the packaging substrate of the chip or directly forms the microstrip line circuit on the PCB packaging substrate, saves the peripheral discrete components, reduces the space occupation, simplifies the peripheral wiring, and the microstrip line circuit can consume the predetermined radiation amount according to the standard requirement after the design of the microstrip line circuit, without real-time adjustment of the parameters, and the use is more convenient. The manufacturing process of the microstrip line circuit is compatible with the semiconductor manufacturing processes such as photolithography, plating and etching, and the production and processing of the microstrip line circuit can be performed synchronously during the production and processing of the chip substrate, the manufacturing and design processes are relatively simple, and the process implementation is relatively convenient. When the microstrip line circuit is integrated in the chip, the output terminal of the microstrip line circuit is connected to the ground of the chip, the integrity of the ground of the chip is good, which is beneficial to reduce the external interference and radiation loss, and the EMC performance of the chip can be improved. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 A schematic diagram of the circuit structure provided in the embodiments of this application;
[0020] Figure 2 A schematic diagram of an attenuation filter circuit built from discrete components is provided for an embodiment of this application;
[0021] Figure 3a for Figure 2 The design diagram of the microstrip line circuit corresponding to the attenuation filter circuit in the diagram;
[0022] Figure 3b According to Figure 3a The schematic diagram of the microstrip line circuit obtained from the design drawing of the microstrip line circuit in the diagram;
[0023] Figure 4 This is a schematic diagram of a microstrip line circuit integrated within a chip, as provided in an embodiment of this application.
[0024] Figure 5 This is a schematic diagram of a microstrip line circuit integrated within a system-on-a-chip, as provided in an embodiment of this application.
[0025] Figure 6 A cross-sectional schematic diagram of a system-on-a-chip provided for an embodiment of this application;
[0026] The attached figures are labeled as follows:
[0027] 100 - Chip substrate; 100a, 100b - Packaging substrate; 101 - Core circuit; 102 - Microstrip line circuit; TL1 - First microstrip line; TL2 - Second microstrip line; TL3 - Third microstrip line; TL4 - Fourth microstrip line; TL5 - Fifth microstrip line; RL - Resistor line; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; R4 - Fourth resistor; R5 - Fifth resistor; R6 - Sixth resistor; C1 - First capacitor; C2 - Second capacitor; C3 - Third capacitor; L1 - First inductor; L2 - Second inductor L2. Detailed Implementation
[0028] The specific embodiments of this application will now be described in more detail with reference to the accompanying drawings. The advantages and features of this application will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.
[0029] Figure 1 This is a schematic diagram of the circuit structure provided in this embodiment. Figure 1As shown, the circuit structure includes a chip substrate and a microstrip line circuit 102. The chip substrate has a core circuit 101. The microstrip line circuit 102 is formed above or below the chip substrate, and its input terminal is connected to the core circuit 101, while its output terminal is grounded, so as to dissipate the energy radiated by the core circuit 101. This application designs a large attenuation filter circuit as a small microstrip line circuit 102. The microstrip line circuit 102 can consume the energy radiated by the core circuit 101, reserving radiation margin for the circuit structure and improving the EMC performance of the circuit structure. At the same time, the microstrip line circuit 102 can be integrated on the chip packaging substrate or directly formed on the PCB packaging substrate, saving peripheral discrete components, reducing space occupation, and simplifying peripheral routing. After the microstrip line circuit 102 is designed, it can consume the predetermined amount of radiation according to standard requirements without the need for real-time parameter adjustment, making it more convenient to use. The manufacturing process of the microstrip line circuit 102 is compatible with semiconductor manufacturing processes such as photolithography, plating, and etching. The microstrip line circuit 102 can be manufactured and processed simultaneously during chip substrate production, making the manufacturing and design processes relatively simple and the process implementation relatively convenient. Furthermore, when the microstrip line circuit 102 is integrated into the chip, the output terminal of the microstrip line circuit 102 is connected to the chip's ground. Since the chip's ground integrity is good, it helps to reduce external interference and radiation loss, thereby improving the chip's EMC performance.
[0030] The microstrip line circuit 102 can be designed according to the following approach:
[0031] Assuming the power of excessively radiated signals needs to be reduced by 6dB below 1GHz, a design could be made as follows: Figure 2 The diagram shows an attenuation filter circuit built from discrete components. (Example:) Figure 2As shown, the attenuation filter circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inductor L1 and a second inductor L2. The first end of the first resistor R1 is connected to the first end of the second resistor R2, the second end of the second resistor R2 is connected to the first end of the third resistor R3, the first end of the first capacitor C1 and the first end of the first inductor L1, the second end of the first inductor L1 is connected to the first end of the second capacitor C2 and the first end of the second inductor L2, the second end of the second inductor L2 is connected to the first end of the third capacitor C3, the first end of the fourth resistor R4 and the first end of the fifth resistor R5, the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second ends of the first resistor R1, the third resistor R3, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth resistor R4 and the sixth resistor R6 are connected to each other. The resistance values of the first resistor R1, the third resistor R3 and the sixth resistor R6 are 292 ohm, the resistance values of the second resistor R2 and the fifth resistor R5 are 17 ohm, the capacitance values of the first capacitor C1, the second capacitor C2 and the third capacitor C3 are 4 pF, 7 pF and 4 pF respectively, and the inductance values of the first inductor L1 and the second inductor L2 are both 10 nH. Figure 2 The input impedance and the output impedance of the attenuation filter circuit in Figure 2 The attenuation filter circuit in Figure 2 The attenuation filter circuit in
[0032] According to Figure 2 The design diagram of the microstrip line circuit shown in Figure 3a According to the design diagram shown in Figure 3a The microstrip line circuit shown in Figure 3b The microstrip line circuit shown in Figure 3a and Figure 3bAs shown, assuming the thickness H of the dielectric plate (MSub) of the chip substrate is 5 mil and the dielectric constant is 4.2, the first capacitor C1 can be calculated to obtain the first capacitor microstrip line TL1, the width W of the first capacitor microstrip line TL1 is 40.118 μm, and the length L is 50.975 μm; the first inductor L1 can be calculated to obtain the first inductor microstrip line TL2, the width W of the first inductor microstrip line TL2 is 30.136 μm, and the length L is 96.172 μm; the second capacitor C2 can be calculated to obtain the second capacitor microstrip line TL3, the width W of the second capacitor microstrip line TL3 is 50.118 μm, and the length L is 100.523 μm; the second inductor L2 can be calculated to obtain the second inductor microstrip line TL4, the width W of the second inductor microstrip line TL4 is 30.136 μm, and the length L is 96.172 μm; the third capacitor C3 can be calculated to obtain the third capacitor microstrip line TL5, the width W of the third capacitor microstrip line TL5 is 40.118 μm, and the length L is 50.975 μm; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 can be calculated to obtain the resistor microstrip lines TLR1, TLR2, TLR3, TLR4, TLR5 and TLR6, respectively. In this way, the attenuation filter circuit can be converted into a microstrip line circuit.
[0033] It should be understood that the microstrip line circuit 102 in FIG. 3 is only an example. In practice, the microstrip line circuit 102 can include a plurality of microstrip lines connected to each other, wherein the microstrip lines can include resistor microstrip lines, inductor microstrip lines and capacitor microstrip lines, and all the microstrip lines between the input end and the output end of the microstrip line circuit 102 can collectively consume a predetermined amount of radiated energy.
[0034] Further, in some embodiments, the chip substrate can be a PCB packaging substrate, and the microstrip line circuit 102 can be an on-board circuit on the PCB packaging substrate. At this time, the microstrip line circuit 102 can be regarded as a two-port device reserved on the PCB packaging substrate, and the core circuit 101 can be composed of various components and / or chips soldered on the PCB packaging substrate. The core circuit 101 has circuit interfaces, and the input end of the microstrip line circuit 102 can be connected to any circuit interface, thereby consuming the part of the energy radiated by the core circuit 101 to the circuit interface and suppressing the radiated interference when the circuit interface works.
[0035] Optionally, the circuit interface can be a signal transmission interface, such as a USB interface, a UART interface, an SPI interface or an I2C interface, etc. Of course, the circuit interface can also be a power supply interface or a ground interface, etc., which is not limited in the present application.
[0036] In some embodiments, the microstrip line circuit 102 can be integrated into a single-die chip such as a CPU or MCU chip. Specifically, the circuit structure can be a chip, which has a die and a packaging substrate. The core circuit 101 is formed on the die, and the microstrip line circuit 102 can be formed on the chip's packaging substrate. In this case, the chip substrate is the chip's packaging substrate.
[0037] Furthermore, the core circuit 101 has at least one lead, each lead corresponding to a pin of the chip. The input of the microstrip line circuit 102 can be directly connected to any lead. In this case, the lead connected to the input of the microstrip line circuit 102 can be a reusable lead, allowing the selection of the microstrip line circuit 102 by using this lead. Alternatively, the core circuit 101 can also have at least one switch, which can be a MOSFET, transistor, diode, etc. The input of the microstrip line circuit 102 can be connected to any lead via the switch, allowing the selection of the microstrip line circuit 102 by controlling the opening and closing of the switch.
[0038] Figure 4 This is a schematic diagram showing the microstrip line circuit 102 integrated within a chip according to this embodiment. Figure 4 As shown, the microstrip line circuit 102 is formed within the chip's packaging substrate 100a, and the core circuit 101 on the die has reserved space for a MOSFET. Figure 4 (Not shown in the image) This circuit acts as a switch to activate the microstrip line circuit 102. The input terminal of the microstrip line circuit 102 is connected to pad B via a lead. Pad B is connected to a MOSFET, which is then connected to its corresponding output terminal. The output terminal of the microstrip line circuit 102 is grounded via via C. Thus, the input terminal of the microstrip line circuit 102 can be connected to the output terminal via a MOSFET, while the output terminal can be connected to ground on the package substrate 100a. When in use, the microstrip line circuit 102 can dissipate the energy radiated by the core circuit 101, providing a radiation margin for the chip and improving its EMC performance.
[0039] Optionally, the packaging substrate 100a can be a packaging substrate based on BGA packaging, a packaging substrate based on LGA packaging, a packaging substrate based on WLCSP packaging, etc., which will not be listed here.
[0040] Optionally, the microstrip line circuit 102 can be formed in a free area of the packaging substrate 100a (a region where no other structure needs to be formed), or it can be integrated in the redistribution layer (RDL) of the packaging substrate 100a, simplifying the fabrication process.
[0041] In some embodiments, the microstrip circuit 102 can be integrated in a system on chip (SOC chip). Specifically, the circuit structure can be a system on chip having at least two dies and at least one packaging substrate, the core circuit 101 is formed on each die, and the microstrip circuit 102 is formed on at least one packaging substrate in the system on chip. In this case, the chip substrate mentioned above is at least one packaging substrate in the system on chip.
[0042] Further, each die has a ground lead-out terminal (lead-out terminal for grounding), the ground lead-out terminal corresponds to a ground pin (GND) of the chip, and the input terminal and the output terminal of the microstrip circuit 102 are connected to the ground lead-out terminals of the two dies, thereby balancing the ground of the two dies and solving the problem of ground fluctuation of the two dies.
[0043] In some embodiments, each die has at least one lead-out terminal, one lead-out terminal corresponds to one pad of the die, and the input terminal of the microstrip circuit 102 can be directly connected to one lead-out terminal of at least one die. In this case, the input terminal of the microstrip circuit 102 can be connected to a reusable lead-out terminal, and the selection of the microstrip circuit 102 can be realized by calling this lead-out terminal. In addition, when the microstrip circuit 102 is connected to the lead-out terminals of multiple dies, it can be shared by multiple dies. Of course, each die can also have at least one switch, which can be a MOS tube, a transistor, a diode, etc. The input terminal of the microstrip circuit 102 can be connected to the lead-out terminal of at least one die through the switch, and the selection of the microstrip circuit 102 can be realized by controlling the opening and closing of the switch. In addition, when the microstrip circuit 102 is connected to the lead-out terminals of multiple dies through the switch, it can be shared by multiple dies.
[0044] Figure 5 A schematic diagram of the microstrip circuit 102 integrated in a system on chip is provided for the present embodiment. As shown in Figure 5 The system on chip has two dies and three packaging substrates, the microstrip circuit 102 is formed in the packaging substrate 100b, and each die has a via C on the corresponding packaging substrate 100a. The input terminal and the output terminal of the microstrip circuit 102 are grounded through the lead and the via C. In this way, the input terminal and the output terminal of the microstrip circuit 102 are connected to the ground of the packaging substrate 100a of one die, thereby balancing the ground of the two dies. In some embodiments, one microstrip circuit 102 can be arranged on the corresponding packaging substrate 100a of each die, the input terminal of the microstrip circuit 102 is connected to the core circuit on the corresponding die, and the output terminal is grounded.
[0045] Figure 6 A cross-sectional schematic diagram of a system on chip is provided for the present embodiment. As shown in Figure 6As shown, the system chip can also have two dies and a package substrate 100b, at this time, the two dies are packaged on the package substrate 100b, and the microstrip circuit 102 can be formed on the package substrate 100b. Further, the microstrip circuit 102 can be integrated in a ReDistribution Layer (RDL) of the package chip substrate 100b, simplifying the manufacturing process, and in some embodiments, the microstrip circuit 102 can also be formed in a certain free area (an area that does not need to form other structures) of the package substrate 100b, which will not be illustrated one by one here.
[0046] In summary, in the circuit structure provided by the embodiments of the present application, the circuit structure includes a chip substrate and a microstrip circuit 102, the chip substrate has a core circuit 101, the microstrip circuit 102 is formed above or below the chip substrate, and the input end is connected to the core circuit 101 and the output end is grounded to consume the energy radiated by the core circuit 101. The present application designs the large-size attenuation filter circuit into a small-size microstrip circuit 102, which can consume the energy radiated by the core circuit 101, reserve a radiation margin for the circuit structure, and improve the EMC performance of the circuit structure; at the same time, the microstrip circuit 102 can be integrated on the package substrate of the chip, or directly formed on the PCB package substrate, saving peripheral discrete components, reducing space occupation, simplifying peripheral wiring, and after the design of the microstrip circuit 102 is completed, the microstrip circuit 102 can consume a predetermined amount of radiation according to the standard requirements, without the need for real-time adjustment of its parameters, and the use is more convenient; the manufacturing process of the microstrip circuit 102 is compatible with semiconductor manufacturing processes such as photolithography, plating, and etching, and the production and processing of the microstrip circuit 102 can be synchronized with the production and processing of the chip substrate, and the manufacturing and design processes are relatively simple, and the process implementation is relatively convenient; and when the microstrip circuit 102 is integrated in the chip, the output end of the microstrip circuit 102 is connected to the ground of the chip, which is beneficial to reducing external interference and radiation loss due to the good integrity of the ground of the chip, and can improve the EMC performance of the chip.
[0047] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other.
[0048] It should also be noted that, although the present application has been described in terms of the preferred embodiments, the embodiments disclosed are not intended to limit the scope of the present application, which is limited only by the claims below. Various modifications and alterations to this application can become apparent to those skilled in the art from the preceding description and drawings, and it is intended that all such modifications and alterations fall within the scope of the present application.
[0049] It should also be understood that, unless specifically stated otherwise, references to "a" or "an" or "the" or "at least one" or "one or more" should be construed to mean "one or more" unless otherwise indicated to the contrary. Also, the use of "or" means "and / or" unless stated otherwise.
[0050] It should also be appreciated that the terms "first", "second", "third", and the like, as used in the description and the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of use in either order. It is also to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting. It must be noted that, as used in the specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "the step" can mean one or more steps, and equivalents thereof. All conjunctions used in the present disclosure are to be understood within the most expansive sense possible, such that all examples they convey can take on a wide variety of meanings and embodiments. Also, the phrase "or the like" is intended to mean "or the like" or "or the like, or the like" or "or the like, or the like, or the like" and so on. Furthermore, the use of the term "including" as well as "comprising" as used herein is intended to have a broad meaning analogous to the term "comprising" and does not mean limited to the elements listed after the term, and does not exclude additional elements.
Claims
1. A circuit structure, characterized by, The circuit structure comprises: a chip substrate, which has a core circuit on or under the chip substrate; and a microstrip line circuit formed on the chip substrate, an input end of the microstrip line circuit being connected to the core circuit, and an output end of the microstrip line circuit being grounded to dissipate energy radiated by the core circuit.
2. The circuit structure of claim 1, wherein, The microstrip line circuit comprises a plurality of microstrip lines connected to each other, and the microstrip lines comprise a resistive microstrip line, an inductive microstrip line and a capacitive microstrip line.
3. The circuit structure of claim 1 or 2, characterized in that, The chip substrate is a PCB packaging substrate, and the microstrip line circuit is an on-board circuit on the PCB packaging substrate.
4. The circuit structure of claim 2, wherein, The core circuit has at least one circuit interface, and the input end of the microstrip line circuit is connected to the circuit interface.
5. The circuit structure of claim 1, wherein, The circuit structure is a chip, the core circuit is formed on a die of the chip, and the chip substrate is a packaging substrate of the chip.
6. The circuit structure of claim 5, wherein, The core circuit has at least one lead-out end, and the input end of the microstrip line circuit is connected to the lead-out end.
7. The circuit structure of claim 5, wherein, The core circuit has at least one lead-out end and at least one switch, and the input end of the microstrip line circuit is connected to the lead-out end through the switch.
8. The circuit structure of claim 1, wherein, The circuit structure is a hybrid chip, the hybrid chip comprises at least two dies and at least one packaging substrate, the core circuit is formed on each of the dies, and the chip substrate is at least one of the packaging substrates in the hybrid chip.
9. The circuit structure of claim 8, wherein, Each of the dies has a ground lead-out end, and the input end and the output end of the microstrip line circuit are respectively connected to the ground lead-out ends of the two dies.
10. The circuit structure of claim 8, wherein, The die has at least one lead-out end, and the input end of the microstrip line circuit is connected to the lead-out end of the at least one die.
11. The circuit structure of claim 8, wherein, The die has at least one lead-out end and at least one switch, and the input end of the microstrip line circuit is connected to the lead-out end of the at least one die through the corresponding switch.
12. The circuit structure of claim 5 or 8, wherein, The microstrip line circuit is formed in a free area of the chip substrate, or the microstrip line circuit is integrated in a redistribution layer of the chip substrate.