Wafer structure
By introducing isolation layers and reinforcement channels into the wafer structure, the problem of laser etched wafers being unable to cut PI materials is solved, thus protecting the chip circuit layer and improving packaging reliability and wafer utilization.
Patent Information
- Application Number
- CN202423214544.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-02-06
- Estimated Expiration
- 2034-12-25
AI Technical Summary
Existing laser lithography methods cannot cut metal and PI materials, which reduces packaging reliability and affects product reliability.
An isolation layer is introduced into the wafer structure. The isolation layer is attached to the sidewall of the dicing track and includes bumps and reinforcement tracks to protect the chip circuit layer and improve the reliability and stability of removing PI material from the dicing track.
By designing isolation layers and hardening channels, the chip circuit layers are protected, improving the stability of the wafer dicing process and the safety of the chip, thereby enhancing packaging reliability and wafer utilization.
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Figure CN223885632U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, for example to a wafer structure. BACKGROUND
[0002] In related technologies, in order to improve the utilization rate of the wafer, a laser hidden cutting method is used to cut the wafer. However, the laser hidden cutting method can only cut silicon materials, and cannot cut metal materials and PI (Polyimide) materials.
[0003] Therefore, in order to be able to cut the wafer by using the laser hidden cutting method, the PI material at the cutting path is cancelled.
[0004] However, in the implementation process, the cancellation of the PI material at the cutting path reduces the packaging reliability, and further affects the reliability of the product. SUMMARY
[0005] The following presents a simplified summary of some aspects of the disclosed embodiments in order to provide a basic understanding of such embodiments. This summary is not an extensive overview of the embodiments described in detail in the following detailed description, and is intended neither to identify key or critical elements nor to delineate the scope of such embodiments. Rather, the primary purpose of this summary is merely to present some concepts of the disclosed embodiments in a simplified form as a prelude to the more detailed description presented later.
[0006] The wafer structure provided by the embodiments of the present disclosure can solve the problem of low packaging reliability.
[0007] In some embodiments, a wafer structure is provided, including: a wafer body, the wafer body including a cutting path and a chip, the cutting path being located between two adjacent chips; and an isolation layer, the isolation layer being arranged on a peripheral sidewall of the chip and being attached to a sidewall of the cutting path.
[0008] Optionally, the thickness of the isolation layer is in a range of 1 um to 2 um.
[0009] Optionally, in a depth direction of the cutting path, the height of the isolation layer is greater than or equal to the height of the chip.
[0010] Optionally, the isolation layer includes a protrusion, and an opening of the cutting path is located between two adjacent protrusions of the isolation layer.
[0011] Optionally, in a width direction of the opening of the cutting path, the height of the protrusion is in a range of 1 um to 3 um.
[0012] Optionally, the width of the opening of the cutting path is in a range of 8 um to 14 um.
[0013] Optionally, the wafer structure further includes: a reinforcing path, the reinforcing path being arranged on the peripheral sidewall of the chip, being located between the isolation layer and the sidewall of the chip, and being located on one side of the bottom of the cutting path.
[0014] Optionally, the width of the reinforcing path ranges from 3um to 5um.
[0015] Optionally, the wafer structure further comprises a protection ring arranged on the peripheral side of the chip, and the reinforcing path is located between the protection ring and the isolation layer.
[0016] Optionally, the width of the cutting path ranges from 15um to 30um.
[0017] The wafer structure provided by the embodiments of the present disclosure can achieve the following technical effects:
[0018] The wafer structure provided by the present disclosure comprises a wafer body and an isolation layer. The wafer body is divided into a plurality of chips by a cutting path. An isolation layer is arranged on the peripheral side wall of each chip, and the isolation layer is in close contact with the side wall of the cutting path.
[0019] By adopting the wafer structure provided by the present disclosure, the isolation layer is arranged on the peripheral side of the chip and located on the side wall of the cutting path. The isolation layer protects the circuit layer of the chip, improves the reliability and safety of the removal of PI material in the cutting path part, and protects the reliability of the circuit layer. In addition, the protection of the chip by the isolation layer can improve the stability of the wafer cutting process and the safety of the chip.
[0020] The foregoing general description and the following description are only exemplary and explanatory, and are not intended to limit the present application. BRIEF DESCRIPTION OF DRAWINGS
[0021] One or more embodiments are exemplarily illustrated by corresponding drawings, which do not constitute limitation on the embodiments, and elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute proportional limitation, and wherein:
[0022] Figure 1 is a structure schematic diagram of a wafer structure provided by the embodiments of the present disclosure;
[0023] Figure 2 is Figure 1 is a distribution schematic diagram of part of the chips and the cutting path of the wafer structure provided by the embodiments;
[0024] Figure 3 is Figure 2 is an enlarged structure schematic diagram of the wafer structure at A provided by the embodiments shown;
[0025] Figure 4 is a cross-sectional structure schematic diagram of part of the structure of the wafer structure provided by the embodiments of the present disclosure;
[0026] Figure 5 is Figure 1 is a structure schematic diagram of a single shot of the wafer structure provided by the embodiments shown;
[0027] Figure 6 is a structural schematic diagram of a single shot of a wafer structure provided by one embodiment of the present disclosure.
[0028] Reference signs:
[0029] 1 wafer structure;
[0030] 100 wafer body; 110 chip; 112 circuit layer; 120 dicing lane; 122 opening; 130 isolation layer; 132 bump; 140 reinforcement lane; 150 protection ring; 160 exposure area; 162 functional chip; 164 test chip. DETAILED DESCRIPTION
[0031] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and wafer structures can be simplified.
[0032] The terms "first", "second", and the like in the specification and claims of the embodiments of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.
[0033] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "back", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and its embodiments, and are not used to limit the indicated wafer structure, element or component must have a specific orientation, or be constructed and operated in a specific orientation. And, in addition to indicating the orientation or positional relationship, the above-mentioned terms can also be used to indicate other meanings, for example, the term "upper" can also be used to indicate a certain attachment relationship or connection relationship in some cases. For those skilled in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to the specific circumstances.
[0034] In addition, the terms "set", "connected", and "fixed" should be understood broadly. For example, "connected" can be fixed connection, detachable connection, or integral configuration; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection via an intermediate medium, or internal connection between two wafer structures, elements, or components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present disclosure according to the specific circumstances.
[0035] Unless otherwise specified, the term "plurality" means two or more.
[0036] In the embodiments of the present disclosure, the character " / " represents an "or" relationship between the objects before and after it. For example, A / B means A or B.
[0037] The term "and / or" is a description of the association relationship between objects, which means that there can be three relationships. For example, A and / or B means that there are three relationships of A or B, or A and B.
[0038] It should be noted that the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0039] In some embodiments, in combination with Figures 1 to 6 As shown, a wafer structure 1 is provided, comprising a wafer body 100 and an isolation layer 130. The wafer body 100 comprises a cutting channel 120 and a chip 110, and the cutting channel 120 is located between two adjacent chips 110. The isolation layer 130 is arranged on the peripheral side wall of the chip 110 and is attached to the side wall of the cutting channel 120.
[0040] The wafer structure 1 provided by the present disclosure divides the wafer body 100 into a plurality of chips 110 through the cutting channel 120. The isolation layer 130 is arranged on the peripheral side wall of each chip 110, and the isolation layer 130 is attached to the side wall of the cutting channel 120.
[0041] In combination with Figure 3 And Figure 4 As shown, by using the wafer structure 1 provided by the present disclosure, the isolation layer 130 is arranged on the peripheral side wall of the chip 110 and is located on the side wall of the cutting channel 120. The isolation layer 130 can isolate the chip 110 and prevent short circuit that may occur during cutting or subsequent use, so as to protect the circuit layer 112 of the chip 110, improve the reliability and safety of the PI material removed from the cutting channel 120, and protect the reliability of the circuit layer 112. In addition, the protection of the chip 110 by the isolation layer 130 can improve the stability of the wafer cutting process and the safety of the chip 110.
[0042] Optionally, the isolation layer 130 is a PI (Polyimide) isolation layer. The PI isolation layer has good mechanical strength and flexibility, and can withstand high-temperature processing in the wafer manufacturing process. In this way, the PI isolation layer not only prevents external moisture from entering the circuit layer 112 of the chip 110, but also protects the circuit layer 112 from damage during the scribing process.
[0043] In some embodiments, the thickness of the isolation layer 130 is in the range of 1 um to 2 um.
[0044] In this embodiment, the isolation layer 130 with a thickness of 1 um to 2 um can ensure good electrical insulation performance and maintain the stability of the structure.
[0045] In the implementation process, the thickness of the isolation layer 130 can be reasonably set according to different application environments to meet the isolation requirements, which will not be described here.
[0046] Optionally, the thickness of the isolation layer 130 includes, but is not limited to, 1 um, 1.5 um, or 2 um.
[0047] In some embodiments, in combination with Figure 4 As shown in FIG. 1B, along the depth direction of the scribe lane 120, the height of the isolation layer 130 is greater than or equal to the height of the chip 110.
[0048] In this embodiment, by setting the height of the isolation layer 130 to be greater than or equal to the height of the chip 110, the isolation layer 130 can extend from the bottom of the chip 110 to or beyond the top of the chip 110, thereby improving the coverage effect of the entire sidewall of the chip 110 to prevent debris, dust, or other contaminants generated during the cutting process from contacting the sidewall of the chip 110, thereby avoiding potential electrical short circuit or functional damage, and improving the protection of the chip 110.
[0049] In some embodiments, in combination with Figure 4 As shown in FIG. 1C, the isolation layer 130 includes protrusions 132, and the opening of the scribe lane 120 is located between two adjacent protrusions 132 of the isolation layer 130.
[0050] In this embodiment, the sidewall of the isolation layer 130 at one end of the opening 122 of the scribe lane 120 is provided with a protrusion 132 extending towards the inside of the scribe lane 120. In this way, there are protrusions 132 extending along the length direction of the scribe lane 120 on both sides of the opening 122 of the scribe lane 120. By setting the protrusions 132, the protrusions 132 play a protective role for the chip 110 during the scribing process.
[0051] Optionally, the shape of the protrusion 132 includes, but is not limited to, a circle, an ellipse, a square, a triangle, etc., and is selected according to the material properties and manufacturing process of the isolation layer 130.
[0052] Optionally, the protrusions 132 are uniformly distributed or arranged in a specific pattern along the extension direction of the cutting path 120, for example, the density of the protrusions 132 is increased in the stress concentration area to improve the local strength.
[0053] In some embodiments, the height of the protrusion 132 ranges from 1 um to 3 um along the width direction of the opening 122 of the cutting path 120.
[0054] In this embodiment, the height of the protrusion 132 is set to 1 um to 3 um. On the one hand, by setting the protrusion 132 with an appropriate height, the strength and stability of the structure are improved. On the other hand, the space with the height of the protrusion 132 removed at the opening 122 of the cutting path 120 can meet the requirements of the cutting process, so that the chip 110 can be smoothly cut.
[0055] The height of the protrusion 132 can be adjusted according to different cutting process requirements to adapt to different production requirements.
[0056] Optionally, the specific value of the height of the protrusion 132 includes, but is not limited to, 1 um, 1.5 um, 2 um, 2.5 um, or 3 um.
[0057] In some embodiments, the width of the opening 122 of the cutting path 120 ranges from 8 um to 14 um.
[0058] In this embodiment, the width of the opening 122 of the cutting path 120 is set to 8 um to 14 um to meet the implementation of the cutting process.
[0059] Specifically, the width of the opening 122 of the cutting path 120 can be adjusted according to the precision of the cutting equipment and the size of the chip 110.
[0060] Optionally, the specific value of the width D of the opening 122 of the cutting path 120 includes, but is not limited to, 8 um, 9 um, 10 um, 11 um, 12 um, 13 um, or 14 um.
[0061] In some embodiments, in combination with the above-mentioned embodiments, the width of the opening 122 of the cutting path 120 ranges from 8 um to 14 um. Figure 3 As shown, the wafer structure 1 further includes a reinforcing path 140. The reinforcing path 140 is arranged on the side wall of the chip 110, located between the isolation layer 130 and the side wall of the chip 110, and located on one side of the bottom of the cutting path 120.
[0062] In this embodiment, the reinforcing path 140 is located between the isolation layer 130 and the sidewall of the chip 110, enhancing the structural strength of the sidewall of the chip 110, on one hand, ensuring the stress resistance of the wafer after cutting; on the other hand, preventing the cutting of the circuit layer 112 of the chip 110 in the cutting process, and improving the protection of the chip 110.
[0063] Optionally, the reinforcing path 140 is set between the sidewall of the chip 110 and the isolation layer 130 by using Poly dummy. Poly dummy is a virtual polysilicon structure unrelated to actual electronic components, which is inserted into different areas of the wafer to fill blank spaces or adjust process steps. By using Poly dummy as the reinforcing path 140, defects caused by mechanical stress in the manufacturing process are reduced, thereby improving the overall yield. In addition, under the action of long-term use or environmental stress (such as temperature change, vibration, etc.), the reinforcing path 140 helps to maintain the stability of the structure of the chip 110, thereby improving the reliability of the product. In different areas of the wafer, due to process deviation or design reasons, uneven stress may be generated. The polysilicon reinforcing path 140 can help balance these stresses and reduce defects caused by stress concentration.
[0064] In some embodiments, the width of the reinforcing path 140 ranges from 3um to 5um.
[0065] In this embodiment, the reinforcing path 140 with a width of 3um to 5um can provide sufficient mechanical strength to support the sidewall of the chip 110 on the wafer, especially during deep trench isolation or cutting, which helps to prevent sidewall collapse or cracking. In addition, it helps to uniformly disperse the stress generated during processing or use, reducing local stress concentration, thereby reducing the risk of damage to the chip 110. A wider reinforcing path 140 can prevent over-etching during deep trench etching, protecting the sidewall of the chip 110 from excessive erosion.
[0066] Optionally, the width of the reinforcing path 140 can be adjusted according to the size of the chip 110 and process requirements.
[0067] Optionally, the specific value of the width of the reinforcing path 140 includes but is not limited to 3um, 3.5um, 4um, 4.5um or 5um.
[0068] In some embodiments, in combination with Figure 3 As shown, the wafer structure 1 further comprises a protection ring 150. The protection ring 150 is arranged on the side of the chip 110, and the reinforcing path 140 is located between the protection ring 150 and the isolation layer 130.
[0069] In this embodiment, the seal ring 150 is used to protect the edge of the chip 110, which is located between the chip 110 and the cutting path 120, to prevent the chip 110 from being mechanically damaged during the cutting process, and to improve the protection effect of the chip 110. And the seal ring 150 can block the moisture from the cutting side to invade the inside of the chip 110, and protect the chip 110 from the influence of environmental humidity.
[0070] Further, the seal ring 150 is arranged on the side of the chip 110, and the reinforcing path 140 is arranged between the seal ring 150 and the isolation layer 130, so as to form a three-layer protection structure, so as to enhance the protection effect of the chip 110 and improve the reliability of the chip 110.
[0071] Optionally, the seal ring 150 (Sealring) includes a ring-shaped diffusion region (Diff) and a ring-shaped metal contact via (Metal Contact Via). The ring-shaped diffusion region is usually composed of a doped silicon layer, which surrounds the edge of the chip 110 to form a continuous ring structure. The ring-shaped metal contact via is a through hole formed on the silicon wafer, which is used to connect different levels of metal. The ring-shaped metal contact via connects the ring-shaped diffusion region and the upper metal to form a closed electrical connection ring, thereby enhancing the mechanical and electrical integrity of the seal ring 150.
[0072] In some embodiments, the width B of the cutting path 120 is in the range of 15um to 30um.
[0073] In this embodiment, by setting the width of the cutting path 120 to 15um to 30um, the utilization rate of the wafer structure 1 is improved. By reducing the width of the cutting path 120, the number of chips 110 that can be divided from the wafer structure 1 is increased, and the production cost is reduced.
[0074] Optionally, the specific value of the width of the cutting path 120 includes but is not limited to 15um, 17um, 19um, 20um, 22um, 24um, 26um, 28um or 30um.
[0075] In some embodiments, in combination with Figure 5 and Figure 6 As shown, the chip 110 includes a functional chip 162 and a test chip 164, and the test chip 164 is used for wafer process testing. By arranging the test chip 164, the Test-key arranged in the cutting path 120 in the related art is cancelled, that is, the wafer test after the wafer process is made, and the width of the cutting path 120 is reduced, and the packaging cutting can be completed. And the area of the cutting path 120 is much larger than the area of the test chip 164, so as to achieve the purpose of improving the number of effective chips 110.
[0076] In some embodiments, the laser scribe method is used to scribe along the scribe line 120 of the wafer structure 1. Since a too small scribe line 120 cannot achieve a safe scribing method, by using the laser scribe method for scribing, the packaging process scribing can be achieved in the case of a narrower scribe line 120. In this way, by reducing the width of the scribe line 120, the wafer utilization is improved. And the effect of packaging process scribing can be improved.
[0077] In some embodiments, as shown in Figure 1 The wafer body 100 includes a plurality of shots 160, and each shot 160 includes a plurality of functional chips 162 and a test chip 164. Figure 1 、 Figure 5 and Figure 6 The number of test chips 164 is one or more test chips 164. The test chip 164 is used to realize the wafer process test in a single shot.
[0078] In some embodiments, as shown in Figure 1 The wafer body 100 includes a plurality of shots 160, and each shot 160 includes a plurality of functional chips 162. The plurality of shots 160 share one or more test chips 164 for process test. In this way, the position and number of test chips 164 can be set according to the test requirements, so as to improve the wafer utilization.
[0079] The above description and drawings sufficiently illustrate the embodiments of the present disclosure to enable one skilled in the art to practice them. Other embodiments can include structural and other changes. The embodiments represent only the possible variations. Individual components and functions are optional unless specifically required, and the order of operations can be changed. Some parts and features of some embodiments can be included or replaced by parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A wafer structure, characterized by, The wafer structure comprises: a wafer body comprising a cutting path and a chip, the cutting path being located between two adjacent chips; an isolation layer arranged on the side wall of the chip and adhering to the side wall of the cutting path.
2. The wafer structure of claim 1, wherein: the thickness of the isolation layer is in a range of 1um to 2um; and / or the isolation layer is a polyimide isolation layer.
3. The wafer structure of claim 1, wherein: in the depth direction of the cutting path, the height of the isolation layer is greater than or equal to the height of the chip.
4. The wafer structure of any one of claims 1 to 3, wherein: the isolation layer comprises a protrusion, and the opening of the cutting path is located between two adjacent protrusions of the isolation layer.
5. The wafer structure of claim 4, wherein: in the width direction of the opening of the cutting path, the height of the protrusion is in a range of 1um to 3um.
6. The wafer structure of any one of claims 1 to 3, wherein: the width of the opening of the cutting path is in a range of 8um to 14um.
7. The wafer structure of any one of claims 1 to 3, wherein, The wafer structure further comprises: a reinforcing path arranged on the side wall of the chip, located between the isolation layer and the side wall of the chip, and located on one side of the bottom of the cutting path.
8. The wafer structure of claim 7, wherein: the width of the reinforcing path is in a range of 3um to 5um.
9. The wafer structure of claim 7, wherein, The wafer structure further comprises: a protection ring arranged on the side of the chip, and the reinforcing path is located between the protection ring and the isolation layer.
10. The wafer structure of any one of claims 1 to 3, wherein: the width of the cutting path is in a range of 15um to 30um.