Packaging carrier and Doherty amplifier

Abstract

The utility model discloses a packaging carrier and a Doherty amplifier comprising the packaging carrier. The packaging carrier comprises a first input interface and a second input interface, a first output interface and a second output interface; a substrate; the first transistor is located on the substrate, the control end of the first transistor is coupled to the first input interface, and the output end of the first transistor is coupled to the first output interface; the second transistor is located on the substrate, the control end of the second transistor is coupled to the second input interface, the output end of the second transistor is coupled to the second output interface, the first transistor comprises a silicon carbide-based transistor, and the second transistor comprises a silicon-based transistor; and the bias circuit is configured to provide corresponding bias voltages for the first transistor and the second transistor.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency communication, specifically to a packaging carrier and a Doherty amplifier including the packaging carrier. Background Technology

[0002] To meet the requirements of high power, high efficiency and miniaturization of various amplifiers in the field of radio frequency communication, it is becoming increasingly popular to package multiple transistors in parallel in the same carrier. This type of carrier, together with suitable peripheral circuits, can support a variety of amplifier architectures, such as balanced amplifiers, Doherty amplifiers and out-phasing amplifiers.

[0003] In related technologies, transistors using the same semiconductor process are often packaged in the same carrier. For example, Figure 1A The package carrier 110 shown includes two silicon-based transistors (111, 112). Figure 1B The package carrier 120 shown includes two gallium nitride-based transistors (121, 122). However, on the one hand, while silicon-based transistors are inexpensive, they have lower efficiency and larger parasitic capacitance. On the other hand, while gallium nitride-based transistors have higher efficiency, they are more expensive, and these transistors exhibit significant nonlinear characteristics and trapping effects. Utility Model Content

[0004] In view of this, the present invention discloses a packaging carrier and a Doherty amplifier including the packaging carrier, so as to alleviate, reduce or even eliminate the above problems.

[0005] According to one aspect of the present invention, an embodiment of the present invention discloses a packaging carrier, comprising: a first input interface and a second input interface; a first output interface and a second output interface; a substrate; a first transistor, wherein the first transistor is located on the substrate, a control terminal of the first transistor is coupled to the first input interface, and an output terminal of the first transistor is coupled to the first output interface; a second transistor, wherein the second transistor is located on the substrate, a control terminal of the second transistor is coupled to the second input interface, and an output terminal of the second transistor is coupled to the second output interface, and wherein the first transistor comprises a silicon carbide-based transistor, and the second transistor comprises a silicon-based transistor; and a bias circuit configured to provide corresponding bias voltages for the first transistor and the second transistor.

[0006] In some embodiments, the package structure further includes a sub-package structure located on the substrate and including the first transistor and the second transistor, wherein the sub-package structure further includes: a first input node and a first output node, wherein the first input node is coupled to the first input interface and the control terminal of the first transistor, and the first output node is coupled to the output terminal of the first transistor and the first output interface; a second input node and a second output node, wherein the second input node is coupled to the second input interface and the control terminal of the second transistor, and the second output node is coupled to the output terminal of the second transistor and the second output interface.

[0007] In some embodiments, the sub-package structure further includes: a base that carries at least a portion of the circuit elements in the sub-package structure; and a protective cover that cooperates with the base to enclose at least a portion of the circuit elements in the sub-package structure.

[0008] In some embodiments, the length of the base and the protective cover is between 10 mm and 20 mm, and the length of the first transistor is between 5 mm and 10 mm.

[0009] In some embodiments, the sub-package structure further includes: a first capacitor, wherein one end of the first capacitor is coupled to the output terminal of the first transistor and the other end is coupled to a first output node of the sub-package structure; and a second capacitor, wherein one end of the second capacitor is coupled to the output terminal of the second transistor and the other end is coupled to a second output node of the sub-package structure.

[0010] In some embodiments, at least one of the following couplings can be implemented by bonding wires or microstrip lines: the coupling between the first input node and the first input interface and the control terminal of the first transistor, the coupling between the second input node and the second input interface and the control terminal of the second transistor, the coupling between the first capacitor and the output terminal of the first transistor and the first output node of the subpackage structure, and the coupling between the second capacitor and the output terminal of the second transistor and the second output node of the subpackage structure.

[0011] In some embodiments, the bias circuit includes: a first bias circuit configured to provide a gate bias voltage to the first transistor; a second bias circuit configured to provide a gate bias voltage to the second transistor; and a third bias circuit configured to provide a drain bias voltage to the first transistor and the second transistor.

[0012] In some embodiments, the third bias circuit includes a first sub-bias circuit and a second sub-bias circuit, wherein: the first sub-bias circuit is configured such that the first transistor provides a drain bias voltage; and the second sub-bias circuit is configured such that the second transistor provides a drain bias voltage.

[0013] In some embodiments, the gate bias voltage provided to the first transistor is between -6 volts and -4 volts, and the gate bias voltage provided to the second transistor is between 0 volts and 3 volts.

[0014] According to another aspect of the present invention, an embodiment of the present invention discloses a Doherty amplifier, comprising: an RF input interface coupled to an input terminal of a power divider of the Doherty amplifier; a package carrier according to any of the foregoing embodiments of the present invention, wherein the first input interface and the second input interface of the package carrier are coupled to an output terminal of the power divider, the first transistor is configured to obtain a first amplified signal based on a first signal from the first input interface, and the second transistor is configured to obtain a second amplified signal based on a second signal from the second input interface; and a combining matching network coupled between the first output interface, the second output interface of the package carrier, and the RF output interface of the Doherty amplifier.

[0015] In some embodiments, the package carrier further includes: a third input interface and a third output interface, wherein the third input interface is coupled to the output of the power divider and the third output interface is coupled to the combining matching network; a third transistor, wherein the third transistor is located on the substrate, the control terminal of the third transistor is coupled to the third input interface, the output terminal of the third transistor is coupled to the third output interface, and wherein the third transistor is configured to obtain a third amplified signal based on a third signal from the third input interface.

[0016] In the packaging carrier provided according to the embodiments of the present invention, first and second transistors are disposed on the substrate of the packaging carrier, wherein the first transistor includes a silicon carbide-based transistor and the second transistor includes a silicon-based transistor. These transistors cooperate with other circuit elements in the packaging carrier to leverage the advantages of both silicon-based and silicon carbide-based transistors, thereby helping to control the cost of the packaging carrier, the parasitic capacitance of the transistors within the packaging carrier, and enabling the packaging carrier to have high operating efficiency and good linearity.

[0017] These and other aspects of the present invention will become clear from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0018] In the following description of exemplary embodiments in conjunction with the accompanying drawings, more details, features, and advantages of the present invention are disclosed, in which:

[0019] Figure 1A and Figure 1B An exemplary architecture diagram of a packaging carrier in the related art is illustrated schematically;

[0020] Figure 2 An exemplary architecture diagram of a packaging carrier according to some embodiments of the present invention is shown schematically;

[0021] Figure 3 An exemplary architecture diagram of a packaging carrier according to other embodiments of the present invention is shown schematically;

[0022] Figure 4 An exemplary architecture diagram of a packaging carrier according to further embodiments of the present invention is shown schematically;

[0023] Figure 5 The sub-package structure according to some embodiments of the present invention is illustrated schematically;

[0024] Figure 6 The sub-package structure according to some other embodiments of the present invention is illustrated schematically;

[0025] Figure 7 The schematic diagram illustrates an exemplary package structure of a Doherty amplifier according to some embodiments of the present invention;

[0026] Figure 8 The schematic diagram illustrates an exemplary package structure of a Doherty amplifier according to other embodiments of the present invention;

[0027] Figure 9 The schematic diagram illustrates an exemplary package structure of a Doherty amplifier according to further embodiments of the present invention; and

[0028] Figure 10 The diagram schematically illustrates an example of the performance of a Doherty amplifier according to some embodiments of the present invention. Detailed Implementation

[0029] Several embodiments of the present invention will now be described in more detail with reference to the accompanying drawings to enable those skilled in the art to implement the technical solutions of the present invention. The technical solutions of the present invention can be embodied in many different forms and for many different purposes, and should not be limited to the embodiments set forth herein. These embodiments are provided to make the technical solutions of the present invention clear and complete, but the embodiments do not limit the scope of protection of the present invention.

[0030] Here, some terms involved in the various embodiments of this utility model will be explained first, so that those skilled in the art can understand them.

[0031] 1. Package Structure: Refers to a product formed by different components being fabricated on the same substrate through integration processes and sealed within the same package housing. The package structure can take the form of a chip. Similarly, the term "subpackage structure" mentioned in this article has similar characteristics to the above-mentioned package structure. It can also take the form of a chip. However, the "subpackage structure" is fabricated on the substrate of the above-mentioned package structure and sealed inside the package structure. That is, the subpackage structure can be regarded as a component of the package structure.

[0032] 2. Transistor: A semiconductor device comprising three terminals, which may include a gate, a source, and a drain, or a base, a collector, and an emitter. In this article, the control terminal of a transistor refers to either the gate or the base, and the output terminal refers to either the source or the drain, or the collector or the emitter.

[0033] 3. Silicon-based transistors: These are transistors whose current-conducting channels are mainly made of silicon semiconductor materials. Examples of silicon-based transistors include, but are not limited to, lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and bipolar junction transistors (BJTs).

[0034] 4. Silicon carbide-based transistors: These are transistors whose current-carrying channels are primarily made of silicon carbide semiconductor material. Examples of silicon carbide-based transistors include, but are not limited to, lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and junction field-effect transistors (JFETs).

[0035] 5. Input Interface, Input Node, Output Interface, and Output Node: These refer to the connection points / connection elements between the package carrier containing such an interface / node and the device containing such a package carrier (e.g., a Doherty amplifier) ​​and external circuits or systems. Taking input and output interfaces as examples, from a physical perspective, the input interface (e.g., the first input interface, second input interface, and RF input interface described below with reference to several figures) is the physical connection point / connection element for the corresponding package carrier and the Doherty amplifier to receive external RF signals, while the output interface (e.g., the first output interface, second output interface, and RF output interface described below with reference to several figures) is the physical connection point / connection element for the corresponding package carrier and the Doherty amplifier to output amplified RF signals to external circuits or systems. These input and output interfaces can have various suitable shapes and structures, including but not limited to pads, gaskets, sockets, pins, etc. From an electrical perspective, these interfaces not only provide physical connections but can also be designed with specific impedance characteristics to ensure good matching with external circuits and reduce signal reflection and loss.

[0036] Figure 2 An exemplary architectural diagram of a packaging carrier 200 according to some embodiments of the present invention is shown schematically. Figure 2 As shown, the package carrier 200 includes: a first input interface 230a and a second input interface 230b, a first output interface 240a and a second output interface 240b, a substrate, a first transistor 210, a second transistor 220, and bias circuits (250, 260, 270).

[0037] A first transistor 210 and a second transistor 220 are located on a substrate. The control terminal of the first transistor 210 is coupled to a first input interface 230a, and the output terminal of the first transistor 210 is coupled to a first output interface 240a. The control terminal of the second transistor 220 is coupled to a second input interface 230b, and the output terminal of the second transistor 220 is coupled to a second output interface 240b. Figure 2 In the example shown, the first transistor 210 is a silicon carbide (SiC) based transistor, while the second transistor 220 is a silicon (Si) based transistor. Specifically, the gate bias voltage supplied to the first transistor 210 can be between -6 volts and -4 volts to ensure excellent performance, such as lower parasitic capacitance, higher efficiency, and better linearity. The package carrier of this transistor exhibits superior performance compared to, for example… Figure 1A The encapsulation carrier 110 and shown Figure 1B The encapsulation carrier 120 shown.

[0038] For example, such as Figure 2As shown, the bias circuit includes a first bias circuit 250, a second bias circuit 260, and a third bias circuit 270. These bias circuits can be constructed from suitable electrical components such as capacitors and transmission lines. Figure 2 In the example, one end of the first bias circuit 250 is connected to the external DC power supply port 280a, and the other end is connected to the control terminal (gate in this example) of the first transistor 210, thereby providing a gate bias voltage for the first transistor 210; one end of the second bias circuit 260 is connected to the external DC power supply port 280b, and the other end is connected to the control terminal of the second transistor 220, thereby providing a gate bias voltage for the second transistor 220; one end of the third bias circuit 270 is connected to the external DC power supply port 280c, and the other two ends are respectively connected to the output terminals (drains in this example) of the first transistor 210 and the second transistor 220, thereby providing corresponding drain bias voltages for the first transistor 210 and the second transistor 220.

[0039] In some embodiments, the third bias circuit 270 may include different sub-circuits to facilitate more precise application of the bias voltage and further improve performance. For example... Figure 3 As shown, with Figure 2 Similarly, the package carrier 300 includes: a first input interface 330a and a second input interface 330b, a first output interface 340a and a second output interface 340b, a substrate, a first transistor 310, a second transistor 320, and bias circuitry (350, 360, 370a, 370b). The first transistor 310 is a silicon carbide (SiC) based transistor, while the second transistor 320 is a silicon (Si) based transistor. Figure 3 As shown, the bias circuit includes a first bias circuit 350, a second bias circuit 360, and a third bias circuit. The third bias circuit includes a first sub-bias circuit 370a and a second sub-bias circuit 370b. These bias circuits can be constructed from suitable electrical components such as capacitors and transmission lines. Figure 3In the example, one end of the first bias circuit 350 is connected to the external DC power supply port 380a, and the other end is connected to the control terminal (gate in this example) of the first transistor 310, thereby providing a gate bias voltage for the first transistor 310; one end of the second bias circuit 360 is connected to the external DC power supply port 380b, and the other end is connected to the control terminal of the second transistor 320, thereby providing a gate bias voltage for the second transistor 320; one end of the first sub-bias circuit 370a is connected to the external DC power supply port 380c, and the other end is connected to the output terminal (drain in this example) of the first transistor 310, thereby providing a corresponding drain bias voltage for the first transistor 310; one end of the second sub-bias circuit 370b is connected to the external DC power supply port 380d, and the other end is connected to the output terminal (drain in this example) of the second transistor 320, thereby providing a corresponding drain bias voltage for the second transistor 320. Specifically, in order to obtain a package carrier 300 with excellent performance, the gate voltage provided to the first transistor 310 can be between -6V and -4V, and the gate voltage provided to the second transistor 320 can be between 0V and 3V.

[0040] At least for the sake of process convenience, in some embodiments, Figure 2 The packaging carrier 200 shown Figure 3 The illustrated packaging carrier 300 may further include a sub-package structure located on the substrate, and the sub-package structure includes a first transistor and a second transistor. For example, as shown... Figure 4 As shown, the packaging carrier 400 includes a sub-packaging structure 490 located on the substrate of the packaging carrier 400, and the first transistor 410 and the second transistor 420 of the packaging carrier 400 are both packaged in the sub-packaging structure 490. The control terminal of the first transistor 410 is coupled to the first input node 490a of the sub-packaging structure 490, the first input node 490a is coupled to the first input interface 430a of the packaging carrier 400, the output terminal of the first transistor 410 is coupled to the first output node 490b of the sub-packaging structure 490, and the first output node 490b is coupled to the first output interface 440a of the packaging carrier 400. In addition, the control terminal of the second transistor 420 is coupled to the second input node 490c of the sub-packaging structure 490, the second input node 490c is coupled to the second input interface 430b of the packaging carrier 400, the output terminal of the second transistor 420 is coupled to the second output node 490d of the sub-packaging structure 490, and the second output node 490d is coupled to the second output interface 440b of the packaging carrier 400.

[0041] exist Figure 4 In the example shown, the first transistor 410 is a silicon carbide (SiC) based transistor, and the second transistor 420 is a silicon (Si) based transistor. Figure 4The bias circuit shown is Figure 2 Similarly, it includes a first bias circuit 450, a second bias circuit 460, and a third bias circuit 470. These bias circuits can be constructed from suitable electrical components such as capacitors, transmission lines, etc. Figure 4 In the example, one end of the first bias circuit 450 is connected to the external DC power supply port 480a, and the other end is connected to the control terminal (gate in this example) of the first transistor 410, thereby providing a gate bias voltage for the first transistor 410; one end of the second bias circuit 460 is connected to the external DC power supply port 480b, and the other end is connected to the control terminal of the second transistor 420, thereby providing a gate bias voltage for the second transistor 420; one end of the third bias circuit 470 is connected to the external DC power supply port 480c, and the other two ends are respectively connected to the output terminals (drains in this example) of the first transistor 410 and the second transistor 420, thereby providing corresponding drain bias voltages for the first transistor 410 and the second transistor 420. It should be noted that those skilled in the art should understand that... Figure 4 The bias circuit shown can also be used with Figure 3 Instead Figure 2 A similar scheme, namely the third bias circuit 470, can also be composed of two sub-bias circuits, which will not be elaborated here.

[0042] Figure 5 Schematic illustration Figure 4 One implementation of the sub-encapsulation structure 490 in [the code]. For example... Figure 5 As shown, the sub-package structure 500 includes: a protective cover 501 (the material of which can be metal, ceramic, plastic, etc.), which cooperates with the base 503 to encapsulate at least some of the circuit elements in the sub-package structure 500, thereby protecting at least some of the circuit elements in the package cavity. When an appropriate material is selected, the protective cover 501 can also serve as a seal and electromagnetic shield; a cavity periphery material 502 (the material of which can be ceramic, etc.); and a base 503 (the material of which can be diamond, metal, etc.), which is used to carry at least some of the circuit elements in the sub-package structure 500. The base 503 can also provide heat dissipation and grounding loops when appropriate materials are selected; the first transistor 504 has its control terminal electrically connected to the first input node 509 of the subpackage structure 500 via bonding wire 505, and its output terminal electrically connected to the first output node 510 of the subpackage structure 500 via bonding wire; the second transistor 505 has its control terminal electrically connected to the second input node 506 of the subpackage structure 500 via bonding wire 507, and its output terminal electrically connected to the second output node 508 of the subpackage structure 500 via bonding wire.

[0043] Despite Figure 5As not shown, those skilled in the art will understand that the first input node 509 is coupled to the first input interface of the corresponding package carrier, and the second input node 506 is coupled to the second input interface of the corresponding package carrier. Additionally, the first output node 510 may be coupled to the first output interface of the corresponding package carrier, and the second output node 508 may be coupled to the second output interface of the corresponding package carrier.

[0044] In addition, although in Figure 5 The example shows cavity periphery material 502. Those skilled in the art will understand that cavity periphery material 502 can be used to achieve better assembly of protective cover 501 and base 503, but this is not necessary. Alternatively, protective cover 501 can be directly assembled with base 503, for example by mechanical fastening or adhesive bonding.

[0045] Figure 6 Schematic illustration Figure 4 Another implementation of the sub-encapsulation structure 490 in the example. Figure 6 As shown, the sub-package structure 600 includes: a protective cover 601 (the material of which can be metal, ceramic, plastic, etc.), which cooperates with the base 603 to encapsulate at least some of the circuit elements in the sub-package structure 600, thereby protecting at least some of the circuit elements in the package cavity. When an appropriate material is selected, the protective cover 601 can also serve as a seal and electromagnetic shield; a cavity periphery material 602 (the material of which can be ceramic, etc.); and a base 603 (the material of which can be diamond, metal, etc.), which is used to support at least some of the circuit elements in the sub-package structure 600. When an appropriate material is selected, the base 603 can also provide heat dissipation. Thermal and grounding loops; a first transistor 604, whose control terminal is electrically connected to the first input node 610 of the subpackage structure 600 via a bonding wire 605, and whose output terminal is electrically connected to the first capacitor 612 via a bonding wire, and then indirectly coupled to the first output node 611 of the subpackage structure 600 via the first capacitor 612; a second transistor 608, whose control terminal is electrically connected to the second input node 606 of the subpackage structure 600 via a bonding wire 607, and whose output terminal is electrically connected to the second capacitor 613 via a bonding wire, and then indirectly coupled to the second output node 609 of the subpackage structure 600 via the second capacitor 613.

[0046] Despite Figure 6 As not shown, those skilled in the art will understand that the first input node 610 is coupled to the first input interface of the corresponding package carrier, and the second input node 606 is coupled to the second input interface of the corresponding package carrier. Additionally, the first output node 611 may be coupled to the first output interface of the corresponding package carrier, and the second output node 609 may be coupled to the second output interface of the corresponding package carrier.

[0047] In addition, although in Figure 6 The example shows cavity periphery material 602. Those skilled in the art will understand that cavity periphery material 602 can be used to achieve better assembly of protective cover 601 and base 603, but this is not necessary. Alternatively, protective cover 601 can be directly assembled with base 603, for example by mechanical fastening or adhesive bonding.

[0048] In addition, regarding Figure 5 The sub-package structure 500 shown and Figure 6 The dimensions of the various components in the sub-package structure 600 shown are, for example, the lengths (i.e., the long side lengths of their corresponding rectangles) of the protective covers (501, 601) and the base (503, 603) are between 10 mm and 20 mm (e.g., 10 mm, 15.2 mm, 17.4 mm, 20 mm), and the lengths (i.e., the long side lengths of their corresponding rectangles) of the first transistor (504, 604) are between 5 mm and 10 mm (e.g., 5 mm, 6.2 mm, 7.3 mm, 10 mm). This results in a smaller size while providing good heat dissipation performance of the sub-package structure (500, 600), thereby helping to improve the performance of the corresponding package carrier.

[0049] In some embodiments, at least one of the following couplings—between the first input node and the first input interface and the control terminal of the first transistor, the second input node and the second input interface and the control terminal of the second transistor, the first capacitor and the output terminal of the first transistor and the first output node of the subpackage structure, and the second capacitor and the output terminal of the second transistor and the second output node of the subpackage structure—can be implemented by any of the following forms: bonded wire, microstrip line. Figure 6 For example, the coupling between the first input node 610 of the subpackage structure 600 and the control terminal of the first transistor 604 is achieved through bonding wire 605. The coupling between the first capacitor 612 and the output terminal of the first transistor 604 and the first output node 611 of the subpackage structure 600 is also achieved through bonding wire 605. Figure 6 The corresponding bonding lines shown are used for coupling. The coupling between the second input node 606 of the subpackage structure 600 and the control terminal of the second transistor 608 is achieved via bonding line 607. The coupling between the second capacitor 613 and the output terminal of the second transistor 608 and the second output node 609 of the subpackage structure 600 is also achieved via... Figure 6 The corresponding bond wires shown are used for implementation. Alternatively, these couplings can also be implemented using microstrip lines. As yet another example, some of these couplings can be implemented using bond wires, while others can be implemented using microstrip lines.

[0050] Figure 7 The diagram schematically illustrates an exemplary package structure of a Doherty amplifier according to some embodiments of the present invention. Exemplarily, as shown... Figure 7 As shown, the Doherty amplifier may include a carrier board 700 and a package carrier 701 disposed on the carrier board 700. The package carrier 701 may be as described above. Figure 5 The described packaging carrier 500 and the above reference Figure 6 Any of the described package carriers 600, package carrier 701 includes the aforementioned first transistor and second transistor. Carrier board 700 may include a printed circuit board (PCB).

[0051] like Figure 7 As shown, the Doherty amplifier also includes: two RF input interfaces (RF input interface 702 and RF input interface 703), which obtain corresponding RF signals (hereinafter referred to as the first signal and the second signal) from the output of the power divider of the Doherty amplifier (in this example, the power divider is not on the carrier 700), and they are coupled to the first and second input interfaces of the package carrier 701 such that the first input interface and the second input interface are coupled to the output of the power divider; a first transistor is configured to obtain a first amplified signal based on the first signal from the first input interface; a second transistor is configured to obtain a second amplified signal based on the second signal from the second input interface; a heat sink 710; inductors (706, 707); capacitors (704, 705, 708, 709, 711, 712, 714); a transmission line 713; and an RF output interface 715. The transmission line 713 and capacitor 714 form a combining matching network, which combines the first amplified signal generated by the first amplification path where the first transistor is located and the second amplified signal generated by the second amplification path where the second transistor is located and outputs it from the RF output interface 715.

[0052] like Figure 7As shown, the Doherty amplifier also includes DC voltage input terminals (716, 717, 718, 719), which transmit corresponding DC voltages to the control terminals (e.g., gates) and output terminals (e.g., drains) of the first and second transistors, respectively. Exemplarily, the gate bias circuit of the first transistor is formed by components such as capacitor 708 and inductor 706 and is connected to an external DC power supply port 716; the gate bias circuit of the second transistor is formed by components such as capacitor 709 and inductor 707 and is connected to an external DC power supply port 718; the drain bias circuit of the first transistor is formed by components such as capacitor 711 and is connected to an external DC power supply port 717; and the drain bias circuit of the second transistor is formed by components such as capacitor 712 and is connected to an external DC power supply port 719. The first and second output interfaces of the package carrier 701 are electrically connected to the RF output interface 715 via transmission line 713 and capacitor 714.

[0053] Figure 8 The diagram schematically illustrates an exemplary package structure of a Doherty amplifier according to other embodiments of the present invention. Exemplarily, as... Figure 8 As shown, the Doherty amplifier may include a carrier board 800 and a package carrier 801 disposed on the carrier board 800. The package carrier 801 may be as described above. Figure 5 The described packaging carrier 500 and the above reference Figure 6 Any of the described package carriers 600, package carrier 801 includes the aforementioned first transistor and second transistor. The first transistor is configured to obtain a first amplified signal based on a first signal from a first input interface, and the second transistor is configured to obtain a second amplified signal based on a second signal from a second input interface. Carrier board 800 may include a printed circuit board (PCB).

[0054] like Figure 8 As shown, the Doherty amplifier also includes: an RF input interface 802, which is coupled to the input of the power divider 803 of the Doherty amplifier; a heat sink 810; inductors (807, 808); capacitors (804, 805, 806, 809, 811, 813); a transmission line 812; and an RF output interface 814. The transmission line 812 and capacitor 813 form a combining matching network, which combines the first amplified signal generated by the first amplification path where the first transistor is located and the second amplified signal generated by the second amplification path where the second transistor is located, and outputs them from the RF output interface 814.

[0055] like Figure 8As shown, the Doherty amplifier also includes DC voltage input terminals (815, 816, 817), which transmit corresponding DC voltages to the control terminals (e.g., gates) and output terminals (e.g., drains) of the first and second transistors, respectively. Exemplarily, the gate bias circuit of the first transistor is formed by components such as capacitor 806 and inductor 807 and is connected to an external DC power supply port 815; the gate bias circuit of the second transistor is formed by components such as capacitor 809 and inductor 808 and is connected to an external DC power supply port 817; and the drain bias circuit of the first and second transistors is formed by components such as capacitor 811 and is connected to an external DC power supply port 816. The first and second output interfaces of the package carrier 801 are electrically connected to the RF output interface 814 via transmission line 812 and capacitor 813.

[0056] Figure 9 The diagram schematically illustrates an exemplary package structure of a Doherty amplifier according to further embodiments of the present invention. Exemplarily, as shown... Figure 9 As shown, the Doherty amplifier may include a carrier board 900 and a package carrier 901 disposed on the carrier board 900. The package carrier 901 includes the aforementioned first transistor, second transistor, and other corresponding circuit elements. The carrier board 900 may include a printed circuit board (PCB). Exemplarily, the package carrier 901 may be the one described above. Figure 5 The described packaging carrier 500 and the above reference Figure 6 Any of the 600 encapsulation carriers described.

[0057] like Figure 9 As shown, the first and second input interfaces of the package carrier 901 are respectively coupled (via, for example, transmission line 904) to the output of the power divider 903 of the Doherty amplifier. The input of the power divider 903 is coupled to the RF input interface 902 of the Doherty amplifier. A first transistor is configured to obtain a first amplified signal based on a first signal from the first input interface, and a second transistor is configured to obtain a second amplified signal based on a second signal from the second input interface. Transmission line 909 and capacitor 910 form a combining matching network, which is coupled between the first and second output interfaces of the package carrier 901 and the RF output interface 911 of the Doherty amplifier, and combines the first and second amplified signals and outputs them from the RF output interface 911.

[0058] like Figure 9As shown, capacitor 908 and the corresponding transmission line constitute the drain bias circuit of the first and second transistors inside the package carrier 901 and are connected to the external DC power supply port 906, which provides the corresponding drain voltages to these transistors. Additionally, the package carrier 901 is electrically connected to the external DC power supply ports (905, 907) via corresponding transmission lines, which provide the corresponding gate bias voltages to the first and second transistors inside the package carrier 901.

[0059] It should be noted that, although the above references, for example Figure 7-9 In the described embodiments, the package carrier includes only two input interfaces and corresponding two output interfaces (a first input interface, a second input interface, a first output interface, and a second output interface). Those skilled in the art will understand that when applied to a Doherty amplifier, the package carrier can also include more input interfaces and corresponding output interfaces to achieve more channels (e.g., three, four, or even more) of Doherty amplifiers. For example, taking a three-channel Doherty amplifier as an example, the package carrier further includes: a third input interface and a third output interface, wherein the third input interface is coupled to the output of the power divider, and the third output interface is coupled to the combining matching network; a third transistor, wherein the third transistor is located on the substrate, the control terminal of the third transistor is coupled to the third input interface, the output terminal of the third transistor is coupled to the third output interface, and wherein the third transistor is configured to obtain a third amplified signal based on a third signal from the third input interface. Accordingly, the combining matching network combines the first amplified signal, the second amplified signal, and the third amplified signal and outputs them from the RF output interface of the Doherty amplifier.

[0060] Figure 10 The diagram schematically illustrates example performance figures of a Doherty amplifier according to some embodiments of the present invention. For example... Figure 10 As shown, the above text is used. Figure 2 The input interface of the package carrier 1000 in the illustrated architecture is connected to the RF input interface of the Doherty amplifier via a power divider to obtain the corresponding RF input. The output interface of the package carrier 1000 is connected to the RF output interface via the power combiner (i.e., combining and matching network) of the Doherty amplifier to achieve the corresponding RF output. Figure 10 It can be seen that the two RF paths of the Doherty amplifier can simultaneously achieve high gain performance, and compared to those based on Figure 1A The Doherty amplifier with the shown package carrier architecture has a wider bandwidth. Furthermore, compared to amplifiers based on… Figure 1BThe Doherty amplifier with the packaged carrier architecture shown has lower phase distortion (AM-PM), and the overall output signal phase distortion flatness of the system can be kept very small after power combining.

[0061] It will be understood that although the terms "first," "second," etc., may be used herein to describe various devices, elements, components, or parts, these devices, elements, components, or parts should not be limited by these terms. These terms are used only to distinguish one device, element, component, or part from another device, element, component, or part. The terms "connection" or "coupling" as used herein may be either "direct connection" or "indirect connection."

[0062] Although the present invention has been described in conjunction with some embodiments, it is not intended to be limited to the specific forms set forth herein. Rather, the scope of the present invention is limited only by the appended claims. Additionally, although individual features may be included in different claims, these may be advantageously combined, and inclusion in different claims does not imply that such a combination of features is not feasible and / or advantageous. The order of features in the claims does not imply that the features must be in any particular order of their operation. Furthermore, in the claims, the word "comprising" does not exclude other elements, and the terms "a" or "an" do not exclude a plurality. Reference numerals in the claims are provided only by way of explicit example and should not be construed as limiting the scope of the claims in any way.

Claims

1. A packaging carrier, comprising: First input interface and second input interface; First output interface and second output interface; Substrate; A first transistor, wherein the first transistor is located on the substrate, the control terminal of the first transistor is coupled to the first input interface, and the output terminal of the first transistor is coupled to the first output interface; The second transistor is located on the substrate, the control terminal of the second transistor is coupled to the second input interface, the output terminal of the second transistor is coupled to the second output interface, and the first transistor includes a silicon carbide-based transistor, and the second transistor includes a silicon-based transistor. as well as A bias circuit is configured to provide corresponding bias voltages to the first transistor and the second transistor.

2. The packaging carrier according to claim 1, wherein the packaging carrier further comprises a sub-packaging structure, the sub-packaging structure being located on the substrate and comprising the first transistor and the second transistor, and wherein the sub-packaging structure further comprises: A first input node and a first output node, wherein the first input node is coupled to the first input interface and the control terminal of the first transistor, and the first output node is coupled to the output terminal of the first transistor and the first output interface; A second input node and a second output node, wherein the second input node is coupled to the second input interface and the control terminal of the second transistor, and the second output node is coupled to the output terminal of the second transistor and the second output interface.

3. The packaging carrier according to claim 2, wherein the sub-packaging structure further comprises: A base that supports at least a portion of the circuit elements in the sub-package structure; A protective cover that mates with the base to enclose at least a portion of the circuit elements in the sub-package structure.

4. The packaging carrier according to claim 3, wherein the length of the base and the protective cover is between 10 mm and 20 mm, and wherein the length of the first transistor is between 5 mm and 10 mm.

5. The packaging carrier according to claim 2, wherein the sub-packaging structure further comprises: A first capacitor, wherein one end of the first capacitor is coupled to the output terminal of the first transistor, and the other end is coupled to the first output node of the sub-package structure; The second capacitor, wherein one end of the second capacitor is coupled to the output terminal of the second transistor, and the other end is coupled to the second output node of the sub-package structure.

6. The encapsulation carrier according to claim 5, wherein, The coupling between the first input node and the first input interface and the control terminal of the first transistor, the coupling between the second input node and the second input interface and the control terminal of the second transistor, the coupling between the first capacitor and the output terminal of the first transistor and the first output node of the sub-package structure, and the coupling between the second capacitor and the output terminal of the second transistor and the second output node of the sub-package structure, at least one of the following can be implemented by any of the following forms: bond wire, microstrip line.

7. The packaging carrier according to claim 1, wherein the bias circuit comprises: A first bias circuit is configured to provide a gate bias voltage to the first transistor; A second bias circuit is configured to provide a gate bias voltage to the second transistor; as well as A third bias circuit is configured to provide drain bias voltage to the first transistor and the second transistor.

8. The packaging carrier according to claim 7, wherein the third bias circuit comprises a first sub-bias circuit and a second sub-bias circuit, and wherein: The first sub-bias circuit is configured such that the first transistor provides a drain bias voltage; The second sub-bias circuit is configured to provide a drain bias voltage for the second transistor.

9. The encapsulation carrier according to claim 1, wherein, The gate bias voltage supplied to the first transistor is between -6 volts and -4 volts, and the gate bias voltage supplied to the second transistor is between 0 volts and 3 volts.

10. A Doherty amplifier, comprising: A radio frequency input interface, which is coupled to the input of the power divider of the Doherty amplifier; The package carrier according to any one of claims 1-9, wherein the first input interface and the second input interface of the package carrier are coupled to the output of the power divider, the first transistor is configured to obtain a first amplified signal based on a first signal from the first input interface, and the second transistor is configured to obtain a second amplified signal based on a second signal from the second input interface; A matching network is coupled between the first output interface, the second output interface and the radio frequency output interface of the Doherty amplifier in the package carrier.

11. The Doherty amplifier of claim 10, wherein the packaging carrier further comprises: A third input interface and a third output interface, wherein the third input interface is coupled to the output of the power divider and the third output interface is coupled to the combining matching network; A third transistor, wherein the third transistor is located on the substrate, the control terminal of the third transistor is coupled to the third input interface, the output terminal of the third transistor is coupled to the third output interface, and wherein the third transistor is configured to obtain a third amplified signal based on a third signal from the third input interface.

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