CAN bus fault injection test system based on FPGA
The FPGA-based CAN bus fault injection test system solves the problems of high cost and MCU processing delay in traditional test platforms, achieving low-cost and efficient CAN bus interference testing, and supporting simulation of various interference scenarios and hardware expansion.
Patent Information
- Application Number
- CN202520309576.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2026-02-10
- Estimated Expiration
- 2035-02-25
AI Technical Summary
Traditional CAN bus test platforms are expensive and have limited functionality, making them difficult to expand. MCU solutions suffer from latency and system lag when handling complex interference signals.
An FPGA-based CAN bus fault injection test system is adopted, which includes a digital interference injection module, an analog interference injection module, an FPGA processing module, a CAN interface module, a host computer, and a power supply. The FPGA processing module realizes hardware parallel processing and supports the simulation and expansion of various interference scenarios.
It reduces the cost of the testing system, improves the processing speed, avoids system delays and lag, and enables flexible hardware function expansion and efficient processing of complex interference signals.
Smart Images
Figure CN223899227U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of automotive testing, specifically to an FPGA-based CAN bus fault injection test system. Background Technology
[0002] During the design phase of automotive electronic controllers, it is necessary to analyze and address potential faults that the controllers may encounter during operation. Since the CAN bus operates in complex industrial and automotive application environments, interference injection testing of the CAN bus physical layer (analog interference) and protocol layer (digital interference) is a key test item for verifying the reliability of the CAN bus. The test requires the acquisition of CAN bus data.
[0003] Traditional CAN bus test platforms mainly use two methods to acquire data:
[0004] (1) Interference is injected using the German Vector VH6501 jammer and its dedicated control software CANoe (refer to the instruction manual). Figure 1 When performing digital interference, the VH6501, in conjunction with its dedicated control software CANoe, interferes with various functional parameters of the CAN bus to achieve channel selection and mode setting, baud rate and data rate setting, and interference count selection. When performing simulated interference, it can also simulate CAN bus short circuits, open circuits, and the resistance effects caused by the cable length. The CAN bus acquires data and completes tests through Vector's hardware interface VN1640. However, the entire Vector toolchain is very expensive, and its closed technology results in fixed hardware module functions, making it difficult to expand module functions.
[0005] (2) MCU (Micro controller Unit) is a microcontroller and a dedicated CAN controller such as SJA1000 to acquire bus data and inject interference. Although it is relatively reasonably priced compared to the interference device VH6501, the serial processing mechanism of MCU may cause delays when processing complex interference signals, and may cause lag or even system crash under high load. Utility Model Content
[0006] The purpose of this invention is to provide an FPGA-based CAN bus fault injection test system that can solve the above-mentioned problems.
[0007] To achieve the above objectives, this utility model proposes an FPGA-based CAN bus fault injection test system, comprising: a digital interference injection module, an analog interference injection module, an FPGA processing module, a CAN interface module, a host computer, and a power supply.
[0008] The digital interference injection module is connected to the FPGA processing module via an interface; the analog interference injection module is connected to the FPGA processing module via the CAN_H network bus and the CAN_L network bus.
[0009] The output of the FPGA processing module is connected to the CAN interface module;
[0010] The host computer and the digital interference injection module are connected via wired communication, and the host computer and the CAN interface module are connected via wired communication.
[0011] The power supply is used to power the digital interference injection module, the analog interference injection module, the FPGA processing module, and the CAN interface module.
[0012] Further configured, the simulated interference injection module includes contact resistor Rs1, contact resistor Rs3, terminating resistor Rs2, disconnection resistor Rs4, disconnection resistor Rs5, load capacitor Cs, CAN_H network bus and CAN_L network bus.
[0013] A further configuration includes a terminating resistor Rs2 between the CAN_H network bus and the CAN_L network bus, and a load capacitor Cs between the CAN_H network bus and the CAN_L network bus.
[0014] A further setting is to configure the CAN_H network bus with a disconnection resistor Rs4.
[0015] A further setting is to configure the CAN_L network bus with a disconnection resistor Rs5.
[0016] A further configuration is made such that a first branch is connected in parallel on the CAN_H network bus, and a contact resistor Rs1 and a double-pole switch SH are connected in series on the first branch.
[0017] A further configuration is made such that a second branch is connected in parallel to the CAN_L network bus, and a contact resistor Rs3 and a double-pole switch SL are connected in series on the second branch.
[0018] Further configured, the double-pole switch SH can be switched to the power supply terminal V or the ground terminal GND, and the double-pole switch SL can be switched to the power supply terminal V or the ground terminal GND.
[0019] The power supply is further configured such that it supplies power to the digital interference injection module, the analog interference injection module, the FPGA processing module, and the CAN interface module via a power conversion module.
[0020] A further feature is that the CAN interface module is connected to the device under test, which is an automotive electronic controller or a real vehicle.
[0021] The beneficial effects of one or more of the above technical solutions:
[0022] (1) Set up a digital interference injection module and an analog interference injection module. The digital interference injection module uses a pre-configured file to parse the CAN bus message bit stream. The FPGA processing module can use the pre-configured file to interfere with various functional parameters of the parsed message bit stream. The host computer sends various forms of interference commands to the FPGA. The analog interference module controls the adjustment of digital potentiometers and capacitors through the FPGA. It supports the simulation of CAN bus short circuit, open circuit, resistance / capacitor adjustment, and physical layer interference scenarios such as cables. Compared with the interference instrument VH6501, the price is significantly reduced. Moreover, the hardware module function can be expanded by changing the circuit structure of the analog interference injection module.
[0023] (2) Compared with the traditional MCU+SJA1000 solution, the processing speed is significantly improved by the hardware parallel capability of FPGA, avoiding the delay and system lag problems when the MCU is processed serially. Attached Figure Description
[0024] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute a limitation thereof.
[0025] Figure 1 A schematic diagram of the existing fault injection test system structure.
[0026] Figure 2 This is a schematic diagram of the structure of this utility model.
[0027] Figure 3 This is a schematic diagram of the simulated interference injection module of this utility model.
[0028] Figure 4 This is a schematic diagram of the digital interference injection module of this utility model.
[0029] Figure 5 This is a schematic diagram of the FPGA processing module of this utility model.
[0030] Figure 6 This is a schematic diagram of the FPGA processing module and digital interference injection pin adapter structure of this utility model.
[0031] In the diagram, 1 is the digital interference injection module; 2 is the analog interference injection module; 3 is the FPGA processing module; 4 is the CAN interface module; 5 is the host computer; 6 is the power supply; 61 is the power conversion module; and 7 is the device under test. Detailed Implementation
[0032] The specific implementation of this embodiment will now be described with reference to the accompanying drawings.
[0033] Reference Figure 2 and Figure 3 A CAN bus fault injection test system based on FPGA, referring to Figure 2 and Figure 3 It includes: digital interference injection module 1, analog interference injection module 2, FPGA processing module 3, CAN interface module 4, host computer 5, and power supply 6.
[0034] The digital interference injection module 1 is connected to the FPGA processing module 3 via an interface; the analog interference injection module 2 is connected to the FPGA processing module 3 via the CAN_H network bus and the CAN_L network bus.
[0035] The output of FPGA processing module 3 is connected to CAN interface module 4;
[0036] The host computer 5 and the digital interference injection module 1 are connected via wired communication, and the host computer 5 and the CAN interface module 4 are connected via wired communication.
[0037] Power supply 6 is used to supply power to digital interference injection module 1, analog interference injection module 2, FPGA processing module 3 and CAN interface module 4.
[0038] The analog interference injection module 2 includes contact resistor Rs1, contact resistor Rs3, terminating resistor Rs2, disconnection resistor Rs4, disconnection resistor Rs5, load capacitor Cs, CAN_H network bus and CAN_L network bus. Rs1 to Rs5 are digital resistance potentiometers (also known as digitally controlled programmable resistors), Cs is a digital capacitance potentiometer, and SH and SL are double-pole switches. The resistance / capacitance values can be set by programming the existing digital potentiometers using an FPGA.
[0039] A terminating resistor Rs 2 is set between the CAN_H network bus and the CAN_L network bus. The CAN_H network bus and the CAN_L network bus can be short-circuited to each other, that is, the digital resistor potentiometer Rs 2 is set to 0Ω, which can control the terminating resistor between CANH and CANL (the digital resistor potentiometer Rs 2 can be set to a certain value).
[0040] A load capacitor Cs is set between the CAN_H network bus and the CAN_L network bus to simulate the parasitic or load capacitance of long cables.
[0041] The CAN_H network bus sets the disconnection resistor Rs4, and the CAN_L network bus sets the disconnection resistor Rs5. By changing the resistance, the resistance of the cable and the disconnection situation are simulated. That is, the digital resistance potentiometers Rs4 / Rs5 are set to a certain resistance value.
[0042] The first branch of the CAN_H network bus is set in parallel, and the contact resistor Rs1 and the double-pole switch SH are set in series on the first branch.
[0043] The CAN_L network bus is connected in parallel with a second branch. A contact resistor Rs3 and a double-pole switch SL are connected in series on the second branch. The contact resistors Rs1 and Rs3 are used to simulate the contact resistance between the bus and the interference voltage (internal or external).
[0044] Double-pole switch SH can be switched to either power supply terminal V or ground terminal GND, and double-pole switch SL can also be switched to either power supply terminal V or ground terminal GND; double-pole switches SH and SL can be individually short-circuited to ground by setting the digital resistance potentiometer Rs 1 / Rs 3 to 0Ω and switching SH / SL to GND; double-pole switches SH and SL can be used to test interference voltage by setting the digital resistance potentiometer Rs 1 / Rs 3 to 0Ω and switching SH / SL to V.
[0045] Power supply 6 supplies power to digital interference injection module 1, analog interference injection module 2, FPGA processing module 3 and CAN interface module 4 through power conversion module 61. The CAN transceiver model is ADM3050E. The FPGA processing module 3 is an existing chip, using product model XC7A35T-2CSG324I. The CAN interface module 4 is an existing module, using a combination of a 2-channel isolator and a CAN transceiver, product model ADM3050EBRI Z. The host computer uses existing conventional host computer equipment.
[0046] The CAN interface module 4 connects to the device under test 7, which is an automotive electronic controller or a real car.
[0047] The digital interference injection module 1 is an existing communication board, capable of parameter configuration and CAN bus message parsing via a pre-configured C++ control program. The interference is then processed by the host computer through the FPGA processing module 3 (see reference). Figure 5 RS422_TXD1 and RS422_RXD1 interface and communication board (refer to) Figure 4 ) Connected via UART-RXD1 or UART-RXD2 interface, FPGA processing module 3 connects via... Figure 6 The pin-adapter structure connects to the communication board.
[0048] The principle of injection testing is as follows:
[0049] First, digital interference is performed to set the baud rate and data rate: the host computer data is transmitted to the CAN interface module 4 via the FPGA processing module 3 and the digital interference injection module 1 to complete the parameter adjustment. Specifically, the digital interference injection module uses a pre-configured file to parse the CAN bus message bit stream, and the FPGA processing module can use the pre-configured file to interfere with various functional parameters of the parsed message bit stream. The connection is made via wired communication. The above-mentioned configured file can be implemented using existing technology. This embodiment protects the hardware structure of the system.
[0050] After digital interference test injection, the test feedback for the interference message in the digital interference is as follows: the CAN interface module feeds back to the host computer through the communication pin, and the host computer displays the interfered part of the message. The displayed message is considered to be consistent with the applied interference command.
[0051] Next, simulated interference injection is performed. The simulated interference function is divided into the following items (if a short circuit / open circuit is required, the digital potentiometer should be set to 0 / infinity), refer to... Figure 3 :
[0052] 1. CANH and CANL can be short-circuited to ground individually, that is, the digital resistance potentiometer Rs 1 or Rs 3 is set to 0Ω, and the switch SH or SL is turned to GND, which is used to simulate the contact resistance between the bus and the interference voltage.
[0053] 2. CANH and CANL can be used to test interference voltage. Set the digital resistance potentiometer Rs 1 / Rs 3 to 0Ω and switch SH or SL to V to simulate the contact resistance between the bus and the interference voltage.
[0054] 3. CANH and CANL can simulate the resistance and breakage of cables by setting the digital resistance potentiometers Rs4 / Rs5 to a certain resistance value to simulate the resistance and breakage of cables.
[0055] 4. CANH and CANL can be short-circuited to each other, that is, the digital resistance potentiometer Rs2 is set to 0Ω, thereby adjusting the terminating resistance on the bus;
[0056] 5. The terminating resistor between CANH and CANL can be controlled. The digital resistance potentiometer Rs2 can be set to a certain value, and the terminating resistor on the bus can be adjusted.
[0057] 6. The capacitance between CANH and CANL can be controlled. The digital capacitance potentiometer Cs can be set to a certain value to simulate the parasitic or load capacitance of long cables.
[0058] The simulated interference test is conducted by connecting an existing oscilloscope to the CAN bus, performing short-circuit and open-circuit operations, or adjusting resistors and capacitors. The oscilloscope's level signal waveform is then observed to determine if the level signal status is good. For example, as the capacitance increases, the falling edge time of the level signal waveform gradually increases, and the bit width gradually decreases, indicating that the capacitive reactance of the wires will seriously affect the CAN bus signal transmission of the device under test.
[0059] Although the specific embodiments of the present utility model have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present utility model. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solution of the present utility model are still within the scope of protection of the present utility model.
Claims
1. A CAN bus fault injection test system based on FPGA, characterized in that, include: Digital interference injection module, analog interference injection module, FPGA processing module, CAN interface module, host computer and power supply; The digital interference injection module is connected to the FPGA processing module via an interface; the analog interference injection module is connected to the FPGA processing module via the CAN_H network bus and the CAN_L network bus. The output of the FPGA processing module is connected to the CAN interface module; The host computer and the digital interference injection module are connected via wired communication, and the host computer and the CAN interface module are connected via wired communication. The power supply is used to power the digital interference injection module, the analog interference injection module, the FPGA processing module, and the CAN interface module.
2. The FPGA-based CAN bus fault injection test system according to claim 1, characterized in that, The simulated interference injection module includes contact resistor Rs1, contact resistor Rs3, terminating resistor Rs2, disconnection resistor Rs4, disconnection resistor Rs5, load capacitor Cs, CAN_H network bus, and CAN_L network bus.
3. The FPGA-based CAN bus fault injection test system according to claim 2, characterized in that, A terminating resistor Rs2 is provided between the CAN_H network bus and the CAN_L network bus, and a load capacitor Cs is provided between the CAN_H network bus and the CAN_L network bus.
4. The FPGA-based CAN bus fault injection test system according to claim 2, characterized in that, The CAN_H network bus is equipped with a disconnection resistor Rs4.
5. The FPGA-based CAN bus fault injection test system according to claim 2, characterized in that, The CAN_L network bus is equipped with a disconnection resistor Rs5.
6. The FPGA-based CAN bus fault injection test system according to claim 1, characterized in that, The CAN_H network bus is configured with a first branch line in parallel, and a contact resistor Rs1 and a double-pole switch SH are configured in series on the first branch line.
7. The FPGA-based CAN bus fault injection test system according to claim 6, characterized in that, The CAN_L network bus is configured with a second branch in parallel, and a contact resistor Rs3 and a double-pole switch SL are connected in series on the second branch.
8. The FPGA-based CAN bus fault injection test system according to claim 7, characterized in that, A double-pole switch SH can be switched to either the power supply terminal V or the ground terminal GND, and a double-pole switch SL can be switched to either the power supply terminal V or the ground terminal GND.
9. The FPGA-based CAN bus fault injection test system according to claim 1, characterized in that, The power supply provides power to the digital interference injection module, analog interference injection module, FPGA processing module, and CAN interface module through a power conversion module.
10. The FPGA-based CAN bus fault injection test system according to claim 1, characterized in that, The CAN interface module connects to the device under test, which is an automotive electronic controller or a real vehicle.