Electronic circuit adopting intermittent charging and discharging

Abstract

The utility model discloses an electronic circuit adopting intermittent charging and discharging. The electronic circuit comprises a control circuit, a power level circuit and a charging circuit. The control circuit generates a charging control signal. The power stage circuit receives a voltage signal. The charging circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the charging control signal. The control circuit controls the charging circuit to charge the power level circuit for multiple times in a plurality of working periods of a plurality of continuous pulse waves of the charging control signal so as to generate a plurality of charging sections of a rising wave band of the voltage signal. The control circuit controls the charging circuit to stop charging the power level circuit in a plurality of non-working periods of a plurality of continuous pulse waves of the charging control signal, so that the voltage signal generates a charging stopping horizontal line segment or an elevator discharging segment between two of a plurality of elevator charging segments. According to the utility model, intermittent control is adopted for charging and discharging of the power level circuit, so that the control accuracy of the electronic circuit adopting intermittent charging and discharging is greatly improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to charge and discharge, especially, an intermittent charge and discharge electronic circuit. BACKGROUND

[0002] In recent years, due to the evolution of technology and the rise of environmental awareness, people's requirements for efficiency and electromagnetic interference are getting higher and higher, whether it is communication application or energy conversion, the control of switch plays a very important role. At the same time, the cost of materials and labor is rising, reducing product design area and improving technical quality has always been the breakthrough goal of researchers. SUMMARY

[0003] In view of the deficiency of prior art, the utility model provides an electronic circuit of intermittent charge and discharge. The electronic circuit of intermittent charge and discharge includes control circuit, power stage circuit and charging circuit. The control circuit generates charging control signal. The power stage circuit receives voltage signal. The charging circuit is coupled with the power stage circuit and the control circuit, and is controlled by the control circuit according to the charging control signal. In the first period, the control circuit controls the charging circuit to charge the power stage circuit for multiple times in multiple working periods of continuous multiple pulses of the charging control signal, to generate multiple first charging steps of rising wave segment of the voltage signal respectively. In the first period, the control circuit controls the charging circuit to stop charging the power stage circuit in multiple non-working periods of continuous multiple pulses of the charging control signal, so that the voltage signal generates a stop charging horizontal line segment or a first discharging step between two of the multiple first charging steps.

[0004] In some embodiments, the control circuit also generates discharging control signal, and the electronic circuit of intermittent charge and discharge also includes discharging circuit. The discharging circuit is coupled with the power stage circuit and the control circuit, and is controlled by the control circuit according to the discharging control signal. In the second period after the first period, the control circuit controls the charging circuit to discharge the power stage circuit for multiple times in multiple working periods of continuous multiple pulses of the discharging control signal, to generate multiple second discharging steps of falling wave segment in the voltage signal respectively. In the second period, the control circuit controls the discharging circuit to stop discharging the power stage circuit in multiple non-working periods of continuous multiple pulses of the discharging control signal, so that the voltage signal generates a stop discharging horizontal line segment or a second charging step between every two of the multiple second discharging steps.

[0005] In some embodiments, the discharging circuit includes a discharging side current source circuit and a discharging switch. The discharging side current source circuit is coupled to the power stage circuit. A first terminal of the discharging switch is coupled to the discharging side current source circuit, a second terminal of the discharging switch is coupled to a ground terminal, and a control terminal of the discharging switch is coupled to the control circuit to receive the discharging control signal. When the discharging switch is turned on according to the discharging control signal, the discharging side current source circuit provides a discharging current through the discharging switch toward the ground terminal to discharge the power stage circuit.

[0006] In some embodiments, the power stage circuit includes a first capacitor and a power transistor. A first terminal of the first capacitor is coupled to the charging circuit and the discharging circuit at an input terminal of the power stage circuit, and a second terminal of the first capacitor is coupled to a ground terminal. A first terminal of the power transistor is coupled to a first power supply voltage, a second terminal of the power transistor is coupled to the ground terminal, and a control terminal of the power transistor is coupled to the input terminal. The voltage signal is generated at the input terminal.

[0007] In some embodiments, the charging circuit includes a charging side current source circuit and a charging switch. A first terminal of the charging switch is coupled to the charging side current source circuit, a second terminal of the charging switch is coupled to the power stage circuit, and a control terminal of the charging switch is coupled to the control circuit to receive the charging control signal. When the charging switch is turned on according to the charging control signal, the charging side current source circuit provides a charging current through the charging switch to the power stage circuit to charge the power stage circuit.

[0008] In some embodiments, the control circuit includes a first comparator and an output circuit. A first input terminal of the first comparator receives a first reference voltage signal, a second input terminal of the first comparator receives a state signal, and the first comparator compares the first reference voltage signal and the state signal to generate a switching signal at an output terminal of the first comparator, wherein the state signal represents a change state of a voltage difference between the control terminal and the second terminal of the power transistor. The output circuit receives the switching signal and outputs the switching signal as the charging control signal or the discharging control signal.

[0009] In some embodiments, the control circuit further includes a sensing comparison circuit, a decision circuit, and a signal generation circuit. The sensing comparison circuit receives a sensing voltage signal, is configured to compare the sensing voltage signal with a plurality of second reference voltages to output a plurality of comparison signals, wherein the sensing voltage signal represents the voltage difference of the power transistor. The decision circuit receives a plurality of the comparison signals, is configured to determine, according to a plurality of the comparison signals, a time difference between a time when the sensing voltage signal reaches each of the second reference voltages and a time threshold, and to generate a trigger signal according to the time difference. The signal generation circuit receives the trigger signal and generates the state signal, is configured to control a level of the state signal according to the trigger signal.

[0010] In some embodiments, the sensing comparison circuit includes a sensing circuit, a plurality of second comparators, and a plurality of reference resistors. The sensing circuit is configured to sense the voltage difference of the power transistor to output the sensing voltage signal. A first input terminal of each of the second comparators is coupled to the sensing circuit to receive the sensing voltage signal, second input terminals of the plurality of the second comparators are respectively coupled to a plurality of the second reference voltages, and a plurality of output terminals of the plurality of the second comparators respectively output a plurality of the comparison signals. The plurality of the reference resistors are coupled in series between a second supply voltage and the ground terminal. The second supply voltage serves as one of the second reference voltages. The plurality of the reference resistors include a first reference resistor and a second reference resistor, and a voltage at a common node between the first reference resistor and the second reference resistor serves as another one of the second reference voltages.

[0011] In some embodiments, the signal generation circuit includes a first switch, an input current source, an input capacitor, and a second switch. A first terminal of the first switch is coupled to a second input terminal of the first comparator at a first node, and a control terminal of the first switch receives the trigger signal. A first terminal of the input current source is coupled to a second terminal of the first switch, and a second terminal of the input current source is coupled to the ground terminal, wherein the input current source circuit provides a current to the first node through the first switch when the first switch is turned on according to the trigger signal. A first terminal of the input capacitor is coupled to the first node, and a second terminal of the input capacitor is coupled to the ground terminal, wherein the state signal is generated at the first node. A first terminal of the second switch is coupled to the first node, and a second terminal of the second switch is coupled to the ground terminal. The decision circuit generates a reset signal, and a control terminal of the second switch receives the reset signal. The decision circuit enables the reset signal to turn on the second switch every interval time equal to the time threshold.

[0012] In some embodiments, the on and off states of the power transistor of the power stage circuit are controlled by the voltage signal, the indication signal represents the on and off states of the power transistor, and the control circuit further includes a transition detection circuit. The transition detection circuit receives the indication signal, is configured to detect rising and falling edges of the indication signal to output a transition detection signal. Whenever the transition detection circuit detects the rising edge of the indication signal, the transition detection circuit outputs the transition detection signal to control the output circuit to output the switching signal as the charging control signal. Whenever the transition detection circuit detects the falling edge of the indication signal, the transition detection circuit outputs the transition detection signal to control the output circuit to output the switching signal as the discharging control signal. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A block diagram of an electronic circuit using intermittent charging of a first embodiment of the present application.

[0014] Figure 2 A step flow chart of an intermittent charging method of the first embodiment of the present application.

[0015] Figure 3 A block diagram of an electronic circuit using intermittent charging and discharging of a second embodiment of the present application.

[0016] Figure 4 A step flow chart of an intermittent discharging method of the second embodiment of the present application.

[0017] Figure 5 A circuit diagram of an electronic circuit using intermittent charging and discharging of a third embodiment of the present application.

[0018] Figures 6-11 Waveform diagrams of main signals of electronic circuits of the fourth to ninth embodiments of the present application.

[0019] Figure 12 A circuit diagram of a control circuit of an electronic circuit using intermittent charging and discharging of a tenth embodiment of the present application.

[0020] Figure 13 Waveform diagrams of a charging control signal and other main signals of an electronic circuit of the tenth embodiment of the present application.

[0021] Figure 14 Waveform diagrams of a discharging control signal and other main signals of an electronic circuit of the tenth embodiment of the present application.

[0022] Figure 15 A circuit diagram of an electronic circuit using intermittent charging and discharging of an eleventh embodiment of the present application.

[0023] Figure 16 Waveform diagram of main signals of the electronic circuit of the twelfth embodiment of the present application. DETAILED DESCRIPTION

[0024] The advantages and effects of the present application can be understood by the contents disclosed in the present specification. The present application can be implemented or applied by other different embodiments, and each detail in the present specification can be modified or changed based on different viewpoints and applications without departing from the concept of the present application.

[0025] Figure 1 Block diagram of the electronic circuit of the first embodiment of the present application using intermittent charging, Figure 2 Step flow chart of the intermittent charging method of the first embodiment of the present application. Please refer to Figure 1 and Figure 2 The intermittent charging method of the present application includes steps S11-S15 of intermittent charging as shown in Figure 2 , which can be executed by the electronic circuit of the present application using intermittent charging (for example, the electronic circuit 1 of Figure 1 ). As shown in Figure 1 , the electronic circuit 1 includes a control circuit 10, a charging circuit 11, and a power stage circuit 12. The control circuit 10 generates a charging control signal SCH. The charging circuit 11 is coupled to the control circuit 10 to receive the charging control signal SCH. In addition, the charging circuit 11 is also coupled to the power stage circuit 12. The control circuit 10 operates in a plurality of switching periods to control the power stage circuit 12 through the charging control signal SCH. The operation of the electronic circuit 1 of the present application in each switching period will be described below by Figure 1 and Figure 2 .

[0026] In step S11, the electronic circuit 1 enters a first period (for example, a charging period P10 in Figure 6 ) in the switching period, and executes steps S12-S15 in the first period. In the first period, the charging control signal SCH has a plurality of pulse waves (i.e., has at least two pulse waves, for example, pulse waves P11-P12 in Figure 6 ), and each pulse wave includes a duty-on period (for example, duty-on periods DN11-DN12 in Figure 6 ) and a duty-off period (for example, duty-off periods DFO11-DFO12 in Figure 6During the non-operating period (DF11-DF12), in step S12, the control circuit 10 controls the charging circuit 11 to perform the first charge on the power stage circuit 12 via the charging control signal SCH. Specifically, in step S12, during the first operating period of the charging control signal SCH (e.g., ...), Figure 6 During the operation of pulse P11 (DN11), control circuit 10 controls charging circuit 11 to perform the first charge on power stage circuit 12 to generate a voltage signal (e.g., Figure 5 The first charging step of the rising wave of the gate capacitor voltage signal VCg (e.g., the first charging step of the rising wave of the gate capacitor voltage signal VCg). Figure 6 The charging stage SU11). In this embodiment, the voltage signal is received by the power stage circuit 12. In step S13, the control circuit 10 controls the charging circuit 11 to stop the first charging of the power stage circuit 12 via the charging control signal SCH. Specifically, in step S13, during the first non-operating period after the first operating period of the charging control signal SCH (e.g., ... Figure 6 During the non-operating period (DF11) of pulse P11, control circuit 10 controls charging circuit 11 to stop the first charging of power stage circuit 12, causing the voltage signal to generate the first stop charging horizontal segment (e.g., after the first charging step) Figure 6 (The horizontal line segment SH11 is the one where charging has stopped).

[0027] Next, in step S14, during the second operating period after the first non-operating period of the charging control signal SCH (e.g., Figure 6 During the operation of pulse P12 (DN12), control circuit 10 controls charging circuit 11 to perform a second charge on power stage circuit 12, thereby generating the second charging stage (e.g., the rising wave of the aforementioned voltage signal) of the second charging phase. Figure 6 The charging stage SU12). Then, in step S15, during the second non-operating period after the second operating period of the continuing charging control signal SCH (e.g., Figure 6 During the non-operating period of pulse P12 (DF12), control circuit 10 controls charging circuit 11 to stop the second charging of power stage circuit 12, causing the voltage signal to generate a second stop charging horizontal segment (e.g., after the second charging step) after the second charging step. Figure 6 (The horizontal line segment SH12 that stops charging).

[0028] In the above embodiments, the intermittent charging method of the present invention is illustrated using the first and second operating periods and the first and second non-operating periods of the charging control signal SCH in the first period as examples (i.e., using the charging control signal SCH having two continuous pulses as an example). When the charging control signal SCH in the first period includes three (e.g., Figure 6pulse P11~P13) or more than three consecutive pulses, the electronic circuit 1 can perform operations similar to steps S12 and S13 (and / or steps S14 and S15) after step S15 to continue performing at least one charging operation and at least one stopping charging operation on the power stage circuit 12. That is, in the intermittent charging method of the present application, after charging the power stage circuit 12 for a period of time, the charging of the power stage circuit 12 is stopped during the rest period to achieve intermittent / multi-stage charging of the power stage circuit 12.

[0029] The conventional charging method is to use one-time continuous charging to charge the voltage of the power stage circuit from the valley level or the initial low level directly to the peak level or the preset high level. However, the charging method of the present application for the power stage circuit 12 is to use intermittent / multi-stage charging to charge the voltage signal of the power stage circuit 12 to different voltage levels respectively in multiple charging times, to increase the voltage signal of the power stage circuit 12 in stages until it finally rises to the peak level or the preset high level. Compared with the conventional charging method, the intermittent charging method of the present application can set the charging time length and the charging rest time length (i.e. the time length of stopping charging) of each stage according to the application requirements, which can greatly improve the accuracy of charging control to more flexibly control the charging state of the power stage circuit 12.

[0030] Figure 3 is a block diagram of an electronic circuit using intermittent charging and discharging of the second embodiment of the present application, Figure 4 is a step flow chart of an intermittent discharging method of the second embodiment of the present application. As shown in Figure 4 , the intermittent discharging method of the present application includes steps S21~S25. As shown in Figure 3 , in the second embodiment, the electronic circuit 3 using intermittent charging and discharging includes a control circuit 10, a charging circuit 11, a power stage circuit 12, and a discharging circuit 13. Steps S21~S25 can be performed by the control circuit 10, the power stage circuit 12, and the discharging circuit 13 of the electronic circuit 3. Referring to Figure 3 , the control circuit 10 generates a discharging control signal SDG in addition to the charging control signal SCH. The discharging circuit 13 is coupled to the control circuit 10 to receive the discharging control signal SDG. In addition, the discharging circuit 13 is also coupled to the power stage circuit 12. The control circuit 10 controls the power stage circuit 12 through the charging control signal SCH and the discharging control signal SDG in multiple switching periods. The operation of the electronic circuit 3 of the present application in the switching period will be described below by Figure 3 and Figure 4 .

[0031] In some embodiments, steps S21~S25 are consecutive toFigure 2 the steps Sll-Sl 5 (in Figure 4 Fig. 6) after the intermittent charging steps Sll-Sl 5 (in Figure 3 Fig. 6) are represented by dashed boxes) are made as steps of the intermittent charge-discharge method of the present application. The intermittent charge-discharge method of the present application is then performed by the electronic circuit (e.g. the electronic circuit 3 of Figure 5 Fig. 1, the electronic circuit 5 of Figure 15 Fig. 2, or the electronic circuit 15 of Fig. 3) of the present application which employs the intermittent charge-discharge method.

[0032] Figure 3 Referring to Figure 4 Figs. 1-3, in step S21, the electronic circuit 3 enters the second period (e.g. the discharge period P30 of Figure 6 Fig. 1) of the switching period and performs steps S22-S25 in the second period. In the second period, the discharge control signal SDG has a plurality of consecutive pulses (i.e. has at least two pulses, e.g. the pulses P21-P22 of Figure 6 Fig. 1) and each pulse includes an active period (e.g. the active periods DN21-DN22 of Figure 6 Fig. 1) and an inactive period (e.g. the inactive periods DF21-DF22 of Figure 6 Fig. 1). In the embodiment where steps S21-S25 are subsequent to steps Sll-Sl 5, the above-mentioned second period occurs after the first period in the time axis.

[0033] In step S22, the control circuit 10 controls the discharge circuit 13 to perform a first discharge of the power stage circuit 12 via the discharge control signal SDG. In detail, in step S22, the control circuit 10 controls the discharge circuit 13 to perform a first discharge of the power stage circuit 12 to generate a first discharge ramp (e.g. the discharge ramp SD21 of Figure 6 Fig. 1) of the falling section of the voltage signal in the first active period (e.g. the active period DN21 of the pulse P21 of Figure 6 Fig. 1). In step S23, the control circuit 10 controls the discharge circuit 13 to stop the above-mentioned first discharge of the power stage circuit 12 via the discharge control signal SDG. In detail, in step S23, the control circuit 10 controls the discharge circuit 13 to stop the above-mentioned first discharge of the power stage circuit 12 to generate a first stop discharge horizontal section (e.g. the stop discharge horizontal section SH21 of Figure 6 Fig. 1) of the voltage signal in the first inactive period (e.g. the inactive period DF21 of the pulse P21 of Figure 6 Fig. 1) which is subsequent to the first active period of the discharge control signal SDG.

[0034] Then, in step S24, during a second active period (e.g., active period DN22 of pulse P22) following the first inactive period of the discharge control signal SDG, the control circuit 10 controls the discharge circuit 13 to discharge the power stage circuit 12 a second time to generate a second discharge ramp (e.g., discharge ramp SD22) of the falling section of the voltage signal. Figure 6 Then, in step S24, during a second active period (e.g., active period DN22 of pulse P22) following the first inactive period of the discharge control signal SDG, the control circuit 10 controls the discharge circuit 13 to discharge the power stage circuit 12 a second time to generate a second discharge ramp (e.g., discharge ramp SD22) of the falling section of the voltage signal. Figure 6 Then, in step S24, during a second active period (e.g., active period DN22 of pulse P22) following the first inactive period of the discharge control signal SDG, the control circuit 10 controls the discharge circuit 13 to discharge the power stage circuit 12 a second time to generate a second discharge ramp (e.g., discharge ramp SD22) of the falling section of the voltage signal. Figure 6 Then, in step S24, during a second active period (e.g., active period DN22 of pulse P22) following the first inactive period of the discharge control signal SDG, the control circuit 10 controls the discharge circuit 13 to discharge the power stage circuit 12 a second time to generate a second discharge ramp (e.g., discharge ramp SD22) of the falling section of the voltage signal. Figure 6

[0035] In the above embodiment, the intermittent discharge method of the present application is described by taking the first and second active periods and the first and second inactive periods of the discharge control signal SDG in the second period as examples (i.e., by taking the discharge control signal SDG having two consecutive pulses as an example). When the discharge control signal SDG includes three (e.g., pulses P21-P23) or more than three consecutive pulses in the second period, the electronic circuit 3 can perform operations similar to steps S22 and S23 (and / or steps S24 and S25) to continue discharging the power stage circuit 12 at least one more time and stopping discharging the power stage circuit 12 at least one more time after step S25. It is worth noting that in the intermittent discharge method of the present application, the power stage circuit 12 is discharged for a period of time and then stopped from being discharged during a rest period to achieve intermittent / multi-stage discharging of the power stage circuit 12. Figure 6

[0036] Unlike the conventional discharge method that uses one-time continuous discharging to discharge the voltage of the power stage circuit directly from the peak level or the initial high level to the valley level or the preset low level, the discharge method of the present application uses intermittent / multi-stage discharging to discharge the voltage signal of the power stage circuit to different voltage levels respectively in multiple discharging operations to reduce the voltage of the power stage circuit in stages until the voltage is finally reduced to the valley level or the preset low level. Compared with the conventional discharge method, the intermittent discharge method of the present application can set the discharging time length and the discharging rest time length (i.e., the time length of stopping discharging) of each stage according to application requirements, which can greatly improve the accuracy of discharge control to more flexibly control the discharging state of the power stage circuit 12.

[0037] ​​Compared to traditional charging and discharging methods, in the intermittent charging and discharging method of this invention, the control circuit 10 precisely controls the level of the voltage signal by intermittently controlling the enable time of the charging circuit 11 and / or the discharging circuit 13. For example, it precisely controls the speed at which the voltage signal rises from a trough level or an initial low level to a peak level or a preset high level (hereinafter referred to as the voltage signal rise rate), and / or precisely controls the speed at which the voltage signal falls from a peak level or an initial high level to a trough level or a preset low level (hereinafter referred to as the voltage signal fall rate), thereby controlling the switching speed of the power stage circuit 12 to different operating states. The control circuit 10 can select an appropriate intermittent switching strategy to control the rise and / or fall rate of the voltage signal based on the characteristics of the selected power stage circuit 12, such as its conduction curve and parasitic parameters.

[0038] If only a simple setting of the rise and / or fall rate of the aforementioned voltage signal is required, a relatively low-frequency fixed-frequency control can be selected. Fixed-frequency operation results in relatively low noise. Variable-frequency control, on the other hand, is suitable for applications requiring more precise control of the voltage level changes of the aforementioned voltage signal, providing an effective and real-time response through frequency conversion.

[0039] Figure 5 This is a circuit diagram of the electronic circuit employing intermittent charging and discharging according to the third embodiment of this utility model. Figure 5 As shown, the electronic circuit 5 of this invention, employing intermittent charging and discharging, includes a control circuit 10, a charging circuit 11A, a discharging circuit 13A, and a power stage circuit 12A. The control circuit 10 generates a charging control signal SCH and a discharging control signal SDG. Figure 5 In this diagram, the pulse patterns of the charging control signal SCH and the discharging control signal SDG are for illustrative purposes only and are not intended to limit the scope of this invention. (Comparison) Figure 5 and Figure 3 , Figure 5 The charging circuit 11A, discharging circuit 13A, and power stage circuit 12A are respectively Figure 3 The charging circuit 11, discharging circuit 13, and power stage circuit 12 are each implemented in one manner. The charging circuit 11A includes a charging-side current source circuit 110 (hereinafter referred to as "current source circuit 110") and a charging switch SW11. In this embodiment, the current source circuit 110 includes a charging-side current source CU1 (hereinafter referred to as "current source CU1"). The input terminal of the current source CU1 is coupled to the power supply voltage VCC, and its output terminal is coupled to the first terminal of the charging switch SW11. The second terminal of the charging switch SW11 is coupled to the input terminal of the power stage circuit 12A at node N10. The control terminal of the charging switch SW11 is coupled to the control circuit 10 to receive the charging control signal SCH.

[0040] The discharge circuit 13A includes a discharge-side current source circuit 130 (hereinafter referred to as "current source circuit 130") and a discharge switch SW13. In this embodiment, the current source circuit 130 includes a discharge-side current source CU2 (hereinafter referred to as "current source CU2"). An input terminal of the current source CU2 is coupled to an input terminal of the power stage circuit 12A at a node N10, and an output terminal thereof is coupled to a first terminal of the discharge switch SW13. A second terminal of the discharge switch SW13 is coupled to a ground terminal GND. A control terminal of the discharge switch SW13 is coupled to the control circuit 10 to receive a discharge control signal SDG.

[0041] Referring to Figure 5 The power stage circuit 12A mainly includes a capacitor Cg and a power transistor Ml. In addition, depending on the system architecture in which the electronic circuit 5 is applied, the power stage circuit 12A can further include other circuit elements. For example, in the case where the electronic circuit 5 is applied to a system architecture of a Local Interconnect Network (LIN), the power stage circuit 12A can further include an upper diode Dl, a lower diode D2, resistors Rl and R2, and a capacitor Cl. A first terminal of the capacitor Cg and a control terminal of the power transistor Ml are coupled to an input terminal of the power stage circuit 12A at the node N10, and are coupled to a second terminal of the charge switch SWl l and a first terminal of the current source CU2 through this input terminal of the power stage circuit 12A. A second terminal of the capacitor Cg is coupled to the ground terminal GND. A first terminal of the power transistor Ml is coupled to a cathode of the lower diode D2, and a second terminal thereof is coupled to the ground terminal GND. A cathode of the upper diode Dl is coupled to an anode of the lower diode D2. A first terminal of the resistor R2 and a first terminal of the resistor Rl are coupled to a power supply voltage VBAT. A second terminal of the resistor R2 is coupled to an anode of the upper diode Dl. A second terminal of the resistor Rl, a cathode of the upper diode Dl, an anode of the lower diode D2, and a first terminal of the capacitor Cl are coupled to an output terminal LIN of the power stage circuit 12A. A second terminal of the capacitor Cl is coupled to the ground terminal GND. In this embodiment, the power transistor Ml is implemented as an N-type field effect transistor, and thus the control terminal, the first terminal, and the second terminal of the power transistor Ml are a gate, a drain, and a source of the N-type transistor, respectively.

[0042] When the charging switch SW11 is turned on according to the charging control signal SCH, the current source CU1 provides a charging current to flow through the turned-on charging switch SW11 to the capacitor Cg to charge the capacitor Cg, so that the voltage level of the gate capacitor voltage signal VCg at the first end of the capacitor Cg (i.e. the input end of the power stage circuit 12A) gradually increases. When the charging switch SW11 is turned off according to the charging control signal SCH, the current source circuit 110 stops providing the charging current to the capacitor Cg, so that the charging circuit 11A stops charging the capacitor Cg and the voltage level of the gate capacitor voltage signal VCg stops increasing. For example, the charging switch SW11 is turned on during the working period of the charging control signal SCH and is turned off during the non-working period of the charging control signal SCH. The working periods of the successive pulses of the charging control signal SCH can be determined according to the voltage difference between the control end and the second end of the power transistor M1, i.e. according to the actual gate-source voltage (VGS) of the power transistor M1.

[0043] When the discharging switch SW13 is turned on according to the discharging control signal SDG, the current source CU2 provides a discharging current to flow through the turned-on discharging switch SW13 to the ground terminal GND to discharge the capacitor Cg of the power stage circuit 12A, so that the voltage level of the gate capacitor voltage signal VCg gradually decreases. When the discharging switch SW13 is turned off according to the discharging control signal SDG, the current source circuit 130 stops providing the discharging current to the ground terminal GND, so that the discharging circuit 13A stops discharging the capacitor Cg and the voltage level of the gate capacitor voltage signal VCg stops decreasing. For example, the discharging switch SW13 is turned on during the working period of the discharging control signal SDG and is turned off during the non-working period of the discharging control signal SDG. The working periods of the successive pulses of the discharging control signal SDG can be determined according to the actual gate-source voltage (VGS) of the power transistor M1.

[0044] According to the above, the present application intermittently controls the charging switch SW11 to be in the turned-on state, so that the charging current output by the current source CU1 is gradually released to the capacitor Cg in discontinuous periods to increase the voltage at the control end of the power transistor M1 (i.e. the voltage level of the gate capacitor voltage signal VCg), thereby controlling the turn-on speed of the power transistor M1. Similarly, the present application intermittently controls the discharging switch SW13 to be in the turned-on state, so that the capacitor Cg is gradually discharged in discontinuous periods to decrease the voltage at the control end of the power transistor M1, thereby controlling the turn-off speed of the power transistor M1. The power transistor M1 operates according to the gate capacitor voltage signal VCg, thereby controlling the variation (rise or fall) speed of the output voltage at the output end LIN of the power stage circuit 12A.

[0045] Figure 6Waveform diagram of main signals of the electronic circuit of the fourth embodiment of the present application. Figure 6 The pattern of the multiple pulses of the charging control signal SCH is Figure 1 , Figure 3 , Figure 5 and Figure 15 An example of the respective charging control signals SCH, and Figure 6 The pattern of the multiple pulses of the discharging control signal SDG is Figure 3 , Figure 5 and Figure 15 An example of the respective discharging control signals SDG.

[0046] As shown in Figure 6 , the frequency, the on-period, the off-period or the combination thereof of the multiple pulses of the charging control signal SCH can be different from each other, and the frequency, the on-period, the off-period or the combination thereof of the multiple pulses of the discharging control signal SDG can be different from each other, but in this embodiment, only an example is illustrated, and the present application is not limited thereto. The control circuit 10 controls the power stage circuit 12A by the charging control signal SCH and the discharging control signal SDG in multiple switching periods. Referring to Figure 6 , the electronic circuit 5 can operate in the successive periods P10, P20, P30 and P40 in the switching periods. In the following, by the electronic circuit 5 of Figure 5 in combination with the main signals of Figure 6 , the charging and discharging operation of the present application to the power stage circuit in the switching periods is illustrated. In the charging period P10 of the power stage circuit 12A, the charging control signal SCH has multiple successive pulses P11-P13, and each pulse includes an on-period and an off-period. Therefore, the pulses P11-P13 include the on-periods DN11-DN13 respectively, and include the off-periods DF11-DF13 respectively. In addition, in the charging period P10 and the successive maintaining period P20, the discharging control signal SDG is maintained at the low voltage level without any pulse.

[0047] Referring to Figure 5 and Figure 6In the charging period P10, the discharging switch SW13 is continuously turned off to cut off the discharging path between the node N10 and the ground terminal GND because the discharging control signal SDG is maintained at the low voltage level. In addition, in the charging period P10, the control circuit 10 turns on the charging switch SW11 to allow the charging circuit 11A to supply the charging current with the charging current value i1 from the current source circuit 110 to the power stage circuit 12A during the operation periods DN11-DN13 of the charging control signal SCH, respectively. Thus, during the operation periods DN11-DN13, the charging current from the current source circuit 110 is supplied to the first terminal of the capacitor Cg to charge the capacitor Cg multiple times to generate multiple charging steps SU11-SU13 in the rising wave segment of the gate capacitor voltage signal VCg. Referring to Figure 5 With Figure 6 In the operation periods DN11-DN13, the gate current ICg of the capacitor Cg has the charging current value i1, which is positive, indicating that the direction of the gate current ICg is to the capacitor Cg (i.e., to charge the capacitor Cg). In the charging period P10, the control circuit 10 turns off the charging switch SW11 to stop the charging circuit 11A from charging the power stage circuit 12A with the charging current during the non-operation periods DF11-DF13 of the charging control signal SCH. Thus, during the non-operation periods DF11-DF13, the gate capacitor voltage signal VCg stops rising, and multiple stop charging horizontal segments SH11-SH13 are generated in the rising wave segment. After the charging period P10, the electronic circuit 5 enters the sustain period P20 for operation.

[0048] In the sustain period P20, the control circuit 10 causes the charging control signal SCH to have the pulse P14. In this embodiment, the time length of the operation period (i.e., the pulse width) of the pulse P14 is equal to the time length of the sustain period P20, and the pulse P14 has no non-operation period. Referring to Figure 5 With Figure 6 In the sustain period P20, the charging switch SW11 is turned on according to the pulse P14, and the charging circuit 11A supplies the charging current from the current source circuit 110 to the first terminal of the capacitor Cg to charge the capacitor Cg again, and the gate capacitor voltage signal VCg rises again. When the gate capacitor voltage signal VCg rises to the peak level or the preset high level, the gate current ICg becomes zero, and the charging switch SW11 is continuously turned on according to the pulse P14 to maintain the gate capacitor voltage signal VCg at the peak level or the preset high level. At the end of the sustain period P20, the charging control signal SCH is switched to the low voltage level (i.e., the pulse P14 ends). After the sustain period P20, the electronic circuit 5 enters the discharging period P30 of the power stage circuit 12A for operation.

[0049] As Figure 6 shown, during the discharging period P30, the discharging control signal SDG has a plurality of successive pulses P21-P23, and each pulse includes an ON period and an OFF period. Therefore, the pulses P21-P23 respectively include ON periods DN21-DN23, and respectively include OFF periods DF21-DF23.

[0050] Referring Figure 5 to Figure 6 , during the discharging period P30 and the succeeding sustain period P40, the charging control signal SCH is switched to and maintained at a low voltage level, so the charging switch SW11 is continuously turned off to cut off the charging path between the power supply voltage VCC and the node N10. In addition, during the discharging period P30, the control circuit 10 turns on the discharging switch SW13 within the ON periods DN21-DN23 of the discharging control signal SDG, so that the capacitor Cg is discharged by the discharging current provided by the current source CU2. Therefore, a plurality of discharging steps SD21-SD23 are generated in the falling wave segment of the gate capacitor voltage signal VCg which gradually decreases. Referring Figure 5 to Figure 6 , during the ON periods DN21-DN23, the gate current ICg of the capacitor Cg has a discharging current value -i2, where the discharging current value -i2 is negative, indicating that the direction of the gate current ICg is out of the capacitor Cg (i.e. the capacitor Cg is discharged). During the discharging period P30, the control circuit 10 turns off the discharging switch SW13 within the OFF periods DF21-DF23 of the discharging control signal SDG, so that the discharging circuit 13A stops discharging the capacitor Cg. Therefore, during the OFF periods DF21-DF23, the gate capacitor voltage signal VCg stops decreasing, and a plurality of stop discharging horizontal line segments SH21-SH23 are generated in the falling wave segment. After the discharging period P30, the electronic circuit 5 enters the sustain period P40 for operation.

[0051] During the sustain period P40, the control circuit 10 causes the discharging control signal SDG to have a pulse P24. In this embodiment, the time length of the ON period of the pulse P24 (i.e. the pulse width of the pulse P24) is equal to the time length of the sustain period P40. Referring Figure 5 to Figure 6In the sustain period P40, the discharging switch SW13 is turned on according to the pulse P24, and the gate capacitance voltage signal Vcg is discharged again by the discharging current provided by the current source CU2 of the discharging circuit 13A, and the gate capacitance voltage signal Vcg is decreased again. When the gate capacitance voltage signal Vcg is decreased to the above-mentioned valley level or the preset low level, the gate current ICg becomes zero, and the discharging switch SW13 is continuously turned on according to the pulse P24 to maintain the gate capacitance voltage signal Vcg at the above-mentioned valley level or the preset low level. At the point when the sustain period P40 ends, the discharging control signal SDG is switched to the low voltage level (i.e. the pulse P24 ends). After the sustain period P40, the electronic circuit 5 enters the charging period P10 of the next switching period to operate.

[0052] Figure 7 The waveform diagram of the main signals of the electronic circuit of the fifth embodiment of the present application. Figure 7 The pattern of the multi-pulse of the charging control signal SCH is as follows Figure 1 , Figure 3 , Figure 5 and Figure 15 Another example of the respective charging control signal SCH, and Figure 7 The pattern of the multi-pulse of the discharging control signal SDG is as follows Figure 3 , Figure 5 and Figure 15 Another example of the respective discharging control signal SDG.

[0053] The difference between Figure 6 and Figure 7 , Figure 7 The difference between Figure 6 and the fourth embodiment is that, in the charging period P10, the discharging control signal SDG has the same pulse pattern as the charging control signal SCH. According to the above-mentioned embodiments about the operation of controlling the charging circuit 11A and the discharging circuit 13A, the charging switch SW11 is turned on during the working period of the charging control signal SCH, and the discharging switch SW13 is turned on during the working period of the discharging control signal SDG. It is assumed that the charging current value i1 is greater than the discharging current value i2. In the charging period P10 of Figure 7 , the charging switch SW11 is turned on at the same time, the discharging switch SW13 is also turned on, so that the current source circuit 110 supplies the charging current to the first end of the capacitor Cg at the same time, and the discharging current is provided by the current source CU2 to discharge the capacitor Cg. As shown in Figure 7 , in the charging section of the rising section of the gate capacitance voltage signal Vcg, the capacitor Cg is charged according to the current difference between the charging current value i1 and the discharging current value i2 (i.e. the gate current ICg, ICg = i1 - i2 (positive value)). Compared with Figure 6 , Figure 7The gate capacitor voltage signal VCg rises slowly from the trough level or initial low level to the peak level or preset high level during the rising phase. During the rising phase of the gate capacitor voltage signal VCg (i.e., during charging P10), appropriately using a gate current ICg with a charging current value i1 or a current difference (ICg = i1 - i2) to charge the capacitor Cg can improve the control accuracy of the conduction speed of the power stage circuit 12A.

[0054] Assume the discharge current i2 is greater than the charging current i1. According to other embodiments, during discharge P30, while charging switch SW11 is turned on, discharge switch SW13 is also turned on, so that current source circuit 110 supplies charging current to the first terminal of capacitor Cg, and simultaneously provides discharge current through current source CU2 to discharge capacitor Cg. In the charging phase of the falling band of the gate capacitor voltage signal VCg, capacitor Cg is discharged according to the current difference between charging current i1 and discharge current i2 (ICg = i1 - i2 (negative value)). Compared to Figure 6 In this embodiment, the gate capacitor voltage signal VCg discharges directly from the peak level or initial high level to the trough level or preset low level at a relatively slow speed during the falling band. During the falling band of the gate capacitor voltage signal VCg (i.e., during the discharge period P30), appropriately using a gate current ICg with a discharge current value i2 or a current difference (ICg = i1 - i2) to discharge the capacitor Cg can improve the control accuracy of the turn-off speed of the power stage circuit 12A.

[0055] Figure 8-11 The above are waveform diagrams of the signals of the electronic circuits in the sixth to ninth embodiments of this utility model. Figure 1 , Figure 3 , Figure 5 and Figure 15 The pulse pattern of the charging control signal SCH generated by the control circuit 10 and / or Figure 3 , Figure 5 and Figure 15 The pulse pattern of the discharge control signal SDG generated by the control circuit 10 can be the same as that of... Figure 8 The control signal SWA shown is as follows: Figure 9 The control signal SWb shown is as follows: Figure 10 The control signal SWc shown, or as... Figure 11 The pulse pattern of the control signal SWd is shown. (See also...) Figure 8 Multiple pulses of the control signal SWA have the same frequency, for example, all equal to a fixed frequency Fsw. (See also...) Figure 9 Multiple pulses of the control signal SWb have the same operating period, for example, all equal to the fixed on-time Ton. (See also...) Figure 10The plurality of pulses of the control signal SWc have the same non-operation period, for example, all equal to a fixed off time Toff. Referring to Figure 11 The plurality of pulses of the control signal SWd each have the same duty cycle. The above-mentioned pulse patterns are merely illustrative, and the present application is not limited thereto.

[0056] Figure 12 FIG. 10 is a circuit diagram of a control circuit of an electronic circuit using intermittent charging and discharging according to a tenth embodiment of the present application. Figure 13 FIG. 11 is a waveform diagram of a charging control signal and other main signals of the electronic circuit during switching according to the tenth embodiment of the present application. Figure 14 FIG. 12 is a waveform diagram of a discharging control signal and other main signals of the electronic circuit during switching according to the tenth embodiment of the present application. Figure 12 The control circuit 10A is an embodiment of the control circuit 10 of Figure 1 , Figure 3 , Figure 5 and Figure 15 The control circuit 10A is an embodiment of the control circuit 10 of Figure 12 As shown in FIG. 10, the control circuit 10A includes a charging and discharging switching circuit 100, a comparator 101, a signal generating circuit 102, a judging circuit 103, a sensing comparison circuit 104, and a state transition detection circuit 105. The control circuit 10A controls the power stage circuit 12A through a charging control signal SCH and a discharging control signal SDG in a plurality of switching periods.

[0057] The sensing circuit 120 is coupled to the control terminal (gate) and the second terminal (source) of the power transistor Ml to sense the actual voltage difference VGS between the control terminal and the second terminal, to output a sensing voltage signal S30. The voltage level of the sensing voltage signal S30 represents the actual voltage difference VGS. In an embodiment, the voltage level of the sensing voltage signal S30 is equal to the value of the actual voltage difference VGS. The plurality of comparators 121-123 (described below) of the sensing comparison circuit 104 receive the sensing voltage signal S30 from the sensing circuit 120, and compare the sensing voltage signal S30 with a plurality of reference voltages V31-V33, respectively, to output a plurality of comparison signals S31-S33, respectively.

[0058] The judgment circuit 103 is coupled to the sensing comparison circuit 104 to receive comparison signals S31 to S33, and determines the time difference between the time taken for the sensed voltage signal S30 to reach each reference voltage V31 to V33 and the time threshold value based on the comparison signals S31 to S33, and generates a trigger signal S34 based on the judgment result. The signal generation circuit 102 is coupled to the first output terminal of the judgment circuit 103 to receive the trigger signal S34, and generates a state signal Vstate based on the trigger signal S34. In this embodiment, the signal generation circuit 102 controls the voltage level of the state signal Vstate based on the trigger signal S34. As described above, the trigger signal S34 is generated based on the level change of the sensed voltage signal S30 (representing the actual voltage difference VGS of the power transistor M1), and the signal generation circuit 102 generates the state signal Vstate under the control of the trigger signal S34. Therefore, the state signal Vstate depends on the change state of the actual voltage difference VGS.

[0059] The first input terminal of comparator 101 (e.g., the inverting input terminal (-)) receives a reference voltage signal Vsaw, and its second input terminal (e.g., the non-inverting input terminal (+)) is coupled to signal generation circuit 102 to receive a status signal Vstate. Comparator 101 compares the status signal Vstate with the reference voltage signal Vsaw to generate a switching signal S37 at the output terminal of comparator 101. When the voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a high voltage level (corresponding to the operating period); when the voltage level of the status signal Vstate is lower than the voltage level of the reference voltage signal Vsaw, the switching signal S37 is at a low voltage level (corresponding to the non-operating period). The input terminal of charge / discharge switching circuit 100 is coupled to the output terminal of comparator 101 to receive the switching signal S37. The first output terminal of charge / discharge switching circuit 100 serves as the first output terminal of control circuit 10A, and is coupled to... Figure 1 or Figure 3 The input terminal of the charging circuit 11 shown, or coupled to, is as follows Figure 5 The charging circuit 11A shown, or coupled to, is as follows Figure 15 The charging circuit 11B shown includes the control terminal of the charging switch SW11. The second output terminal of the charge / discharge switching circuit 100, serving as the second output terminal of the control circuit 10A, is coupled to... Figure 3 The input terminal of the discharge circuit 13 shown, or coupled to, is as follows Figure 5 The discharge circuit 13A shown, or coupled to, as Figure 15 The control terminal of the discharge switch SW13 included in the discharge circuit 13B shown.

[0060] See Figure 12, the sensing comparison circuit 104 can include a sensing circuit 120, a plurality of comparators 121-123, and a plurality of reference resistors R31-R33. In other embodiments, the sensing circuit 120 can be disposed outside the sensing comparison circuit 104. A first input (e.g., a non-inverting input (+)) of each of the comparators 121-123 is coupled to an output of the sensing circuit 120 to receive the sensing voltage signal S30. The reference resistors R31-R33 are coupled in series between a power supply voltage VDD and a ground terminal GND. In particular, a first terminal of the reference resistor R31 is coupled to the power supply voltage VDD, a second terminal of the reference resistor R31 is coupled to a first terminal of the reference resistor R32, a second terminal of the reference resistor R32 is coupled to a first terminal of the reference resistor R33, and a second terminal of the reference resistor R33 is coupled to the ground terminal GND. The reference resistors R31-R33 perform a voltage division operation on a voltage difference between the power supply voltage VDD and the ground terminal GND to generate reference voltages V31, V32, and V33.

[0061] A second input (e.g., an inverting input (-)) of the comparator 121 is coupled to the first terminal of the reference resistor R31 to receive the power supply voltage VDD as the reference voltage V31. The comparator 121 compares a voltage of the sensing voltage signal S30 with the reference voltage V31 to generate a comparison signal S31 at an output of the comparator 121. A second input (e.g., a non-inverting input) of the comparator 122 is coupled to a common node between the reference resistors R31 and R32 to receive the reference voltage V32 from the common node. The comparator 122 compares a voltage of the sensing voltage signal S30 with the reference voltage V32 to generate a comparison signal S32 at an output of the comparator 122. A second input (e.g., a non-inverting input) of the comparator 123 is coupled to a common node between the reference resistors R32 and R33 to receive the reference voltage V33 from the common node. The comparator 123 compares a voltage of the sensing voltage signal S30 with the reference voltage V33 to generate a comparison signal S33 at an output of the comparator 123. The comparison signals S31-S33 are provided to the determination circuit 103.

[0062] Referring to Figure 12The signal generation circuit 102 can include a switch SW1, a switch SW2, an input current source CUin, and an input capacitor Cin. A first terminal of the switch SW1 is coupled to a second input terminal of the comparator 101 at a node N11. A first terminal of the input current source CUin is coupled to a second terminal of the switch SW1, and a second terminal thereof is coupled to a ground terminal GND. A control terminal of the switch SW1 is coupled to a first output terminal of the decision circuit 103 to receive a trigger signal S34. A first terminal of the input capacitor Cin and a first terminal of the switch SW2 are coupled to the node N11. A second terminal of the input capacitor Cin and a second terminal of the switch SW2 are coupled to the ground terminal GND. The decision circuit 103 further generates a reset signal S35. A control terminal of the switch SW2 is coupled to a second output terminal of the decision circuit 103 to receive the reset signal S35.

[0063] When the switch SW1 is turned on according to the trigger signal S34, an input current provided by the input current source CUin flows through the switch SW1 to the node N11 to charge the input capacitor Cin, so that a voltage at the first terminal of the input capacitor Cin (i.e., a voltage at the node N11) increases. The voltage signal at the first terminal of the input capacitor Cin is the state signal Vstate. The decision circuit 103 enables the reset signal S35 (e.g., makes the reset signal S35 have a pulse to turn on the switch SW2 to discharge the input capacitor Cin, thereby resetting the voltage at the second input terminal of the comparator 101 (to a zero value)) every interval time equal to a time threshold value (e.g., an ideal interval time t0). Figure 13

[0064] The charge-discharge switching circuit 100 receives the switching signal S37 from the output terminal of the comparator 101 as the charging control signal SCH and / or the discharging control signal SDG. For example, the charge-discharge switching circuit 100 can determine to output the switching signal S37 as the charging control signal SCH and / or the discharging control signal SDG according to a transition detection signal S38 received from the transition detection circuit 105, which is described in detail as follows.

[0065] The transition detection circuit 105 receives an indication signal S39 (from an external circuit). According to an embodiment of the present application, a rising edge of the indication signal S39 indicates that the gate capacitance voltage signal VCg enters a rising wave segment, and a falling edge of the indication signal S39 indicates that the gate capacitance voltage signal VCg enters a falling wave segment. The transition detection circuit 105 detects the rising edge and the falling edge of the indication signal S39 to output the transition detection signal S38. According to an embodiment of the present application, during the switching period, whenever the transition detection circuit 105 detects, as described above, the rising edge or the falling edge of the indication signal S39, the transition detection circuit 105 outputs the transition detection signal S38 to the charge-discharge switching circuit 100. Figure 13 ​When the rising edge of the indicated signal S39 is reached, the transition detection circuit 105 outputs a transition detection signal S38 with charging indication information to the charge / discharge switching circuit 100, so as to instruct the charge / discharge switching circuit 100 to use the switching signal S37 as the charging control signal SCH, thereby charging the capacitor Cg of the power stage circuit 12A and causing the power transistor M1 to enter the conduction state.

[0066] According to one embodiment of the present invention, during the switching period, whenever the transition detection circuit 105 detects such as Figure 14 When the falling edge of the indicated signal S39 is reached, the transition detection circuit 105 outputs a transition detection signal S38 with discharge indication information to the charge / discharge switching circuit 100, instructing the charge / discharge switching circuit 100 to use the switching signal S37 as the discharge control signal SDG, thereby discharging the capacitor Cg of the power stage circuit 12A and causing the power transistor M1 to enter the off state. As described above, the indicated signal S39 can represent the on and off states of the power transistor M1 during each switching period. In some embodiments, the transition detection circuit 105 may be located within the judgment circuit 103, and the judgment circuit 103 generates and outputs the transition detection signal S38. In other embodiments, the transition detection circuit 105 may be omitted, and the judgment circuit 103 detects the rising and falling edges of this indicated signal S39 and generates and outputs the transition detection signal S38.

[0067] like Figure 13 , Figure 14 As shown, during the switching period, the curve of the actual voltage difference VGS of power transistor M1 changing with time may deviate from the curve of the ideal voltage difference VGSTG changing with time. See [reference needed]. Figure 13 Starting from the rising edge of indicator signal S39, the ideal voltage difference VGSTG takes ideal time (Tideal) to rise from 0 volts to the supply voltage VDD; see also Figure 14From the time point of the falling edge of the indication signal S39, the ideal voltage difference VGSTG decreases from the power supply voltage VDD to 0 volt also takes the ideal time Tideal. According to this embodiment of the present application, the power supply voltage VDD is averagely divided into m voltage segments. For example, the power supply voltage VDD is averagely divided into 3 (m=3) voltage segments. Ideally, the actual voltage difference VGS of the power transistor Ml increases from 0 volt to 1 / 3 of the default power supply voltage VDD (the first target voltage) after a certain ideal interval time t0, then increases from 1 / 3 of the power supply voltage VDD to 2 / 3 (the second target voltage) after another certain ideal interval time t0, and then increases from 2 / 3 of the power supply voltage VDD to the power supply voltage VDD (the third target voltage) after another certain ideal interval time t0. Therefore, it can be known that the ideal time Tideal is averagely divided into 3 ideal interval times t0, i.e. t0=Tideal / m, wherein m=3. Similarly, ideally, the actual voltage difference VGS decreases from the power supply voltage VDD to 2 / 3 of the power supply voltage VDD, from 2 / 3 of the power supply voltage VDD to 1 / 3, and from 1 / 3 of the power supply voltage VDD to 0 volt in the three ideal interval times t0, respectively.

[0068] As mentioned above, whenever the judging circuit 103 enables the reset signal S35, the switch SW2 is turned on according to the enabled reset signal S35 (i.e. according to the pulse of the reset signal S35), so that the voltage of the input capacitor Cin is discharged to reset to zero value. Ideally, whenever the judging circuit 103 enables the reset signal S35, the judging circuit 103 makes the trigger signal S34 have an initial pulse P31, and the initial pulse P31 has a preset working period DN31. In this embodiment, the preset working period DN31 is equal to the ideal interval time t0 divided by a constant k (DN31=t0 / k). In an embodiment, the constant k is preset according to system requirement. In each ideal time Tideal, the trigger signal S34 has three initial pulses P31, which correspond to the three ideal interval times t0, respectively. In Figure 13 、 Figure 14 In the following, the initial pulse P31 is represented by a dashed line. Since some initial pulses P31 completely or partially overlap with the modulated pulses (e.g. the modulated pulses P41-P43, the modulated pulses P81-P83, which are described in the following) represented by solid lines, the parts of the initial pulses P31 which overlap with the modulated pulses are not shown by the dashed lines in the following. Figure 13 、 Figure 14 In the following, the initial pulse P31 is represented by a dashed line. Since some initial pulses P31 completely or partially overlap with the modulated pulses (e.g. the modulated pulses P41-P43, the modulated pulses P81-P83, which are described in the following) represented by solid lines, the parts of the initial pulses P31 which overlap with the modulated pulses are not shown by the dashed lines in the following.

[0069] However, in practice, the actual voltage difference VGS of the power transistor Ml can reach the at least one target voltage in time, early, or late during the switching period. Therefore, the control circuit 10A of the embodiment of the present application adjusts the operation period of the plurality of pulses of at least one of the charge control signal SCH and the discharge control signal SDG according to the actual voltage difference VGS of the power transistor Ml, so that the actual voltage difference VGS can gradually approach the ideal voltage difference VGSTG.

[0070] Referring to Figure 12 , the determination circuit 103 also receives the indication signal S39. As shown in Figure 13 , based on the rising edge of the indication signal S39, the electronic circuit enters the current switching period, the charge-discharge switching circuit 100 takes the switching signal S37 as the charge control signal SCH according to the transition detection signal S38, and the gate capacitance voltage signal VCg enters the rising wave segment (i.e. enters the charging period of the power stage circuit 12A), so that the actual voltage difference VGS of the power transistor Ml gradually rises with the gate capacitance voltage signal VCg. In detail, at the time point of the rising edge of the indication signal S39 (i.e. at the starting time point of the first ideal interval time t0 in the charging period) and the starting time points of the second and third ideal interval times t0 respectively, the determination circuit 103 makes the reset signal S35 have pulses respectively to turn on the switch SW2, so as to reset the voltage of the input capacitor Cin to zero. In this embodiment, it is assumed that at the starting time points of the first to third ideal interval times t0 respectively, the determination circuit 103 makes the trigger signal S34 have initial pulses P31, in other words, in the current switching period, the initial pulses P31 serve as the modulated pulses P41-P43 of the trigger signal S34, and the actual operation period Tvty(t) of the modulated pulses P41-P43 is equal to DN31 (= t0 / k) (y is 41, 42, or 43) to turn on the switch SWl, so that the input capacitor Cin is charged, and the voltage level of the state signal Vstate starts to increase, as shown in the state signal Vstate represented by the dashed line in Figure 13 . Based on the state signal Vstate in the current switching period, through the operation of the comparator 101 and the charge-discharge switching circuit 100, the charge control signal SCH has three initial pulses P60 in the first to third ideal interval times t0 respectively. It is assumed that, in the charging period in the current switching period, based on the three initial pulses P60, as shown in Figure 13 , the curve of the change of the actual voltage difference VGS with time deviates from the curve of the change of the ideal voltage difference VGSTG with time. According to the above, it is known that the three initial pulses P60 correspond to the three initial pulses P31 of the trigger signal S34 respectively. The initial pulses P60 are represented by dashed lines, and the modulated pulses P61-P63 (to be described later) are represented by solid lines. In Figure 13In the current switching period, there should be three initial pulses P60, but since the first initial pulse P60 completely overlaps with the modulated pulse P61, the first initial pulse P60 is not shown in the figure. Figure 13 The first initial pulse P60 is not shown in the figure.

[0071] Referring to Figure 13 In the current switching period, the actual voltage difference VGS of the power transistor M1 takes an actual interval time t11 equal to the ideal interval time t0 from the starting point of the first segment ideal interval time t0 to 1 / 3 of the power supply voltage VDD, i.e. t11=t0, so that the actual interval time t11 minus the ideal interval time t0 obtains a time difference Δt11 (Δt11=t11-t0=0, i.e. there is no error between the actual interval time t11 and the ideal interval time t0). In the embodiment of the present application, once the actual voltage difference VGS increases from 0 volt and reaches 1 / 3 of the power supply voltage VDD, the voltage level of the sensing voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S33 output by the comparator 123 is switched to a high voltage level. The judging circuit 103 obtains the actual interval time t11 according to the time point of the rising edge of the indication signal S39 and the time point at which the comparison signal S33 is switched to a high voltage level. The judging circuit 103 judges that the actual interval time t11 is equal to the ideal interval time t0 (t11=t0) and calculates that the time difference Δt11 is equal to zero (Δt11=0).

[0072] The judging circuit 103 determines the actual working period of one of the modulated pulses of the trigger signal S34 in the next switching period according to formula 1:

[0073] Tvty(t+1)=Tvty(t)+c*Δtx (Formula 1)

[0074] Wherein, Tvty(t) represents the actual working period of one modulated pulse of the trigger signal S34 in the current switching period, Tvty(t+1) represents the actual working period of one modulated pulse of the trigger signal S34 in the next switching period, c is a pre-determined error compensation coefficient, x is 11, 12, 13, 21, 22, or 23, and y is 41, 42, 43, 81, 82, or 83.

[0075] As mentioned above, during the current switching period, the actual active period Tvt41(t) of the modulated pulse P41 of the trigger signal S34 is equal to DN31 (= t0 / k) and Δt11 = 0. Thus, according to equation 1, the decision circuit 103 determines that the actual active period Tvt41(t+1) of the modulated pulse P41 of the trigger signal S34 in the next switching period is equal to t0 / k, i.e. equal to the preset active period DN31 (Tvt41(t+1) = t0 / k + c*0 = t0 / k = DN31). In this embodiment, the modulated pulses of the trigger signal S34 are represented by solid lines. Thus, the modulated pulse P41 of the solid line overlaps with the corresponding initial pulse P31 of the dashed line, Figure 13 Only the implemented modulated pulse P41 is represented in the middle.

[0076] According to the above, the actual active period Tvt41 of the modulated pulse P41 is equal to the preset active period DN31 of the initial pulse P31. In the next switching period, the switch SW1 is turned on according to the modulated pulse P41 within the preset active period DN31 and the input current provided by the input current source CUin charges the input capacitor Cin via the switch SW1 for the time length of the preset active period DN31, as shown in Figure 13 the actual voltage level of the state signal Vstate represented by the solid line is higher than the voltage level of the reference voltage signal Vsaw for a duration equal to the ideal active period (i.e. the active period of the initial pulse P60). In this way, the duration of the switching signal S37 at the high voltage level is equal to the ideal active period mentioned above. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the charge control signal SCH based on the rising edge of the indication signal S39 by the transition detection signal S38, the charge-discharge switching circuit 100 controls the duty cycle of the first pulse of the charge control signal SCH to be equal to the ideal active period mentioned above (i.e. the modulated pulse P61 whose duty cycle is equal to the ideal active period mentioned above), so that the on period of the power transistor M1 is equal to the ideal active period mentioned above.

[0077] Referring to Figure 13, in the current switching period, the actual voltage difference VGS of the power transistor M1 takes the actual interval time t12 delayed from 1 / 3 of the power voltage VDD to 2 / 3 of the power voltage VDD from the starting point of the second segment ideal interval time t0, and the actual interval time t12 is greater than the ideal interval time t0, i.e. t12>t0, therefore, the actual interval time t12 minus the ideal interval time t0 obtains the time difference Δt12 (Δt12=t12-t0>0, i.e. there is an error between the actual interval time t12 and the ideal interval time t0). In the embodiment of the present application, once the actual voltage difference VGS increases from 1 / 3 of the power voltage VDD and reaches 2 / 3 of the power voltage VDD, the voltage level of the sensing voltage signal S30 is equal to the reference voltage V32. At this time, the comparison signal S32 output by the comparator 122 is switched to the high voltage level. The judgment circuit 103 obtains the actual interval time t12 according to the starting point of the second segment ideal interval time t0 and the time point when the comparison signal S32 is switched to the high voltage level. The judgment circuit 103 judges that the actual interval time t12 is greater than the ideal interval time t0 (t12>t0), and calculates that the time difference Δt12 is greater than zero (Δt12>0). As described above, in the current switching period, the actual working period Tvt42(t) of the modulation pulse P42 of the trigger signal S34 is equal to DN31 (=t0 / k). According to formula 1, the judgment circuit 103 determines that the actual working period Tvt42(t+1) of the modulation pulse P42 of the trigger signal S34 in the next switching period is equal to t0 / k+c*Δt12, i.e. greater than the preset working period DN31 (Tvt42(t+1)=t0 / k+c*Δt12>DN31).

[0078] According to the above, the actual working period Tvt42 of the modulation pulse P42 is greater than the preset working period DN31 of the initial pulse P31. Therefore, in the next switching period, the switch SW1 is turned on according to the modulation pulse P42 in the longer actual working period Tvt42, and the time for the input current source CUin to charge the input capacitor Cin via the switch SW1 is longer (longer than the length of the preset working period DN31), as shown in Figure 13As shown, the duration during which the actual voltage level of the status signal Vstate marked by a solid line is higher than the voltage level of the reference voltage signal Vsaw becomes longer (longer than the above-mentioned ideal operating period). In this way, the duration during which the switching signal S37 is at a high voltage level becomes longer. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the charge control signal SCH based on the rising edge of the indication signal S39, the charge-discharge switching circuit 100 controls the duty cycle of the second pulse of the charge control signal SCH to be longer than the above-mentioned ideal operating period (that is, modulates the pulse P62, whose duty cycle is longer than the above-mentioned ideal operating period), making the conduction period of the power transistor M1 longer. Since the second initial pulse P60 partially overlaps with the modulated pulse P62 presented by a solid line, Figure 13 the dotted line indicating the overlapping part of the second initial pulse P60 and the modulated pulse P62 in Figure 13 is not shown.

[0079] Refer to Figure 13 , in the current switching period, starting from the starting point of the third ideal interval time t0, the actual voltage difference VGS of the power transistor M1 reaches the power supply voltage VDD from 2 / 3 of the power supply voltage VDD in the actual interval time t13, and the actual interval time t13 is less than the ideal interval time t0, that is, t13 < t0. Therefore, the time difference Δt13 is obtained by subtracting the ideal interval time t0 from the actual interval time t13 (Δt13 = t13 - t0 < 0). In the embodiment of the present invention, once the actual voltage difference VGS increases from 2 / 3 of the power supply voltage VDD and reaches the power supply voltage VDD, the voltage level of the sensed voltage signal S30 is equal to the reference voltage V33. At this time, the comparison signal S31 output by the comparator 121 switches to a high voltage level. The determination circuit 103 obtains the actual interval time t13 based on the starting point of the third ideal interval time t0 and the time point when the comparison signal S31 switches to a high voltage level. The determination circuit 103 determines that the actual interval time t13 is less than the ideal interval time t0 (t13 < t0), and calculates that the time difference Δt13 is less than zero (Δt13 < 0, that is, there is an error between the actual interval time t13 and the ideal interval time t0). As described above, in the current switching period, the actual operating period Tvt43(t) of the modulated pulse P43 of the trigger signal S34 is equal to DN31 (= t0 / k). According to Equation 1, the determination circuit 103 determines that the actual operating period Tvt43(t + 1) of the modulated pulse P43 of the trigger signal S34 in the next switching period is equal to t0 / k + c * Δt13, that is, less than the preset operating period DN31 (Tvt43(t + 1) = t0 / k + c * Δt13 < DN31).

[0080] As described above, the actual operating period Tvt43 of the modulated pulse P43 is less than the preset operating period DN31 of the initial pulse P31. Therefore, in the next switching period, switch SW1 is turned on during the shorter actual operating period Tvt43 according to the modulated pulse P43, and the time for the input current provided by the input current source CUin to charge the input capacitor Cin via switch SW1 is shortened (shorter than the preset operating period DN31). Figure 13 As shown, this shortens the duration for which the actual voltage level of the state signal Vstate (indicated by the solid line) is higher than the voltage level of the reference voltage signal Vsaw (shorter than the ideal operating period). Consequently, the duration for which the switching signal S37 is at a high voltage level is shortened. During the next switching period, when the charge / discharge switching circuit 100 outputs the switching signal S37 as the charging control signal SCH based on the rising edge of the indicator signal S39, the operating period of the third pulse of the charging control signal SCH controlled by the charge / discharge switching circuit 100 is shorter than the ideal operating period (i.e., the modulated pulse P63 has a shorter operating period than the ideal operating period), thus shortening the on-time of the power transistor M1. Since the third initial pulse P60 partially overlaps with the modulated pulse P63 (indicated by the solid line), therefore... Figure 13 The dashed line at the point where the third initial pulse P60 overlaps with the modulated pulse P63 is not shown in the image.

[0081] During each switching period, at the end of the third ideal interval time t0 during the charging period, the determination circuit 103 pulses the reset signal S35 again to turn on the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. Simultaneously, at the end of the third ideal interval time t0, the charge / discharge switching circuit 100 pulses the charging control signal SCH with a pulse P64, and the pulse width of P64 ends at the falling edge of the indicator signal S39. During the pulse width of P64 (i.e., during the maintenance period of the power stage circuit 12A), the charging switch SW11 remains on according to P64, and the gate capacitor voltage signal VCg rises and remains at the peak level or a preset high level, causing the actual voltage difference VGS of the power transistor M1 to rise and remain at a specific level (this specific level is higher than the power supply voltage VDD level).

[0082] In one embodiment, during each switching period, based on the rising edge of the indication signal S39, the determination circuit 103 starts counting the number of pulses of the reset signal S35. When the cumulative number of pulses of the reset signal S35 starting from the rising edge of the indication signal S39 reaches a pulse count threshold (e.g., ...), the count continues. Figure 14 When there are four (=m+1=3+1) as shown, the judgment circuit 103 outputs a control signal S40 to control the charge-discharge switching circuit 100, so that its output charging control signal SCH has a pulse P64.

[0083] As described above, based on the rising edge of the indicator signal S39, the gate capacitor voltage signal VCg enters the rising band. During the rising band of the gate capacitor voltage signal VCg, the intermittent charging and discharging method of this invention adjusts the operating period of multiple pulses of the charging control signal SCH (i.e., the on-time of the charging switch SW11) according to the actual voltage difference VGS of the power transistor M1. In this way, the change in the actual voltage difference VGS of the power transistor M1 can gradually approach the ideal voltage difference VGSTG.

[0084] During each switching period, during the charging and sustaining periods of the power stage circuit 12A, the charge / discharge switching circuit 100 controls the discharge control signal SDG to remain at a low voltage level to turn off the discharge switch SW13, thereby cutting off the discharge path between node N10 and ground terminal GND until the falling edge of the indicator signal S39.

[0085] like Figure 14 As shown, during the current switching period, based on the falling edge of the indication signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as the discharge control signal SDG according to the state detection signal S38, and the gate capacitor voltage signal VCg enters the falling band (i.e., the discharge period of the power stage circuit 12A), causing the actual voltage difference VGS of the power transistor M1 to gradually decrease along with the gate capacitor voltage signal VCg. During the discharge period, the charge / discharge switching circuit 100 first controls the discharge control signal SDG to have a pulse P80, so that the discharge switch SW13 is turned on during the operation of the pulse P80, causing the actual voltage difference VGS of the power transistor M1 to start decreasing from a specific level higher than the power supply voltage VDD. The operation period of the pulse P80 is preset, starting at the point when the actual voltage difference VGS begins to decrease from the specific level, and ending at the point when the reset signal S35 makes its first pulse during the discharge period.

[0086] Furthermore, based on the falling edge of the indicator signal S39, the charge / discharge switching circuit 100 controls the charging control signal SCH to switch to a low voltage level and maintains it at the low voltage level until the rising edge of the indicator signal S39 during the next switching period.

[0087] Next, during the current switching period, at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the reset signal S35 to have a pulse to turn on the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero. In this embodiment, it is assumed that at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the trigger signal S34 to have an initial pulse P31. In other words, during the current switching period, the initial pulse P31 serves as the modulated pulses P81 to P83 of the trigger signal S34, and the actual operating period Tvty(t) of the modulated pulses P81 to P83 is equal to DN31 (=t0 / k) (y is 81, 82, or 83). Furthermore, at the start of each of the first to third ideal intervals t0 during the discharge period, the determination circuit 103 causes the trigger signal S34 to have an initial pulse P31 to turn on the switch SW1, causing the input capacitor Cin to be charged, and the voltage level of the state signal Vstate begins to increase, such as Figure 14 The state signal Vstate is represented by a dashed line. Based on the state signal Vstate during the current switching period, the charging control signal SCH has three initial pulses P60 during the first to third ideal interval times t0, respectively, through the operation of comparator 101 and the charge / discharge switching circuit 100. During the discharge period of the current switching period, based on these three initial pulses P60, as follows... Figure 14 As shown, the curve of the actual voltage difference VGS changing with time deviates from the curve of the ideal voltage difference VGSTG changing with time. As can be seen from the above, the three initial pulses P60 during the discharge period correspond to the three initial pulses P31 of the trigger signal S34. The initial pulses P60 are represented by dashed lines, while the modulated pulses P91 to P93 (described later) are represented by solid lines.

[0088] See Figure 14, during this current switching period, starting from the starting point of the first ideal interval time t0, the actual voltage difference VGS reaches 2 / 3 of the power supply voltage VDD in an actual interval time t23 that is shorter than the ideal interval time t0, that is, t23 < t0. According to the above description and the analogous operation during the charging period, the judgment circuit 103 calculates that the time difference Δt23 is less than zero (Δt23 = t23 - t0 < 0, that is, there is an error between the actual interval time t23 and the ideal interval time t0). As described above, during the current switching period, the actual working period Tvt81(t) of the modulation pulse P81 of the trigger signal S34 is equal to DN31 ( = t0 / k). According to Equation 1, the judgment circuit 103 determines that in the next switching period, the actual working period Tvt81(t + 1) of the modulation pulse P81 of the trigger signal S34 is equal to t0 / k + c*Δt23, that is, less than the preset working period DN31 (Tvt81(t + 1) = t0 / k + c*Δt23 < DN31). The switch SW1 conducts in a shorter actual working period Tvt81, and the charging time of the input capacitor Cin becomes shorter (shorter than the time length of the preset working period DN31), as Figure 14 shown, so that the duration during which the actual voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw becomes shorter (shorter than the above ideal working period). In this way, the duration during which the switching signal S37 is at the high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indication signal S39, the charge-discharge switching circuit 100 controls the working period of the first pulse of the discharge control signal SDG to be shorter than the above ideal working period (that is, the modulation pulse P91, whose working cycle is shorter than the above ideal working period), making the conduction time of the power transistor M1 shorter. Since the first initial pulse P60 and the modulation pulse P91 partially overlap, Figure 14 the dotted line showing the overlapping part of the first initial pulse P60 and the modulation pulse P91 in

[0089] Refer to Figure 14 , the starting point of the working period of the modulation pulse P91 overlaps with the ending point of the working period of the pulse P80, so Figure 14 the rising edge of the modulation pulse P91 is not presented in

[0090] Refer to Figure 14During this current switching period, starting from the beginning of the second ideal interval time t0, the actual voltage difference VGS takes a longer time than the ideal interval time t0, from 2 / 3 of the power supply voltage VDD to 1 / 3 of the power supply voltage VDD, i.e., t22>t0. Based on the above description and the analogy during charging, the judgment circuit 103 calculates that the time difference Δt22 is greater than zero (Δt22=t22-t0>0, i.e., there is an error between the actual interval time t22 and the ideal interval time t0). As mentioned above, during the current switching period, the actual operating period Tvt82(t) of the modulation pulse P82 of the trigger signal S34 is equal to DN31(=t0 / k). According to Equation 1, the judgment circuit 103 determines that the actual working period Tvt82(t+1) of the modulated pulse P82 of the trigger signal S34 in the next switching period is equal to t0 / k+c*Δt22, which is greater than the preset working period DN31 (Tvt82(t+1)=t0 / k+c*Δt22>DN31). Switch SW1 is turned on during the longer actual working period Tvt82, and the charging time of the input capacitor Cin becomes longer (longer than the preset working period DN31), such as... Figure 14 As shown, this makes the duration for which the actual voltage level of the state signal Vstate is higher than the voltage level of the reference voltage signal Vsaw longer (longer than the ideal operating period). Consequently, the duration for which the switching signal S37 is at a high voltage level is longer. During the next switching period, when the charge / discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indicator signal S39, the second pulse of the discharge control signal SDG controlled by the charge / discharge switching circuit 100 operates for a period longer than the ideal operating period (i.e., the modulated pulse P92 has a longer operating period than the ideal operating period), thus increasing the on-time of the power transistor M1. Since the second initial pulse P60 partially overlaps with the modulated pulse P92, therefore... Figure 14 The dashed line at the point where the second initial pulse P60 overlaps with the modulated pulse P92 is not shown in the image.

[0091] See Figure 14, during this current switching period, starting from the starting point of the third ideal interval time t0, the actual voltage difference VGS reaches 0 volts earlier by 1 / 3 of the power supply voltage VDD in an actual interval time t21 shorter than the ideal interval time t0, that is, t21 < t0. According to the above description and the analogous operation during the charging period, the determination circuit 103 calculates that the time difference Δt21 is less than zero (Δt21 = t21 - t0 < 0, that is, there is an error between the actual interval time t21 and the ideal interval time t0). As described above, during the current switching period, the actual working period Tvt83(t) of the modulation pulse P83 of the trigger signal S34 is equal to DN31 (= t0 / k). According to Equation 1, the determination circuit 103 determines that the actual working period Tvt83(t + 1) of the modulation pulse P83 of the trigger signal S34 in the next switching period is equal to t0 / k + c * Δt21, that is, less than the preset working period DN31 (Tvt83 = t0 / k + c * Δt21 < DN31). The switch SW1 conducts in a shorter actual working period Tvt83, and the charging time of the input capacitor Cin becomes shorter (shorter than the time length of the preset working period DN31), as Figure 14 shown, making the duration for which the actual voltage level of the status signal Vstate is higher than the voltage level of the reference voltage signal Vsaw shorter (shorter than the above ideal working period). In this way, the duration for which the switching signal S37 is at the high voltage level becomes shorter. In the next switching period, when the charge-discharge switching circuit 100 outputs the switching signal S37 as the discharge control signal SDG based on the falling edge of the indication signal S39, the charge-discharge switching circuit 100 controls the working period of the third pulse of the discharge control signal SDG to be shorter than the above ideal working period (that is, the modulation pulse P93, whose working cycle is shorter than the above ideal working period), making the conduction time of the power transistor M1 shorter. Since the third initial pulse P60 and the modulation pulse P93 partially overlap, Figure 14 the dotted line indicating the overlapping part of the third initial pulse P60 and the modulation pulse P93 is not shown in

[0092] In each switching period, at the end point of the third ideal interval time t0 during the discharge period, the determination circuit 103 makes the reset signal S35 have a pulse again to conduct the switch SW2, thereby resetting the voltage of the input capacitor Cin to zero value again. At the same time, at the end point of the third ideal interval time t0, the charge-discharge switching circuit 100 makes the discharge control signal SDG have a pulse P94, and the pulse width period of the pulse P94 ends at the rising edge of the indication signal S39. During the pulse width period of the pulse P94 (that is, during the maintenance period of the power stage circuit 12A), the discharge switch SW13 continuously conducts according to the pulse P94, and the gate capacitance voltage signal VCg is maintained at the valley level or a preset low level, making the actual voltage difference VGS of the power transistor M1 maintained at 0 volts.

[0093] According to one embodiment, during each switching period, based on the falling edge of the indicator signal S39, the determination circuit 103 starts counting the number of pulses of the reset signal S35. When the cumulative number of pulses of the reset signal S35 starting from the falling edge of the indicator signal S39 reaches a pulse count threshold (e.g., ...), the count continues. Figure 12-14 When there are four (=m+1=3+1) as shown, the judgment circuit 103 outputs a control signal S40 to control the charge-discharge switching circuit 100, so that its output discharge control signal SDG has a pulse P94.

[0094] As described above, based on the falling edge of the indicator signal S39, the gate capacitor voltage signal VCg enters the falling band. During the falling band of the gate capacitor voltage signal VCg, the intermittent charging and discharging method of this invention adjusts the operating period of multiple pulses of the discharge control signal SDG (i.e., the on-time of the discharge switch SW13) according to the actual voltage difference VGS of the power transistor M1, so that the change of the actual voltage difference VGS of the power transistor M1 can be closer to the ideal voltage difference VGSTG.

[0095] Based on the above, during the current switching period, the control circuit 10A determines the pulse patterns of the charging control signal SCH and the discharging control signal SDG during the next switching period based on the actual voltage difference VGS. This achieves the intermittent charging and discharging method of this invention, thereby improving the accuracy of charging and discharging control and flexibly controlling the charging and discharging states of the power stage circuit 12A. Through the charging and discharging control of this invention, the curve of the actual voltage difference VGS of the power transistor M1 changing with time can be changed, gradually conforming to the curve of the ideal voltage difference VGSTG changing with time, thus enabling the output voltage level change rate at the output terminal LIN of the power stage circuit 12A to reach the desired value.

[0096] In the above embodiments, the pulse pattern of the charging control signal SCH and / or discharging control signal SDG is determined based on the actual gate-source voltage (VGS) of the power transistor M1. In other embodiments, the pulse pattern of the charging control signal SCH and / or discharging control signal SDG can be determined based on the drain-source voltage (VDS) of the power transistor M1. Specifically, the control circuit 10A can perform the pulse pattern based on the drain-source voltage of the power transistor M1 dropping from the supply voltage VDD to 0 volts in an ideal time, Tideal. Figure 12-14 Similar operations are performed to determine the pulse pattern of the charging control signal SCH and / or the discharging control signal SDG. Please refer to the relevant description. Figure 15 The explanation is omitted here.

[0097] Please see Figure 5This is a circuit diagram of the electronic circuit 15 employing intermittent charging and discharging according to the eleventh embodiment of this utility model. Figure 15 In the circuit, charging circuit 11A includes current source CU1, and discharging circuit 13A includes current source CU2. Figure 5 In the embodiment, the charging circuit 11B includes a charging-side resistor R15, replacing... Figure 5 The charging circuit 11A; the discharging circuit 13B includes a discharging-side resistor R16, replacing... Figure 7 The discharge circuit is 13A.

[0098] When the charging switch SW11 is turned on according to the charging control signal SCH, the charging current flows from the power supply voltage VCC through the charging-side resistor R15 and the turned-on charging switch SW11 to the capacitor Cg, charging the capacitor Cg and gradually increasing the voltage level of the gate capacitor voltage signal VCg at the first terminal of the capacitor Cg. When the discharging switch SW13 is turned on according to the discharging control signal SDG, the discharging current flows from the first terminal of the capacitor Cg through the discharging-side resistor R16 and the turned-on discharging switch SW13 to the ground terminal GND, discharging the capacitor Cg and gradually decreasing the voltage level of the gate capacitor voltage signal VCg.

[0099] In the above embodiments, based on the rising edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as only the charging control signal SCH according to the transition detection signal S38; based on the falling edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as only the discharging control signal SDG according to the transition detection signal S38. In some embodiments, based on the rising edge and / or falling edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as both the charging control signal SCH and the discharging control signal SDG according to the transition detection signal S38. For example, during charging, based on the rising edge of the indicator signal S39, the charge / discharge switching circuit 100 uses the switching signal S37 as both the charging control signal SCH and the discharging control signal SDG, such that the charging control signal SCH and the discharging control signal SDG have the same pulse pattern, such as... Figure 12 As shown.

[0100] As described above, during the current switching period, control circuit 10A controls charging circuit 11A and discharging circuit 13A based on the switching signal S37 determined in the previous switching period, thereby controlling the charging and discharging of power stage circuit 12A, and consequently controlling the turn-on and turn-off speed of power transistor M1. According to another embodiment of the present invention, during the charging period of this current switching period, while power stage circuit 12A is charging based on the switching signal S37 determined in the previous switching cycle, control circuit 10A determines whether to additionally enable the discharge control signal SDG (i.e., additionally control the discharge control signal SDG to be at a high voltage level) based on the actual voltage difference VGS. For details, see [link to relevant documentation]. Figure 13 and Figure 16 During the charging period of the current switching period, if the judgment circuit 103 determines that any of the comparison signals S31 to S33 switches to a high voltage level within the first ideal interval time t0, or determines that comparison signals S31 or S32 switches to a high voltage level within the second ideal interval time t0, or determines that comparison signal S31 switches to a high voltage level within the first half (first half) of the third ideal interval time t0, it indicates that the power stage circuit 12A has been overcharged. At this time, the judgment circuit 103 controls the charge / discharge switching circuit 100 to additionally enable the discharge control signal SDG through the judgment signal S36, so as to reduce the voltage level of the gate capacitor voltage signal VCg. For example, see Figure 7 During period P15 of the charging process, the discharge control signal SDG did not... Figure 7 Instead of switching to a low voltage level, it remains at a high voltage level (i.e., compared to the previous level). Figure 16 The corresponding pulse of the discharge control signal SDG is additionally enabled, thereby extending the operating period of the corresponding pulse of the discharge control signal SDG to turn on the discharge switch SW13. Therefore, the gate capacitor voltage signal VCg decreases during period P15, resulting in a discharge stage SD11 in the rising phase of the gate capacitor voltage signal VCg, thereby compensating for the excessively rapid rise in the level of the gate capacitor voltage signal VCg due to overcharging. Figure 12 As shown, elevator segment SD11 is located between two charging segments.

[0101] Similarly, during the discharge period of this current switching period, while the power stage circuit 12A discharges based on the switching signal S37 determined in the previous switching cycle, the control circuit 10A determines whether to additionally enable the charging control signal SCH (i.e., to keep the additional charging control signal SCH at a high voltage level) based on the actual voltage difference VGS. For details, see [link to relevant documentation]. Figure 14 and Figure 16During the discharge period of the current switching period, if the judgment circuit 103 determines that the comparison signal S32 or S33 switches to a low voltage level within the first ideal interval time t0, or determines that the comparison signal S33 switches to a low voltage level within the second ideal interval time t0, or determines that the comparison signal S33 switches to a low voltage level within the first half (first half) of the third ideal interval time t0, it indicates that the power stage circuit 12A has over-discharged. At this time, the judgment circuit 103 controls the charge / discharge switching circuit 100 to additionally enable the charging control signal SCH through the judgment signal S36, so as to increase the voltage level of the gate capacitor voltage signal VCg. For example, see Figure 7 During period P16 of the charging process, the charging control signal SCH was not as expected. Figure 7 Instead of maintaining a low voltage level, it switches to a high voltage level (i.e., compared to the previous level). Figure 16 An additional enable charging control signal (SCH) is used to turn on the charging switch SW11. Therefore, the gate capacitor voltage signal VCg rises during period P16, creating a charging step SU21 in the falling band of the gate capacitor voltage signal VCg, thereby compensating for the excessively rapid level drop of the gate capacitor voltage signal VCg due to over-discharge. Figure 16 As shown, the charging elevator segment SU21 is located between the two discharging elevator segments. In this embodiment, the lengths of P15 and P16 are equal.

[0102] pass Figure 16 In one embodiment, during the current switching period, when the power stage circuit 12A overcharges or overdischarges based on the switching signal S37 determined in the previous switching period, the control circuit 10A can fine-tune the pulse pattern of the charging control signal SCH and / or the discharging control signal SDG in real time, thereby correcting the level change of the gate capacitor voltage signal VCg, so as to accelerate the curve of the actual voltage difference VGS of the power transistor M1 changing with time to match the curve of the ideal voltage difference VGSTG changing with time.

[0103] In other embodiments, the control circuit 10A or the charge / discharge switching circuit 100 may further include a compensation circuit that receives a judgment signal S36 and generates a pulse corresponding to the discharge segment SD11 and / or a pulse corresponding to the charging segment SU21 based on the judgment signal S36. When the charge / discharge switching circuit 100 receives this pulse during charging, it controls the discharge control signal SDG to have this pulse (e.g., Figure 16 In the context of the discharge control signal SDG, the pulse corresponding to period P15 is used; when the charge / discharge switching circuit 100 receives this pulse during the discharge period, it controls the charge control signal SCH to have this pulse (e.g., the pulse during period P15). ​In the context of the charging control signal SCH, the pulse corresponding to period P16 is mentioned. This invention does not limit the specific architecture of the compensation circuit; any circuit that can generate a pulse with a fixed width based on the judgment signal S36 can serve as the aforementioned compensation circuit.

[0104] It is worth noting that the intermittent charging and discharging method of this invention replaces the existing technology which involves continuous charging during charging and continuous discharging during discharging, enabling more precise control. The charging circuit, discharging circuit, and multiple circuit elements included in the power stage circuit of the electronic circuit employing intermittent charging and discharging in this invention are merely illustrative examples and are not intended to limit the invention to these aspects.

[0105] In summary, this invention provides an intermittent charging and discharging method, an intermittent discharging method, and an electronic circuit employing intermittent charging and discharging. The intermittent charging and discharging method and the electronic circuit employing intermittent charging and discharging employ intermittent control of the on / off states of both the charging circuit (including the charging switch) and the discharging circuit (including the discharging switch). The intermittent discharging method employs intermittent control of the on / off states of the discharging circuit (including the discharging switch). Therefore, compared to existing technologies, the intermittent charging and discharging method, the intermittent discharging method, and the electronic circuit employing intermittent charging and discharging significantly improve control accuracy. Furthermore, compared to existing technologies, the electronic circuit employing intermittent charging and discharging reduces the required control hardware circuitry, thereby reducing design area and power consumption, and saving costs.

[0106] The above-disclosed content is only a preferred and feasible embodiment of the present utility model, and is not intended to limit the scope of the patent application of the present utility model. Therefore, all equivalent technical changes made based on the contents of the present utility model specification and drawings are included in the claims of the present utility model.

[0107] [Symbol Explanation]

[0108] 1, 3, 5, 15: Electronic Circuits

[0109] 10, 10A: Control circuit

[0110] 11, 11A, 11B: Charging circuit

[0111] 12, 12A: Power stage circuit

[0112] 13, 13A, 13B: Discharge circuit

[0113] 100: Charge / discharge switching circuit

[0114] 102: Signal generation circuit

[0115] 103: Judgment Circuit

[0116] 104: Sensing Comparison Circuit

[0117] 105: Transition Detection Circuit

[0118] 101: Comparator

[0119] 110: Charging-side current source circuit

[0120] 120: Sensing Circuit

[0121] 121-123: Comparator

[0122] 130: Discharge-side current source circuit

[0123] C1, Cg: Capacitors

[0124] Cin: Input capacitance

[0125] CU1: Charging-side current source

[0126] CU2: Discharge-side current source

[0127] CUin: Input current source

[0128] D: Duty Cycle

[0129] D1: Upper diode

[0130] D2: Lower diode

[0131] DN11~DN13, DN21~DN23, DN31: During working period

[0132] DF11~DF13, DF21~DF23: Non-working period

[0133] Fsw: Fixed Frequency

[0134] GND: Ground terminal

[0135] i1: Charging current value

[0136] i2: Discharge current value

[0137] ICg: Gate current

[0138] LIN: Output terminal

[0139] M1: Power transistor

[0140] N10, N11: Nodes

[0141] P10: During charging

[0142] P11~P14: Pulse Wave

[0143] P15, P16: Period

[0144] P20, P40: Maintenance period

[0145] P21~P24: Pulse Wave

[0146] P30: During discharge

[0147] P31: Initial Pulse

[0148] P41~P43: Modulated pulse

[0149] P60: Initial Pulse Wave

[0150] P61~P63: Modulated Pulse Waves

[0151] P64: Pulse Wave

[0152] P80: Pulse Wave

[0153] P81~P83: Modulated Pulse Waves

[0154] P91~P93: Modulated Pulse Waves

[0155] P94: Pulse Wave

[0156] R1, R2: Resistors

[0157] R15: Charging-side resistor

[0158] R16: Discharge side resistance

[0159] R31~R33: Reference resistors

[0160] S11~S15, S21~S25: Steps

[0161] S30: Sensing voltage signal

[0162] S31~S33: Comparison signals

[0163] S34: Trigger signal

[0164] S35: Reset signal

[0165] S36: Determine the signal

[0166] S37: Switching signal

[0167] S38: Transition Detection Signal

[0168] S39: Indicating signal

[0169] S40: Control signal

[0170] SCH: Charging control signal

[0171] SD11, SD21~SD23: Elevator section

[0172] SDG: Discharge control signal

[0173] SH11~SH13: Horizontal line segment indicating charging stop

[0174] SH21~SH23: Horizontal segment where discharge has stopped

[0175] SU11~SU13、SU21: Charging elevator section

[0176] SW1, SW2: Switches

[0177] SW11: Charging switch

[0178] SW13: Discharge switch

[0179] SWa, SWb, SWc, SWd: Control signals

[0180] t0: Ideal interval time

[0181] t11, t12, t13, t21, t22, t23: Actual interval time

[0182] Tideal: Ideal Time

[0183] Toff: Fixed off time

[0184] Ton: Fixed conduction time

[0185] V31~V33: Reference voltage

[0186] VCg: Gate capacitance voltage signal

[0187] VCC, VBAT, VDD: Power supply voltage

[0188] VGS: Actual gate-source voltage / Actual voltage difference

[0189] VGSTG: Ideal Voltage Difference

[0190] Vsaw: Reference voltage signal

[0191] Vstate: State signal

[0192] Δt11~Δt13: Time difference

[0193] Δt21~Δt23: Time difference.

Claims

1. An electronic circuit employing intermittent charging and discharging, characterized in that, Include: The control circuit generates a charging control signal. The power stage circuit receives voltage signals; and A charging circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the charging control signal; During the first period, the control circuit controls the charging circuit to charge the power stage circuit multiple times during multiple working periods of multiple consecutive pulses of the charging control signal, so as to generate multiple first charging steps of the rising wave of the voltage signal. During the first period, the control circuit controls the charging circuit to stop charging the power stage circuit during multiple non-working periods of multiple consecutive pulses of the charging control signal, so that the voltage signal generates a stop charging horizontal line segment or a first release elevator segment between two of the multiple first charging elevator segments.

2. The electronic circuit employing intermittent charging and discharging according to claim 1, characterized in that, The control circuit also generates a discharge control signal, and the electronic circuit employing intermittent charging and discharging further includes: The discharge circuit is coupled to the power stage circuit and the control circuit, and is controlled by the control circuit according to the discharge control signal; During the second period following the first period, the control circuit controls the charging circuit to discharge the power stage circuit multiple times during multiple working periods of multiple consecutive pulses of the discharge control signal, so that multiple second discharge stages with falling wave bands are generated in the voltage signal respectively. During the second period, the control circuit controls the discharge circuit to stop discharging the power stage circuit during multiple non-operating periods of the multiple pulses of the discharge control signal, so that the voltage signal generates a stop discharge horizontal line segment or a second charging line segment between each two of the multiple second discharge elevator segments.

3. The electronic circuit employing intermittent charging and discharging according to claim 2, characterized in that, The discharge circuit includes: The discharge-side current source circuit is coupled to the power stage circuit; and A discharge switch, wherein a first terminal of the discharge switch is coupled to the discharge-side current source circuit, a second terminal of the discharge switch is coupled to the ground terminal, and a control terminal of the discharge switch is coupled to the control circuit to receive the discharge control signal; as well as When the discharge switch is turned on according to the discharge control signal, the discharge-side current source circuit provides discharge current toward the ground terminal through the discharge switch to discharge the power stage circuit.

4. The electronic circuit employing intermittent charging and discharging according to claim 2, characterized in that, The power stage circuit includes: A first capacitor, the first terminal of which is coupled to the charging circuit and the discharging circuit at the input terminal of the power stage circuit, and the second terminal of which is coupled to ground; and A power transistor, wherein a first terminal of the power transistor is coupled to a first power supply voltage, a second terminal of the power transistor is coupled to the ground terminal, and a control terminal of the power transistor is coupled to the input terminal; The voltage signal is generated at the input terminal.

5. The electronic circuit employing intermittent charging and discharging according to claim 1, characterized in that, The charging circuit includes: Charging-side current source circuit; and A charging switch, wherein a first terminal of the charging switch is coupled to the charging-side current source circuit, a second terminal of the charging switch is coupled to the power stage circuit, and a control terminal of the charging switch is coupled to the control circuit to receive the charging control signal; When the charging switch is turned on according to the charging control signal, the charging side current source circuit provides charging current that flows through the charging switch to the power stage circuit to charge the power stage circuit.

6. The electronic circuit employing intermittent charging and discharging according to claim 4, characterized in that, The control circuit includes: A first comparator receives a first reference voltage signal at its first input terminal and a status signal at its second input terminal. The first comparator compares the first reference voltage signal with the status signal to generate a switching signal at its output terminal, wherein the status signal indicates the changing state of the voltage difference between the control terminal and the second terminal of the power transistor. as well as The output circuit receives the switching signal and outputs the switching signal as the charging control signal or the discharging control signal.

7. The electronic circuit employing intermittent charging and discharging according to claim 6, characterized in that, The control circuit also includes: A sensing comparison circuit receives a sensed voltage signal and is configured to compare the sensed voltage signal with a plurality of second reference voltages to output a plurality of comparison signals, wherein the sensed voltage signal represents the voltage difference of the power transistor; The judgment circuit receives multiple comparison signals, configures itself to determine the time difference between the time when the sensed voltage signal reaches each of the second reference voltages and the time threshold value based on the multiple comparison signals, and generates a trigger signal accordingly. as well as A signal generation circuit receives the trigger signal and generates the status signal, configured to control the level of the status signal based on the trigger signal.

8. The electronic circuit employing intermittent charging and discharging according to claim 7, characterized in that, The sensing comparison circuit includes: A sensing circuit configured to sense the voltage difference of the power transistors to output the sensed voltage signal; as well as A plurality of second comparators are provided, with the first input terminal of each second comparator coupled to the sensing circuit to receive the sensing voltage signal, the second input terminals of the plurality of second comparators being respectively coupled to a plurality of second reference voltages, and the plurality of output terminals of the plurality of second comparators respectively outputting a plurality of comparison signals; as well as Multiple reference resistors are connected in series between the second power supply voltage and the ground terminal; The second power supply voltage is one of the second reference voltages; The plurality of reference resistors include a first reference resistor and a second reference resistor, and the voltage at a common node between the first reference resistor and the second reference resistor is another of the second reference voltages.

9. The electronic circuit employing intermittent charging and discharging according to claim 7, characterized in that, The signal generation circuit includes: A first switch, the first end of the first switch being coupled to the second input of the first comparator at the first node, and the control end of the first switch receiving the trigger signal; An input current source is provided, wherein a first terminal of the input current source is coupled to a second terminal of the first switch, and the second terminal of the input current source is coupled to the ground terminal, wherein when the first switch is turned on according to the trigger signal, the input current source circuit provides current to the first node through the first switch; as well as An input capacitor, wherein a first end of the input capacitor is coupled to the first node, and a second end of the input capacitor is coupled to the ground terminal, wherein the status signal is generated at the first node; as well as A second switch, the first end of which is coupled to the first node, and the second end of which is coupled to the grounding terminal; The determination circuit generates a reset signal, and the control terminal of the second switch receives the reset signal. At intervals equal to the time threshold value, the determination circuit enables the reset signal to turn on the second switch.

10. The electronic circuit employing intermittent charging and discharging according to claim 6, characterized in that, The on / off state of the power transistor in the power stage circuit is controlled by the voltage signal, the indication signal indicates the on / off state of the power transistor, and the control circuit further includes: A transition detection circuit receives the indication signal and is configured to detect the rising edge and falling edge of the indication signal to output a transition detection signal. Whenever the state transition detection circuit detects the rising edge of the indication signal, the state transition detection circuit outputs the state transition detection signal to control the output circuit to output the switching signal as the charging control signal; Whenever the state transition detection circuit detects the falling edge of the indicator signal, the state transition detection circuit outputs the state transition detection signal to control the output circuit to output the switching signal as the discharge control signal.

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