Power amplifier, chip and radio frequency front-end module

Abstract

The utility model relates to the technical field of radio frequency, in particular to a power amplifier, a chip and a radio frequency front end module, the power amplifier comprises a first signal input port, a signal output port and a power amplification circuit, the first signal input port and the signal output port are distributed along a first straight line, the first signal input port is used for receiving a radio frequency signal, and the signal output port is used for receiving the radio frequency signal; the first signal output port is used for outputting the radio frequency signal amplified by the power amplification circuit; the power amplification circuit comprises a plurality of transistor units which are sequentially arranged along a first direction intersected with a first straight line; the capacitor units are sequentially arranged in the first direction and are in one-to-one correspondence with the transistor units in the second direction, one end of each capacitor unit is connected to the first signal input port, and the other end of each capacitor unit is connected to the corresponding transistor unit; and the capacitance values of the capacitor units are sequentially reduced in the first direction along the direction far away from the first straight line. According to the invention, the input impedance of all transistor units can be consistent.

Description

Technical Field

[0001] This application relates to the field of radio frequency technology, and in particular to a power amplifier, a chip, and a radio frequency front-end module. Background Technology

[0002] In power amplifiers, multiple transistors connected in parallel are typically used to increase output power. Each transistor has a DC blocking capacitor between its gate and the RF input terminal to prevent bias signals from leaking to the RF input terminal. The connection line between the RF input terminal and each DC blocking capacitor has parasitic inductance. Because the path lengths between each capacitor and the RF input terminal are different, and the magnitudes of the parasitic inductances are inconsistent, the input impedance of the transistors becomes inconsistent, affecting the performance of the power amplifier. Utility Model Content

[0003] In view of the above problems, embodiments of this application provide a power amplifier, a chip, and an RF front-end module to solve the above technical problems.

[0004] This application provides a power amplifier, including a first signal input port, a signal output port, and a power amplification circuit connected between the first signal input port and the signal output port. The first signal input port and the signal output port are distributed along a first straight line. The first signal input port is used to receive a radio frequency (RF) signal, and the first signal output port is used to output the RF signal amplified by the power amplification circuit. The power amplification circuit includes:

[0005] Multiple transistor units are arranged sequentially along a first direction intersecting the first straight line; and

[0006] Multiple capacitor units are arranged sequentially along the first direction and correspond one-to-one with the multiple transistor units in the second direction. One end of each capacitor unit is connected to the first signal input port and the other end is connected to the corresponding transistor unit.

[0007] In the first direction, along the direction away from the first straight line, the capacitance value of the capacitor unit decreases sequentially.

[0008] Optionally, the transistor unit includes a single transistor;

[0009] The capacitor unit includes a capacitor;

[0010] The capacitor has its first terminal connected to the first signal input port, its second terminal connected to the first terminal of the transistor, its second terminal connected to the signal output port, and its third terminal grounded.

[0011] Optionally, the transistor unit includes a plurality of transistors, which are arranged sequentially along the first direction;

[0012] The capacitor unit includes multiple capacitors with equal capacitance values, and the multiple capacitors are arranged sequentially along the first direction and are arranged one-to-one with the transistors in the second direction;

[0013] The capacitor has its first terminal connected to the first signal input port, its second terminal connected to the first terminal of the corresponding transistor, its second terminal connected to the signal output port, and its third terminal grounded.

[0014] Optionally, the number of capacitors in each capacitor unit is equal.

[0015] Optionally, each capacitor unit includes two or three capacitors.

[0016] Optionally, the capacitance value of the capacitor is greater than or equal to 0.2pF.

[0017] Optionally, the distance between the second terminal of each capacitor and the first terminal of the corresponding transistor is equal.

[0018] Optionally, the difference in capacitance values ​​between any two adjacent capacitor cells is equal.

[0019] Optionally, the signal input port, the power amplifier circuit, and the signal output port are arranged sequentially along the first straight line.

[0020] Optionally, the plurality of transistor units are arranged symmetrically about the first linear axis, and the plurality of capacitor units are arranged symmetrically about the first linear axis.

[0021] Optionally, the power amplifier further includes a second signal input port, and the first end of the transistor is also connected to the second signal input port, which is used to receive a bias signal and is located on the first straight line.

[0022] Optionally, the power amplifier is integrated into a chip, the chip including a substrate and a first metal layer and a second metal layer disposed on the substrate, wherein the first signal input port and the first end of the capacitor are located on the first metal layer, and the second signal input port and the second end of the capacitor unit are located on the second metal layer and connected to the first end of the transistor.

[0023] Optionally, the power amplifier includes at least two power amplifier circuits, wherein the two power amplifier circuits include a first power amplifier circuit and a second power amplifier circuit;

[0024] The radio frequency signal output by the first power amplifier circuit and the radio frequency signal output by the second power amplifier circuit are a pair of differential signals, and the first power amplifier circuit and the second power amplifier circuit are arranged sequentially along the first direction.

[0025] This application provides a chip that includes the power amplifier provided in any of the above embodiments.

[0026] This application provides an RF front-end module, including the power amplifier or the chip provided in any of the above embodiments.

[0027] The power amplifier, chip, and RF front-end module provided in this application embodiment include a first signal input port, a signal output port, and a power amplification circuit connected between the first signal input port and the signal output port. The first signal input port and the signal output port are distributed along a first straight line. The first signal input port is used to receive RF signals, and the first signal output port is used to output RF signals amplified by the power amplification circuit. The power amplification circuit includes multiple transistor units arranged sequentially along a first direction intersecting the first straight line; and multiple capacitor units arranged sequentially along the first direction and corresponding one-to-one with the multiple transistor units in a second direction. One end of each capacitor unit is connected to the first signal input port, and the other end is connected to the corresponding transistor unit. The capacitance value of the capacitor units decreases sequentially along the direction away from the first straight line in the first direction. By reducing the capacitance value of the capacitor units sequentially along the direction away from the first straight line in the first direction, the influence of parasitic inductance differences on the input impedance can be effectively reduced, ensuring that the input impedance of all transistor units is consistent, thereby improving the performance of the power amplifier.

[0028] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0029] Figure 1 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0030] Figure 2 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0031] Figure 3 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0032] Figure 4 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0033] Figure 5 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0034] Figure 6 A partial structural schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0035] Figure 7 A schematic diagram of the power amplifier provided in an embodiment of this application is shown.

[0036] Figure 8 A structural block diagram of the chip provided in an embodiment of this application is shown.

[0037] Figure 9 A structural block diagram of the radio frequency front-end module provided in an embodiment of this application is shown.

[0038] Figure 10 A structural block diagram of the radio frequency front-end module provided in an embodiment of this application is shown. Detailed Implementation

[0039] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0040] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0042] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0044] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0045] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0046] One embodiment of this application provides a power amplifier 100, including a first signal input port 110, a signal output port 120, and a power amplification circuit 130. Please refer to... Figure 1 As shown. A first signal input port 110 and a signal output port 120 are distributed along a first straight line L. The first signal input port 110 is used to receive radio frequency (RF) signals, and a power amplifier circuit 130 is used to amplify the RF signals input from the first signal input port 110. The first signal output port 120 is used to output the RF signals amplified by the power amplifier circuit 130. The power amplifier circuit 130 is connected between the first signal input port 110 and the signal output port 120, and includes multiple transistor units 131 and multiple capacitor units 132. The multiple transistor units 131 are arranged sequentially along a first direction, which intersects the first straight line L. The multiple capacitor units 132 are arranged sequentially along the first direction, and each capacitor unit 132 corresponds one-to-one with a transistor unit 131 in a second direction. One end of each capacitor unit 132 is connected to the first signal input port 110, and the other end of each capacitor unit 132 is connected to the corresponding transistor unit 131. In the first direction, along the direction away from the first straight line L, the capacitance value of the capacitor unit 132 decreases sequentially.

[0047] In this embodiment, the first signal input port 110 and the signal output port 120 are distributed along the first straight line L. Transistor units 131 are sequentially arranged along a first direction intersecting the first straight line L. Capacitor units 132 are arranged in a one-to-one correspondence with the transistor units 131. Therefore, in the first direction away from the first straight line L, the connecting line 140 between the capacitor unit 132 and the first signal input port 110 gradually becomes longer, and the parasitic inductance of the connecting line 140 also gradually increases. However, in this embodiment, the capacitance value of the capacitor unit 132 decreases sequentially in the first direction away from the first straight line L, which can effectively reduce the impact of differences in parasitic inductance on the input impedance, making the input impedance of all transistor units 131 consistent, thereby improving the performance of the power amplifier.

[0048] In some implementation methods, please refer to Figure 2 Transistor unit 131 includes a transistor 1311, and capacitor unit 132 includes a capacitor 1321. The first terminal of capacitor 1321 is connected to the first signal input port 110, the second terminal of capacitor 1321 is connected to the first terminal of transistor 1311, the second terminal of transistor 1311 is connected to the signal output port 120, and the third terminal of transistor 1311 is grounded.

[0049] In this embodiment, the length of the connection line 140 between the first end of capacitor 1321 and the first signal input port 110 gradually increases in the first direction away from the first straight line L. Each capacitor unit 132 includes one capacitor 1321, and the capacitance value of each capacitor 1321 decreases successively in the first direction away from the first straight line L. That is, the longer the connection line 140 corresponding to capacitor 1321, the smaller the capacitance value of capacitor 1321 corresponding to transistor 1311. This can accurately reduce the influence of parasitic inductance differences on input impedance, making the input impedance of all transistors 1311 more consistent.

[0050] As one implementation method, please refer to Figure 2 The third terminal of transistor 1311 can be directly grounded. That is, there are only necessary connections (bonding wires or bumps) and traces between the third terminal of transistor 1311 and the ground terminal. For example, the third terminal of transistor 1311 can be connected to the ground terminal on the substrate via bonding wires, or the third terminal of transistor 1311 can be connected to a conductive bump on the chip, and then connected to the ground terminal on the substrate via the bump after the chip is mounted on the substrate.

[0051] As another implementation, the third terminal of transistor 1311 can be indirectly grounded. For example, the third terminal of transistor 1311 can be grounded through a matching circuit or a harmonic suppression circuit. That is, inductors, capacitors, or other components can be provided between the third terminal of transistor 1311 and the ground terminal to form an impedance matching circuit or a harmonic suppression circuit. In this case, the third terminal of transistor 1311 can first be connected to inductors, capacitors, or other components, and then connected to the ground terminal on the substrate via a bump or bonding wire; alternatively, the third terminal of transistor 1311 can first be connected to capacitors, inductors, or other components on the substrate via a bump or bonding wire, and then grounded.

[0052] In one implementation, transistor 1311 can be a heterojunction bipolar transistor (HBT). The first terminal of transistor 1311 can be the base, the second terminal can be the collector, and the third terminal can be the emitter. For example, transistor 1311 can be a heterojunction bipolar transistor fabricated using GaAs (gallium arsenide) technology.

[0053] In other embodiments, transistor 1311 can also be other types of transistors, such as a bipolar junction transistor (BJT), a field-effect transistor (FET), etc. Optionally, the FET can be a metal-semiconductor FET based on GaN (gallium nitride) or SiC (silicon carbide), or a metal-oxide-semiconductor FET based on a Si (silicon) substrate.

[0054] In some implementation methods, please refer to Figure 3 Each transistor unit 131 includes multiple transistors 1311, all of which are arranged sequentially along a first direction. Each capacitor unit 132 includes multiple capacitors 1321, all of which have the same capacitance value. The multiple capacitors 1321 are arranged sequentially along the first direction, and each capacitor 1321 corresponds to a transistor 1311 in a second direction. The first terminal of each capacitor 1321 is connected to a first signal input port 110, the second terminal of each capacitor 1321 is connected to the first terminal of the corresponding transistor 1311, the second terminal of each transistor 1311 is connected to a signal output port 120, and the third terminal of each transistor 1311 is grounded.

[0055] In this embodiment, each transistor unit 131 includes a plurality of transistors 1311. The capacitance values ​​of the capacitors 1321 corresponding to the transistors 1311 in the same transistor unit 131 can be set to equal values, thereby effectively simplifying the design while reducing the impact of parasitic inductance differences on input impedance.

[0056] In some implementation methods, please refer to Figure 3 The fact that each capacitor unit 132 contains an equal number of capacitors 1321 not only effectively simplifies the structure, but more importantly, it allows the distance from the first end of multiple capacitor units 132 to the first signal input port 110 to decrease uniformly and gradually. This results in a uniform and gradual decrease in parasitic inductance, precisely reducing the impact of differences in parasitic inductance on the input impedance, and making the input impedance of all transistors 1311 more consistent. Here, the distance from the first end of capacitor unit 132 to the first signal input port 110 refers to the average distance from the first end of all capacitors 1321 in capacitor unit 132 to the first signal input port 110.

[0057] In some embodiments, the number of capacitors included in the same capacitor unit 132 is less than or equal to four, so as to avoid the inductance values ​​of the parasitic inductance of the connection line 140 corresponding to different capacitors 1321 in the same capacitor unit 132 being too different, thereby ensuring that the consistency of the input impedance of all transistors 1311 can meet the requirements.

[0058] As one implementation method, please refer to Figure 4 Each capacitor unit 132 may include three capacitors 1321, which can not only effectively simplify the structure and reduce the design cost, but also make the difference between the inductance values ​​of the parasitic inductance of the connection line 140 corresponding to different transistors 1311 in the same transistor unit 131 smaller, thereby making the input impedance of all transistors 1311 more consistent.

[0059] As one implementation method, please refer to Figure 3 Each capacitor unit 132 may include two capacitors 1321, which can not only effectively simplify the structure and reduce the design cost, but also further reduce the difference in inductance value between the parasitic inductance of the connecting line 140 corresponding to different capacitors 1321 in the same capacitor unit 132, thereby further ensuring that the input impedance of all transistors 1311 can be more consistent.

[0060] In one implementation, the capacitance value of capacitor 1321 is greater than or equal to 0.2pF, so that the capacitance value of capacitor 1321 is less affected by process errors.

[0061] In some implementation methods, please refer to Figures 2 to 4The distance between the second end of each capacitor 1321 and the first end of the corresponding transistor 1311 is equal, which makes the parasitic capacitance between each capacitor 1321 and the first end of the corresponding transistor 1311 consistent, thereby further ensuring that the input impedance of the transistor 1311 can be more consistent.

[0062] In some implementations, the difference in capacitance values ​​between any two adjacent capacitor units 132 is equal, which can effectively simplify the structure and reduce design costs.

[0063] For example, each capacitor unit 132 includes a plurality of capacitors 1321, and the number of capacitors 1321 included in each capacitor unit 132 is the same. Specifically, the capacitance values ​​of all capacitors 1321 in the same capacitor unit 132 are equal. That is, the difference between the capacitance value of any capacitor 1321 in one capacitor unit 132 and the capacitance value of any capacitor 1321 in an adjacent capacitor unit 132 is equal.

[0064] In some implementation methods, please refer to Figures 1 to 4 The signal input port, power amplifier circuit 130, and signal output port 120 are arranged sequentially along the first straight line L, which makes the layout easier and can prevent the power amplifier circuit 130 from interfering with the connection of the first signal input port 110 or the signal output port 120 to other functional modules.

[0065] In some implementation methods, please refer to Figures 1 to 4 Multiple transistor units 131 are symmetrically arranged about the first straight line L axis. Correspondingly, multiple capacitor units 132 are symmetrically arranged about the first straight line L axis. Compared with multiple capacitor units 132 being arranged on the same side of the first straight line L, the maximum distance between capacitor units 132 and the first signal input port 110 can be reduced. This effectively reduces the difference in capacitance between the capacitor with the largest capacitance value 1321 and the capacitor with the smallest capacitance value 1321, ensuring that the capacitance value in the capacitor unit 132 farthest from the first straight line L is not too small, and more effectively reducing the impact of process errors on the power amplifier 100.

[0066] As one implementation method, please refer to Figures 1 to 4 The first direction is perpendicular to the first straight line L, and the second direction is parallel to the first straight line L, which makes the layout of the power amplifier 100 more compact and can also effectively reduce parasitic inductance.

[0067] In some implementation methods, please refer to Figure 5The power amplifier 100 also includes a second signal input port 150. The first end of the transistor 1311 is also connected to the second signal input port 150. The second signal input port 150 is used to input a bias signal. Furthermore, the second signal input port 150 is located on the first straight line L, which can make each transistor 1311 obtain similar bias conditions as much as possible. This helps to reduce performance differences caused by inconsistent bias, making the operation of the entire circuit more uniform and stable.

[0068] In one implementation, the power amplifier 100 is integrated into a chip, which includes a substrate 210, a first metal layer 220, and a second metal layer 230, which are respectively disposed on the substrate 210. Please refer to... Figure 6 The first signal input port 110 is located on the first metal layer 220, and the first terminal 1321a of the capacitor 1321 is located on the first metal layer 220. The second signal input port 150 is located on the second metal layer 230, and the second terminal 1321b of the capacitor unit 132 is located on the second metal layer 230. Furthermore, the second signal input port 150 and the second terminal 1321b of the capacitor unit 132 are connected to the first terminal 1311a of the transistor 1311.

[0069] In this embodiment, the first signal input port 110 and the second signal input port 150 are on different metal layers. Therefore, the projections of the first signal input port 110 and the second signal input port 150 in the direction perpendicular to the substrate 210 can overlap. That is, the first signal input port 110 and the second signal input port 150 are both located on the first straight line L. This can make the input impedance and bias of each transistor 1311 as consistent as possible, making the operation of the entire circuit more uniform and stable.

[0070] It should be noted that this application does not limit the vertical order of the first metal layer 220 and the second metal layer 230. For example, the first metal layer 220 may be closer to the substrate 210 than the second metal layer 230, or the first metal layer 220 may be farther away from the substrate 210 than the second metal layer 230. The arrangement can be determined according to the actual situation and is not limited here.

[0071] In some implementation methods, please refer to Figure 7The power amplifier 100 includes at least two power amplifier circuits 130. Each power amplifier circuit 130 includes a first power amplifier circuit 130a and a second power amplifier circuit 130b. Correspondingly, the power amplifier 100 includes at least two first signal input ports, such as first signal input ports 110a and 110b; the power amplifier 100 also includes at least two output ports, such as signal output ports 120a and 120b. The first signal input port 110a and the signal output port 120a are distributed along a first straight line L1a corresponding to the first power amplifier circuit 130a, and the power amplifier circuit 130a is connected between the first signal input port 110a and the signal output port 120a. The first signal input port 110b and the signal output port 120b are distributed along a first straight line L1b corresponding to the second power amplifier circuit 130b, and the power amplifier circuit 130b is connected between the first signal input port 110b and the signal output port 120b.

[0072] Optionally, the first power amplifier circuit 130a and the second power amplifier circuit 130b may not be connected to each other in order to amplify two different radio frequency signals, such as two radio frequency signals of different frequency bands.

[0073] Optionally, the first power amplifier circuit 130a and the second power amplifier circuit 130b can be connected to form a differential amplifier circuit, thereby amplifying the differential radio frequency signal. That is, the radio frequency signal output by the first power amplifier circuit 130a and the radio frequency signal output by the second power amplifier circuit 130b are a pair of differential signals. Optionally, the two output terminals of the differential amplifier circuit are also used to connect to a balun to convert the differential signal into a single-ended signal for easy reception by subsequent circuits. Typically, the balun includes a primary winding and a secondary winding. For example, the signal output port 120a of the first power amplifier circuit 130a is connected to one end of the primary winding of the output balun, and the signal output port 120b of the second power amplifier circuit 130b is connected to the other end of the primary winding of the output balun. In the differential amplifier circuit, the first power amplifier circuit 130a and the second power amplifier circuit 130b are arranged sequentially along the first direction. For example, each transistor in the first power amplifier circuit 130a and each transistor in the second power amplifier circuit 130b are arranged on the same straight line along the first direction. This not only facilitates the connection of the power amplifier 100 to other functional modules such as baluns, making the layout more reasonable, but also makes the distance between the first power amplifier circuit 130a and the balun the same as the distance between the second power amplifier circuit 130b and the balun, thus improving the balance of the power amplifier.

[0074] Please refer to Figure 7The first power amplifier circuit 130a and the second power amplifier circuit 130b can be used as the last stage of power amplifier circuit. The signal output ports 120a of the first power amplifier circuit 130a and 120b of the second power amplifier circuit 130b can be arranged close to the edge of the chip 200, which makes it easier to connect other functional modules and facilitates layout.

[0075] One embodiment of this application provides a chip 200, including the power amplifier 100 provided in any of the above embodiments. Please refer to [reference needed]. Figure 8 .

[0076] In this embodiment, the first signal input port 110 and the signal output port 120 are distributed along the first straight line L, and the transistor units 131 are sequentially arranged along the first direction intersecting the first straight line L. Therefore, in the first direction away from the first straight line L, the connecting line 140 between the capacitor unit 132 and the first signal input port 110 gradually becomes longer, and the parasitic inductance of the connecting line 140 also gradually increases. In this embodiment, the capacitance value of the capacitor unit 132 decreases sequentially in the first direction away from the first straight line L, which can effectively reduce the influence of parasitic inductance on the input impedance, so that the input impedance of all transistor units 131 can be consistent.

[0077] One embodiment of this application provides a radio frequency front-end module 300, including the power amplifier 100 provided in any of the above embodiments. Please refer to [link / reference needed]. Figure 9 .

[0078] In this embodiment, the first signal input port 110 and the signal output port 120 are distributed along the first straight line L, and the transistor units 131 are sequentially arranged along the first direction intersecting the first straight line L. Therefore, in the first direction away from the first straight line L, the connecting line 140 between the capacitor unit 132 and the first signal input port 110 gradually becomes longer, and the parasitic inductance of the connecting line 140 also gradually increases. In this embodiment, the capacitance value of the capacitor unit 132 decreases sequentially in the first direction away from the first straight line L, which can effectively reduce the influence of parasitic inductance on the input impedance, so that the input impedance of all transistor units 131 can be consistent.

[0079] One embodiment of this application provides a radio frequency front-end module 400, including the chip 200 provided in any of the above embodiments. Please refer to [the relevant documentation]. Figure 10 .

[0080] In this embodiment, the first signal input port 110 and the signal output port 120 are distributed along the first straight line L, and the transistor units 131 are sequentially arranged along the first direction intersecting the first straight line L. Therefore, in the first direction away from the first straight line L, the connecting line 140 between the capacitor unit 132 and the first signal input port 110 gradually becomes longer, and the parasitic inductance of the connecting line 140 also gradually increases. In this embodiment, the capacitance value of the capacitor unit 132 decreases sequentially in the first direction away from the first straight line L, which can effectively reduce the influence of parasitic inductance on the input impedance, so that the input impedance of all transistor units 131 can be consistent.

[0081] The above description is merely an embodiment of this application. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of this application, but these improvements all fall within the protection scope of this application.

Claims

1. A power amplifier, characterized by, The power amplifier comprises a first signal input port, a signal output port, and a power amplification circuit connected between the first signal input port and the signal output port, the first signal input port and the signal output port are distributed along a first straight line, the first signal input port is configured to receive a radio frequency signal, and the signal output port is configured to output the radio frequency signal amplified by the power amplification circuit, the power amplification circuit comprises: a plurality of transistor units arranged in sequence along a first direction intersecting the first straight line; and a plurality of capacitor units arranged in sequence along the first direction and corresponding to the plurality of transistor units in a second direction, one end of the capacitor unit being connected to the first signal input port and the other end being connected to the corresponding transistor unit. In the first direction, the capacitance of the capacitor unit decreases in sequence in the direction away from the first straight line.

2. The power amplifier of claim 1, wherein, The transistor unit comprises one transistor. The capacitor unit comprises one capacitor. The first end of the capacitor is connected to the first signal input port, the second end of the capacitor is connected to the first end of the transistor, the second end of the transistor is connected to the signal output port, and the third end of the transistor is configured to be grounded.

3. The power amplifier of claim 1, wherein, The transistor unit comprises a plurality of transistors arranged in sequence along the first direction. The capacitor unit comprises a plurality of capacitors with equal capacitance, and the plurality of capacitors are arranged in sequence along the first direction and correspond to the transistors in the second direction. The first end of the capacitor is connected to the first signal input port, the second end of the capacitor is connected to the first end of the corresponding transistor, the second end of the transistor is connected to the signal output port, and the third end of the transistor is configured to be grounded.

4. The power amplifier of claim 3, wherein, The number of capacitors in each capacitor unit is equal.

5. The power amplifier of claim 3, wherein, Each capacitor unit comprises two capacitors or three capacitors.

6. The power amplifier of any one of claims 2-5, wherein, The capacitance of the capacitor is greater than or equal to 0.2 pF.

7. The power amplifier of any one of claims 2-5, wherein, The distance between the second end of each capacitor and the first end of the corresponding transistor is equal.

8. The power amplifier of any one of claims 2-5, wherein, In each adjacent two capacitor units, the difference between the capacitances of the capacitors is equal.

9. The power amplifier of claim 1, wherein, The signal input port, the power amplification circuit, and the signal output port are arranged in sequence along the first straight line.

10. The power amplifier of claim 1, wherein, The plurality of transistor units are arranged symmetrically about the first straight line, and the plurality of capacitor units are arranged symmetrically about the first straight line.

11. The power amplifier of any one of claims 2-5, wherein, The power amplifier is integrated in a chip, the chip comprises a substrate and a first metal layer and a second metal layer arranged on the substrate, the first signal input port and the first end of the capacitor are located on the first metal layer, and the second signal input port and the second end of the capacitor unit are located on the second metal layer and connected to the first end of the transistor.

12. The power amplifier of claim 11, wherein, The power amplifier comprises at least two power amplification circuits, wherein the two power amplification circuits comprise a first power amplification circuit and a second power amplification circuit.

13. The power amplifier of claim 1, wherein, ​ The radio frequency signal output by the first power amplifier circuit and the radio frequency signal output by the second power amplifier circuit are a pair of differential signals, and the first power amplifier circuit and the second power amplifier circuit are arranged in sequence along the first direction.

14. A chip, characterized by Comprising: The power amplifier of any one of claims 1 to 13.

15. A radio frequency front end module, comprising: Comprising: The power amplifier of any one of claims 1 to 13 or the chip of claim 14.

Images