Self-latching control circuit

Abstract

The utility model discloses a self-latching control circuit which is composed of a latching module, a reset module and a filtering module. Wherein the latch module is composed of two NAND gate electronic components, namely a NAND gate U25 and a NAND gate U26; the reset module is composed of a resistor and a capacitor, the resistor and the capacitor form a time delay circuit, namely a resistor R147 and a capacitor C80, and stable output is ensured when the system is started; the problems that in the prior art, when a system is started, voltage is unstable, and a latch is prone to being triggered by mistake are solved, the problem that after an abnormal state is relieved, the latch is possibly reset accidentally, and misoperation is caused is solved, the anti-interference capacity is high, signal fluctuation is reduced through a filter capacitor, stability is improved, and the reliability of the system is improved. The double-NAND gate structure ensures that an abnormal state is locked, secondary triggering is avoided, through charging delay of the R147 and the C80, it is ensured that a high level is output when the system is started, and false triggering is avoided.

Description

TECHNICAL FIELD

[0001] The utility model relates to the electronic circuit technical field of printer, specifically related to a self-locking control circuit for digital inkjet printer. BACKGROUND

[0002] In the digital inkjet printer, the state latch circuit is used for locking the equipment abnormal state (such as error signal), prevents system false triggering. The traditional SR latch has the following problems:

[0003] (1) power sequence problem: the voltage is unstable when the system starts, which can cause the latch to be false triggered;

[0004] (2) state locking is not complete: after the abnormal state is removed, the latch may be accidentally reset, causing false operation.

[0005] The prior art does not fully consider the power delay and the stability of state locking, resulting in insufficient device reliability. SUMMARY

[0006] The utility model discloses in order to solve above -mentioned technical problem, provide a self -latching control circuit, through optimizing power sequence and latching mechanism, ensure that the equipment is stable output high level when starting, the reliable latching low level under abnormal state, avoid false operation.

[0007] The technical scheme of the utility model is realized as follows:

[0008] A self-latching control circuit is composed of a latch module, a reset module and a filter module;

[0009] The latch module is composed of two NAND gate electronic elements, which are NAND gate U25 and NAND gate U26, respectively;

[0010] The reset module is composed of a resistor and a capacitor, and the resistor and the capacitor constitute a delay circuit, which are resistor R147 and capacitor C80, respectively, to ensure stable output when the system starts;

[0011] The filter module is composed of two filter capacitors, which are filter capacitor C90 and filter capacitor C84, respectively, for filtering signal ripple and improving stability;

[0012] It also includes a signal input end and a signal output end, and the input end and the signal output end are connected in parallel with the latch module, the reset module and the filter module.

[0013] The utility model discloses a latch control circuit, which solves the problem of unstable voltage during system startup in the prior art, which can easily cause the latch to be mis-triggered, and also solves the problem that the latch may be accidentally reset after the abnormal state is removed, which can cause misoperation, and the anti-interference ability is strong, the filter capacitor reduces signal fluctuation, improves stability, and the double NAND gate structure ensures abnormal state locking and avoids secondary triggering, and through the charging delay of R147 and C80, the output high level during system startup is ensured, and mis-triggering is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is a circuit structure schematic diagram of the utility model:

[0015] In the drawing:

[0016] U25-NAND gate integrated circuit, U26-NAND gate integrated circuit; R147-resistor; C80-reset capacitor; C20-filter capacitor; C84-filter capacitor: SIGNAL-signal input end; OVER-signal output end; 3V3-power supply; LED-LED drive circuit; LM393-comparator; TVS-transient voltage suppressor diode. DETAILED DESCRIPTION

[0017] As shown in Figure 1 the utility model discloses a kind of self-latch control circuits, which is composed of latch module, reset module and filter module;

[0018] Wherein, the latch module is composed of two NAND gate electronic components, which are NAND gate U25 and NAND gate U26 respectively;The reset module is composed of resistor and capacitor, and the resistor and capacitor constitute a delay circuit, which are resistor R147 and capacitor C80 respectively, to ensure stable output during system startup;The filter module is composed of two filter capacitors, which are filter capacitor C90 and filter capacitor C84 respectively, for filtering signal ripple and improving stability;It also includes signal input end and signal output end, and the input end and signal output end are connected in parallel with latch module, reset module and filter module.

[0019] Preferably, the signal output end is connected in parallel with a state visualization module, which includes an LED drive circuit and a comparator, so that the operator can determine the latch state without the aid of instruments, monitor the signal output end voltage in real time, and trigger the buzzer alarm when abnormal.

[0020] Preferably, the signal input end is connected in parallel with an anti-interference module, which is a transient voltage suppression diode, i.e., a TVS diode, which can absorb transient high voltage (such as static electricity and surge) to prevent circuit damage.

[0021] The LED driving circuit is connected in series with the comparator, is connected in parallel with the signal output end, and is connected to the signal output end.

[0022] Preferably, the NAND gate U25 and the NAND gate U26 form a latch, and the abnormal state is locked at a low level to prevent secondary triggering.

[0023] The utility model discloses a reset mechanism: after the power off of system, the delay circuit of reset module triggers again, and the signal output end OVER restores high level at this time.

[0024] At the initial power-on time: when the 3V3 power supply supplies power, the resistor R147 charges the capacitor C80, and a delay (such as 100 ms) is generated; during the delay period, the signal output end OVER outputs a high level, and the system is ensured to be stable before receiving signals.

[0025] In the normal working state of the circuit: the signal input end SIGNAL is at a high level, the NAND gate U25 input is at a high level, and the signal output end OVER outputs a high level; the filter capacitor C90 and the filter capacitor C84 filter out signal interference, and the output is ensured to be stable.

[0026] In the abnormal state of the latch: when the device reports an error, the signal input end SIGNAL becomes a low level; the NAND gate U25 outputs a low level, the NAND gate U26 input is at a low level, and the signal output end OVER becomes a low level and is latched;

[0027] At this time, even if the signal input end SIGNAL restores a high level, the latch still maintains the signal output end OVER at a low level, and false operation is avoided.

[0028] The reset mechanism of the utility model: after the power off of system, the delay circuit of reset module triggers again, and the signal output end OVER restores high level at this time.

[0029] The above only for the embodiment of the application, and does not limit the application. For those skilled in the art, the application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the application shall be included in the protection scope of the application.

Claims

1. A self-latching control circuit, characterized in that, It consists of a latch module, a reset module, and a filtering module; The latch module consists of two NAND gates, namely NAND gate U25 and NAND gate U26; The reset module consists of a resistor and a capacitor, which together form a delay circuit, namely resistor R147 and capacitor C80. The filtering module consists of two filtering capacitors, namely filtering capacitor C90 and filtering capacitor C84. It also includes a signal input terminal and a signal output terminal, which are connected in parallel with the latch module, the reset module and the filter module.

2. The self-latching control circuit according to claim 1, characterized in that, The signal output terminal is connected in parallel with the status visualization module, which includes an LED driving circuit and a comparator.

3. The self-latching control circuit according to claim 1, characterized in that, The signal input terminal is connected in parallel with the anti-interference module, which is a transient suppression diode.

4. The self-latching control circuit according to claim 2, characterized in that, The LED driver circuit is connected in series with the comparator and in parallel with the signal output terminal.

5. The self-latching control circuit according to claim 1, characterized in that, The NAND gates U25 and U26 constitute a latch.

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