Battery suitable for conductive backboard packaging process
By using a symmetrical cutting and staggered electrode point design, the problems of electrode point asymmetry and incorrect silicon wafer placement in the conductive backplane packaging process are solved, which improves production reliability and battery quality, enhances current distribution uniformity and mechanical stability, and extends battery life.
Patent Information
- Application Number
- CN202520342288.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-28
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-02-28
AI Technical Summary
In existing conductive backplane packaging processes, asymmetrical electrode positions or incorrect silicon wafer orientation can easily lead to component scrap, affecting production efficiency and quality.
A whole silicon wafer is cut into symmetrical first and second half-wafers, with electrode points arranged symmetrically vertically, main gate lines arranged in an alternating pattern, and sub-gate lines evenly distributed laterally to ensure uniform current collection and transmission.
This avoids component scrapping caused by electrode asymmetry or incorrect silicon wafer orientation, improves production reliability and cell rotational symmetry, enhances mechanical stability and current distribution uniformity, and extends cell life.
Smart Images
Figure CN223957904U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to photovoltaic cell technical field, concretely is a kind of cell suitable for conductive backboard packaging process. BACKGROUND
[0002] The current back contact crystalline silicon cell mainstream photovoltaic module packaging mode mainly has two kinds, one is solder strip mode, one is conductive backboard packaging process.The requirement of two kinds of technology to cell has certain difference, such as the position of cell electrode point, the electrode point position in half piece although there is certain flexibility, but when actual operation, to avoid the material placement error of production, leading to major production anomaly, the position of electrode point is preferably symmetrical in half piece: the insulating layer of conductive backboard and cell generally has opening, the insulating layer needs opening, to facilitate the electrode point of cell and conductive backboard through solder paste and form conductive contact, so that current can be introduced into conductive backplate from cell.In addition, the half piece used in the industry during assembly is often divided into AB piece, and if the operation is wrong during production, it will also cause unnecessary anomalies in production.
[0003] The electrode point of cell is often fine-tuned according to the specific position of cell grid line, to facilitate printing alignment and easy identification of whether to shift, which will cause the electrode point in half piece to be asymmetric up and down, and this design has little effect on welded assembly;when used for conductive backboard packaging assembly, it will affect the rotational symmetry of conductive backplate, and if the silicon wafer is placed in the wrong direction during production, the front and back of the silicon wafer will be reversed, rotating the silicon wafer direction by 180 degrees will cause the assembly to be scrapped. SUMMARY
[0004] In view of the deficiencies of the prior art, the utility model provides a kind of cell suitable for conductive backboard packaging process, solve the electrode point of cell, which is often fine-tuned according to the specific position of cell grid line, to facilitate printing alignment and easy identification of whether to shift, which will cause the electrode point in half piece to be asymmetric up and down, and this design has little effect on welded assembly;when used for conductive backboard packaging assembly, it will affect the rotational symmetry of conductive backplate, and if the silicon wafer is placed in the wrong direction during production, the front and back of the silicon wafer will be reversed, rotating the silicon wafer direction by 180 degrees will cause the assembly to be scrapped.
[0005] To achieve the above purpose, the utility model is realized by the following technical scheme: a kind of cell suitable for conductive backboard packaging process, comprising:
[0006] Whole silicon wafer, after cutting, form the first half silicon wafer and the second half silicon wafer of symmetrical arrangement;
[0007] Electrode point, multiple electrode points are arranged in a rectangular array on the first half silicon wafer and the second half silicon wafer, and multiple electrode points are symmetrically arranged up and down;
[0008] The main grid lines are longitudinally arranged on the first and second silicon wafers, and are used to bear the current transmission task, and the main grid lines comprise:
[0009] The positive electrode main grid is arranged outside the plurality of electrode points, and the plurality of positive electrode main grids are arranged in multiple columns.
[0010] The negative electrode main grid is arranged outside the plurality of electrode points, and the plurality of positive electrode main grids are arranged in multiple columns.
[0011] The sub-grid lines are arranged between the plurality of main grid lines, and are used to further refine the current collection area and ensure that the current on the surface of the battery piece is uniformly distributed.
[0012] Preferably, the plurality of electrode points are composed of peripheral electrode points at the front and rear direction edges and internal electrode points at the middle part.
[0013] Preferably, the peripheral electrode points are the same distance from the front and rear direction edges of the first and second silicon wafers, the distance between the peripheral electrode points and the adjacent internal electrode points in the front and rear direction is the same as the distance between the adjacent internal electrode points in the front and rear direction, and the distance between the adjacent peripheral electrode points in the left and right direction is the same as the distance between the adjacent internal electrode points in the left and right direction.
[0014] Preferably, the plurality of negative electrode main grids on the first silicon wafer correspond to the plurality of positive electrode main grids, and the plurality of positive electrode main grids on the second silicon wafer correspond to the plurality of negative electrode main grids.
[0015] Preferably, the negative electrode main grid is arranged in a line type structure with thick ends and a thin middle.
[0016] Preferably, the sub-grid lines comprise:
[0017] The positive electrode sub-grid is arranged in a transverse equidistant and uniform manner, and the positive electrode sub-grid is connected to the positive electrode main grid.
[0018] The negative electrode sub-grid is arranged in a transverse equidistant and uniform manner, and the negative electrode sub-grid is connected to the negative electrode main grid.
[0019] Preferably, the plurality of positive electrode sub-grids and the plurality of negative electrode sub-grids are arranged in an interleaved manner.
[0020] The utility model discloses a kind of batteries suitable for conductive backboard packaging process, it has the beneficial effects as follows: the battery suitable for conductive backboard packaging process, after cutting whole silicon chip, first half silicon chip and second half silicon chip of symmetrical arrangement are formed, while multiple electrode points are opened in rectangular array on first half silicon chip and second half silicon chip, and multiple electrode points are symmetrically arranged up and down, and then cancel AB piece in conventional production, so that the electrode point position on first half silicon chip and second half silicon chip is same, and then welding strip assembly and conductive backplate assembly can be used, and when used for conductive backplate assembly, conductive backplate rotates 180 in actual production ° It does not affect use, avoid the situation of mixed piece. BRIEF DESCRIPTION OF DRAWINGS
[0021] In order to more clearly illustrate the technical scheme in the above-mentioned embodiment or prior art, the drawings needed to be used in the following embodiment or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the utility model, and other drawings can be obtained by those skilled in the art without creative labor.
[0022] Figure 1 It is a whole structure schematic diagram of the utility model;
[0023] Figure 2 It is a structure schematic diagram of whole silicon chip and electrode point of the utility model;
[0024] Figure 3 It is a structure schematic diagram of negative electrode auxiliary grid of the utility model;
[0025] Figure 4 It is a structure schematic diagram of positive electrode main grid and positive electrode auxiliary grid of the utility model;
[0026] Figure 5 It is A part of the utility model Figure 2 in the enlarged schematic diagram.
[0027] In the drawing: 1, whole silicon chip;11, first half silicon chip;12, second half silicon chip;2, electrode point;21, peripheral electrode point;22, internal electrode point;3, main grid line;31, positive electrode main grid;32, negative electrode main grid;4, auxiliary grid line;41, positive electrode auxiliary grid;42, negative electrode auxiliary grid. DETAILED DESCRIPTION
[0028] In order to better understand the above technical scheme, the above technical scheme will be described in detail in combination with the drawings in the specification and specific embodiments.
[0029] Embodiment one
[0030] The utility model embodiment discloses a kind of batteries suitable for conductive backboard packaging process.
[0031] According to the accompanying drawings, it includes: Figures 1-5
[0032] The whole silicon wafer 1 is cut to form the first half silicon wafer 11 and the second half silicon wafer 12 arranged symmetrically;
[0033] The electrode points 2 are arranged in a rectangular array on the first half silicon wafer 11 and the second half silicon wafer 12, and the electrode points 2 are arranged symmetrically up and down;
[0034] The main grid lines 3 are arranged longitudinally on the first half silicon wafer 11 and the second half silicon wafer 12 to undertake the task of transmitting current, and the main grid lines 3 include:
[0035] The positive electrode main grid 31 is arranged outside the electrode points 2, and the positive electrode main grid 31 is arranged in multiple columns;
[0036] The negative electrode main grid 32 is arranged in multiple columns, and the multiple columns of negative electrode main grids 32 are arranged alternately with the multiple columns of positive electrode main grids 31;
[0037] The auxiliary grid lines 4 are arranged between the main grid lines 3 to further refine the current collection area and ensure that the current on the surface of the battery piece can be uniformly distributed.
[0038] The whole silicon wafer 1 is cut to form the first half silicon wafer 11 and the second half silicon wafer 12 arranged symmetrically, and the electrode points 2 are arranged in a rectangular array on the first half silicon wafer 11 and the second half silicon wafer 12, and the electrode points 2 are arranged symmetrically up and down, thereby canceling the AB piece in the conventional production, so that the electrode points 2 on the first half silicon wafer 11 and the second half silicon wafer 12 have the same position, thereby making the solder strip assembly and the conductive back plate assembly usable, and when used for the conductive back plate assembly, the conductive back plate is rotated by 180° in actual production without affecting the use, thereby avoiding the mixing of the pieces.
[0039] Embodiment two
[0040] The utility model embodiment discloses a battery suitable for conductive back plate packaging technology.
[0041] According to the accompanying drawings, it includes: Figures 1-5
[0042] The whole silicon wafer 1 is cut to form the first half silicon wafer 11 and the second half silicon wafer 12 arranged symmetrically;
[0043] The electrode points 2 are arranged in a rectangular array on the first half silicon wafer 11 and the second half silicon wafer 12, and the electrode points 2 are arranged symmetrically up and down;
[0044] The main grid line 3 is longitudinally arranged on the first and second silicon wafers 11 and 12 to undertake the task of transmitting current, and the main grid line 3 includes:
[0045] The positive electrode main grid 31 is arranged outside the plurality of electrode points 2, and the plurality of positive electrode main grids 31 are arranged in multiple columns.
[0046] The negative electrode main grid 32 is arranged in multiple columns, and the multiple columns of negative electrode main grids 32 are arranged alternately with the multiple columns of positive electrode main grids 31.
[0047] The alternating arrangement of the positive electrode main grid 31 and the negative electrode main grid 32 not only optimizes the transmission path of the current, but also enhances the mechanical stability and reliability of the battery. This design helps to reduce the risk of battery thermal runaway or damage caused by uneven current concentration or distribution, prolonging the service life of the battery.
[0048] The sub-grid line 4 is arranged between the plurality of main grid lines 3 to further refine the current collection area and ensure uniform distribution of current on the surface of the battery sheet.
[0049] Further, the plurality of electrode points 2 is composed of peripheral electrode points 21 at the front and rear edges and internal electrode points 22 at the middle part.
[0050] In particular, the peripheral electrode points 21 are the same distance from the front and rear edges of the first and second silicon wafers 11 and 12, the distance between the peripheral electrode points 21 and the adjacent internal electrode points 22 in the front and rear directions is the same as the distance between the adjacent internal electrode points 22 in the front and rear directions, and the distance between the adjacent peripheral electrode points 21 in the left and right directions is the same as the distance between the adjacent internal electrode points 22 in the left and right directions.
[0051] In particular, the plurality of columns of negative electrode main grids 32 on the first silicon wafer 11 are arranged correspondingly with the plurality of columns of positive electrode main grids 31, and the plurality of columns of positive electrode main grids 31 on the second silicon wafer 12 are arranged correspondingly with the plurality of columns of negative electrode main grids 32.
[0052] It should be particularly emphasized that the negative electrode main grid 32 is arranged in a line structure with thick ends and a thin middle.
[0053] In particular, the sub-grid line 4 includes:
[0054] The positive electrode sub-grid 41 is arranged transversely and equidistantly, and the positive electrode sub-grid 41 is connected to the positive electrode main grid 31.
[0055] The negative electrode sub-grid 42 is arranged transversely and equidistantly, and the negative electrode sub-grid 42 is connected to the negative electrode main grid 32.
[0056] Further, the plurality of positive electrode sub-grids 41 and the plurality of negative electrode sub-grids 42 are arranged alternately.
[0057] The current collecting area is further refined by the transversely equidistantly and uniformly arranged positive electrode sub-grid 41 and negative electrode sub-grid 42. This design helps to ensure that the current on the surface of the battery piece can be more uniformly and effectively collected, reducing the loss of current and resistance, thereby improving the overall efficiency of the battery.
[0058] It should be particularly emphasized that the size of the whole silicon wafer 1 in the embodiment is 182.2mm*183.75mm, the battery is designed with nine negative electrode main grids 32 and nine positive electrode main grids 31, the distance between the positive electrode main grid 31 and the negative electrode main grid 32 is 10.32mm, the whole silicon wafer 1 is cut to form the first half silicon wafer 11 and the second half silicon wafer 12 arranged symmetrically, the distance between the peripheral electrode point 21 and the edge is 12.1575mm, and the upper and lower are symmetrical, after the whole wafer is cut into half, the distance between the peripheral electrode point 21 and the adjacent internal electrode point 22 in the front and rear direction is the same as the distance between the adjacent internal electrode points 22 in the front and rear direction, and the distance is 11.26mm, and the upper and lower are symmetrical, the distance between the adjacent peripheral electrode points 21 in the left and right directions is the same as the distance between the adjacent internal electrode points 22 in the left and right directions, and the distance is 10.32mm.
[0059] The basic principle and main features of the utility model and the advantages of the utility model are shown and described above. It should be understood by those skilled in the art that the utility model is not limited by the above-mentioned embodiments, and the above-mentioned embodiments and the description in the specification are only to illustrate the principle of the utility model, and various changes and improvements can be made to the utility model without departing from the spirit and scope of the utility model, and these changes and improvements all fall within the scope of the utility model claimed. The scope of protection of the utility model is defined by the appended claims and their equivalents.
Claims
1. A battery suitable for a conductive backplane packaging process, characterized in that, The utility model relates to a solar wafer, which comprises: a whole silicon wafer (1) cut into a first half silicon wafer (11) and a second half silicon wafer (12); a plurality of electrode points (2) arranged in a rectangular array on the first half silicon wafer (11) and the second half silicon wafer (12) and symmetrically arranged above and below; a plurality of main grid lines (3) longitudinally arranged on the first half silicon wafer (11) and the second half silicon wafer (12) and used for bearing the transmission task of current, wherein the main grid lines (3) comprise: a plurality of positive electrode main grid lines (31) arranged outside the plurality of electrode points (2) and arranged in a plurality of columns; a plurality of negative electrode main grid lines (32) arranged in a plurality of columns and arranged in a plurality of columns alternately with the plurality of positive electrode main grid lines (31); and a plurality of auxiliary grid lines (4) arranged between the plurality of main grid lines (3) and used for further refining the current collection area and ensuring that the current on the surface of the solar wafer is uniformly distributed.
2. The battery suitable for the conductive back sheet packaging process according to claim 1, wherein, The plurality of electrode points (2) are composed of peripheral electrode points (21) at the edges in the front-rear direction and internal electrode points (22) at the middle part.
3. The battery suitable for the conductive back sheet packaging process according to claim 2, wherein, The peripheral electrode points (21) are equidistant from the edges in the front-rear direction of the first half silicon wafer (11) and the second half silicon wafer (12), the distance in the front-rear direction between the peripheral electrode points (21) and the adjacent internal electrode points (22) is the same as the distance in the front-rear direction between the adjacent internal electrode points (22), and the distance in the left-right direction between the adjacent peripheral electrode points (21) is the same as the distance in the left-right direction between the adjacent internal electrode points (22).
4. The battery suitable for the conductive back sheet packaging process according to claim 1, wherein, The plurality of columns of negative electrode main grid lines (32) on the first half silicon wafer (11) correspond to the plurality of columns of positive electrode main grid lines (31) and the plurality of columns of positive electrode main grid lines (31) on the second half silicon wafer (12) correspond to the plurality of columns of negative electrode main grid lines (32).
5. The battery suitable for the conductive backplane packaging process according to claim 1, wherein, The negative electrode main grid lines (32) are arranged in a line type structure with thick ends and a thin middle part.
6. The battery suitable for the conductive backplane packaging process according to claim 1, wherein, The auxiliary grid lines (4) comprise: a plurality of positive electrode auxiliary grid lines (41) arranged transversely at equal distances and uniformly, wherein the positive electrode auxiliary grid lines (41) are connected to the positive electrode main grid lines (31); and a plurality of negative electrode auxiliary grid lines (42) arranged transversely at equal distances and uniformly, wherein the negative electrode auxiliary grid lines (42) are connected to the negative electrode main grid lines (32).
7. The battery suitable for the conductive backplane packaging process according to claim 6, wherein, The plurality of positive electrode auxiliary grid lines (41) and the plurality of negative electrode auxiliary grid lines (42) are arranged alternately.