Double-boot automatic switching circuit

Abstract

The utility model relates to the technical field of laminating equipment rollers, in particular to a double-boot automatic switching circuit, which comprises a CPU (central processing unit), a D trigger, a chip boot 1 and a chip boot 2, the chip boot 1 is connected with a gating device 1, the chip boot 2 is connected with a gating device 2, the gating device 1 is connected with an OR gate 1, the gating device 2 is connected with an OR gate 2, the OR gate 1 and the OR gate 2 are respectively connected with the CPU, and the D trigger is connected with the CPU. The gating device 1 and the gating device 2 are respectively connected with the CPU; the OR gate 1 and the OR gate 2 are respectively connected with a D trigger, the D trigger is connected with a watchdog, and the watchdog sends a watchdog reset signal to the D trigger. Compared with the prior art, the dual-boot automatic switching circuit can realize a boot failure automatic switching function, the CPU selects a corresponding boot chip to execute a read-write updating function, and the reliability of a single board is improved.

Description

[Technical Field]

[0001] This utility model relates to the field of bonding equipment roller technology, and in particular to a dual-boot automatic switching circuit. [Background Technology]

[0002] In existing processor boards, the processor reads the boot code from the boot chip when it starts up and performs operations such as initial power-on settings for the CPU. When the boot chip fails or its contents are accidentally rewritten, the CPU cannot initialize properly and the board cannot run. [Utility Model Content]

[0003] To overcome the above problems, this utility model proposes a dual-boot automatic switching circuit that can effectively solve the above problems.

[0004] The present invention provides a technical solution to solve the above-mentioned technical problems by providing a dual-boot automatic switching circuit, including a CPU, a D flip-flop, a boot1 chip, and a boot2 chip. The boot1 chip is connected to a selector 1, and the boot2 chip is connected to a selector 2. The selector 1 is connected to an OR gate 1, and the selector 2 is connected to an OR gate 2. The OR gate 1 and the OR gate 2 are respectively connected to the CPU, and the selector 1 and the OR gate 2 are respectively connected to the CPU. The OR gate 1 and the OR gate 2 are respectively connected to the D flip-flop, and the D flip-flop is connected to a watchdog timer. The watchdog timer sends a watchdog reset signal to the D flip-flop.

[0005] Preferably, OR gate 1 and OR gate 2 can be discrete devices or programmable logic devices.

[0006] Preferably, the CPU's boot_CS pin is connected to OR gate 1 and OR gate 2, respectively.

[0007] Preferably, the CPU's boot_CS pin is connected to selector 1 and selector 2 respectively.

[0008] Preferably, the IO1 pin of the CPU is connected to selector 1 and selector 2 respectively.

[0009] Preferably, the IO2 pin of the CPU is connected to selector 1 and selector 2 respectively.

[0010] Compared with the prior art, the dual-boot automatic switching circuit of this utility model can realize the automatic switching function when boot fails, and the CPU selects the corresponding boot chip to perform read and write update functions, thereby improving the reliability of the single board. [Attached Image Description]

[0011] Figure 1This is a schematic diagram of the dual-boot automatic switching circuit of this utility model.

Detailed Implementation Methods

[0012] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this utility model.

[0013] It should be noted that in this embodiment of the invention, all directional indications (such as up, down, left, right, front, back, etc.) are limited to relative positions on the specified view, rather than absolute positions.

[0014] Furthermore, in this utility model, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this utility model, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0015] Please see Figure 1 The dual-boot automatic switching circuit of this utility model includes a CPU, a D flip-flop, a boot1 chip and a boot2 chip. The boot1 chip is connected to a selector 1, and the boot2 chip is connected to a selector 2. The selector 1 is connected to an OR gate 1, and the selector 2 is connected to an OR gate 2. The OR gate 1 and the OR gate 2 are respectively connected to the CPU, and the selector 1 and the selector 2 are respectively connected to the CPU.

[0016] OR gate 1 and OR gate 2 are respectively connected to D flip-flops, and the D flip-flops are connected to watchdog timers. The watchdog timers send watchdog reset signals to the D flip-flops.

[0017] OR gate 1 and OR gate 2 can be implemented using discrete devices or programmable logic devices.

[0018] The CPU's boot_CS pin is connected to OR gate 1 and OR gate 2, respectively.

[0019] The CPU's boot_CS pin is connected to selector 1 and selector 2, respectively.

[0020] The CPU's IO1 pin is connected to selector 1 and selector 2, respectively.

[0021] The CPU's IO2 pin is connected to selector 1 and selector 2, respectively.

[0022] Circuit principle:

[0023] 1. CPU_IO1 and CPU_IO2 are inputs or high impedance after power-on reset, and require software configuration to become outputs;

[0024] 2. Boot chip selection mainly involves two functions:

[0025] a) The first is automatic selection:

[0026] i. That is, when CPU_IO1 is 0, the selector selects the output signal of the upper OR gate;

[0027] ii. At this time, the watchdog reset output signal is connected to the clock of the D flip-flop. Each reset causes the flip-flop outputs Q and / Q to toggle once.

[0028] iii. Selecting OR gate 1 and OR gate 2 in sequence can output a CS signal.

[0029] b) The second is CPU strobing:

[0030] i. At this time, CPU_IO1 is 1, the selector selects the CS signal below, and selects the boot chip for the CPU;

[0031] ii. At this time, CPU_IO2 is used to select the boot chip; 0 selects boot1 and 1 selects boot2.

[0032] iii. At this point, the selected boot chip can be read and written accordingly.

[0033] Compared with the prior art, the dual-boot automatic switching circuit of this utility model can realize the automatic switching function when boot fails, and the CPU selects the corresponding boot chip to perform read and write update functions, thereby improving the reliability of the single board.

[0034] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any modifications, equivalent substitutions and improvements made within the concept of the present utility model should be included within the patent protection scope of the present utility model.

Claims

1. A dual boot automatic switchover circuit, characterized by It includes CPU, D flip-flop, chip boot1 and chip boot2, the chip boot1 is connected with the gate 1, the chip boot2 is connected with the gate 2, the gate 1 is connected with or gate 1, the gate 2 is connected with or gate 2, the or gate 1 and or gate 2 are connected with CPU respectively, the gate 1 and gate 2 are connected with CPU respectively; The or gate 1 and or gate 2 are connected with D flip-flop respectively, the D flip-flop is connected with watchdog, the watchdog sends watchdog reset signal to D flip-flop.

2. The dual boot automatic switchover circuit of claim 1, wherein, The or gate 1 and or gate 2 can adopt discrete device, also can adopt programmable logic device.

3. The dual boot automatic switchover circuit of claim 1, wherein, The boot_CS pin of the CPU is connected with or gate 1 and or gate 2 respectively.

4. The dual boot automatic switchover circuit of claim 1, wherein, The boot_CS pin of the CPU is connected with the gate 1 and gate 2 respectively.

5. The dual boot automatic switchover circuit of claim 1, wherein, The IO1 pin of the CPU is connected with the gate 1 and gate 2 respectively.

6. The dual boot automatic switchover circuit of claim 1, wherein, The IO2 pin of the CPU is connected with the gate 1 and gate 2 respectively.

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