Semi-super junction side isolation planar gate silicon carbide VDMOS

Abstract

The utility model provides a semi-super-junction side isolation planar gate silicon carbide VDMOS. The semi-super-junction side isolation planar gate silicon carbide VDMOS comprises a drift layer connected to a silicon carbide substrate; a column region and a lug boss are arranged in the drift layer; the P-type well region is connected to the drift layer and the column region; the inner side surface of the P-type well region is connected to the outer side surface of the lug boss; an N-type source region is arranged in the P-type well region; the insulating medium region is connected to the silicon carbide substrate; the inner side surface of the insulating medium region is connected to the outer side surface of the drift layer and the outer side surface of the P-type well region; the P-type source region is connected to the silicon carbide substrate, and the inner side surface of the P-type source region is connected to the outer side surface of the insulating medium region; the gate dielectric layer is connected with the lug boss and the P-type well region; the gate metal layer is connected to the gate dielectric layer; the source metal layer is respectively connected with the P-type source region, the insulating medium region, the P-type well region and the N-type source region; the drain metal layer is connected to the silicon carbide substrate; the voltage endurance capability of the device can be effectively improved under the condition of fixed thickness and area, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] This utility model relates to a semi-superjunction side-isolated planar gate silicon carbide VDMOS. Background Technology

[0002] Silicon carbide (SiC) VDMOS, as a high-performance power semiconductor device, has been widely used in electric vehicles, aerospace, and power conversion due to its high voltage withstand capability, low on-resistance, fast switching speed, and high reliability. However, traditional silicon carbide VDMOS devices still face some technical bottlenecks in design and manufacturing, mainly including the following:

[0003] The contradiction between withstand voltage and on-resistance: In order to improve the withstand voltage of a device, it is usually necessary to increase the thickness of the drift region, but this will lead to a significant increase in on-resistance, thereby reducing device efficiency.

[0004] Insufficient optimization of terminal structure: In high-voltage applications, the terminal structure of the device needs to withstand large electric field stress, and traditional designs are difficult to effectively optimize the terminal structure to improve the withstand voltage capability.

[0005] Lateral diffusion problem: Under high voltage conditions, lateral diffusion of the pn junction of the device may lead to an increase in leakage current, affecting the stability and reliability of the device. Utility Model Content

[0006] The technical problem to be solved by this utility model is to provide a semi-superjunction side-isolated planar gate silicon carbide VDMOS, which constructs a semi-superjunction structure and a side-isolation structure inside the device. Under the condition of fixed thickness and area, it can effectively improve the withstand voltage of the device, reduce the on-resistance of the device, and the insulating dielectric region can effectively improve the reliability and withstand voltage.

[0007] In a first aspect, this utility model provides a semi-superjunction side-isolated planar gate silicon carbide VDMOS, comprising:

[0008] silicon carbide substrate,

[0009] A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer has pillar regions and protrusions;

[0010] The P-type well region has its lower side connected to the upper side of the drift layer and the upper side of the pillar region, and its inner side connected to the outer side of the protrusion; an N-type source region is provided within the P-type well region.

[0011] An insulating dielectric region, the lower side of which is connected to the upper side of the silicon carbide substrate, and the inner side of which is connected to the outer side of the drift layer and the outer side of the P-type well region;

[0012] The lower side of the P-type source region is connected to the upper side of the silicon carbide substrate, and the inner side of the P-type source region is connected to the outer side of the insulating dielectric region.

[0013] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the protrusion and the upper side of the P-type well region;

[0014] A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the gate dielectric layer;

[0015] A source metal layer, wherein the source metal layer is respectively connected to the P-type source region, the insulating dielectric region, the P-type well region and the N-type source region;

[0016] And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

[0017] The advantages of this utility model are:

[0018] I. This utility model achieves a semi-superjunction device structure by constructing pillar regions in the device, thereby improving the device's withstand voltage, reducing the device's on-resistance, and reducing the difficulty of the manufacturing process.

[0019] II. This utility model constructs an insulating dielectric region, namely a side isolation structure. This structure can isolate the diffusion region of the device during the lateral diffusion process of pn when the drain electrode of the device is subjected to high voltage. By improving the withstand voltage of the device through the withstand voltage of the insulating dielectric region, the withstand voltage capability of the device is improved and the terminal structure of the device is optimized.

[0020] Third, this utility model solves the contradiction between increasing the withstand voltage and reducing the on-resistance of the device by designing the semi-superjunction structure and the side isolation structure of the device, thus effectively improving the performance of the device;

[0021] Fourth, this utility model adopts a two-step deposition and etching process, thereby solving the problem of difficult-to-control etching process precision in the preparation of insulating dielectric regions and optimizing the process. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This is a schematic diagram of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention.

[0024] Figure 2 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 1 .

[0025] Figure 3 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 2 .

[0026] Figure 4 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 3 .

[0027] Figure 5 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 4 .

[0028] Figure 6 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 5 .

[0029] Figure 7 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 6 .

[0030] Figure 8 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 7 .

[0031] Figure 9 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 8 .

[0032] Figure 10 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 9 .

[0033] Figure 11 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 10 .

[0034] Figure 12 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 10 one.

[0035] Figure 13 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 10 two.

[0036] Figure 14 This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 10 three.

[0037] Figure 15This is a cross-sectional view of the process of a semi-superjunction side-isolated planar gate silicon carbide VDMOS according to the present invention. Figure 10 Four. Detailed Implementation

[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0043] like Figure 1 As shown, this application embodiment provides a semi-superjunction side-isolated planar gate silicon carbide VDMOS, comprising:

[0044] Silicon carbide substrate 1,

[0045] A drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; the drift layer 2 has pillar regions 21 and protrusions 22.

[0046] P-type well region 3, the lower side of which is connected to the upper side of the drift layer 2 and the upper side of the pillar region 21, the inner side of which is connected to the outer side of the protrusion 22; an N-type source region 31 is provided in the P-type well region 3.

[0047] Insulating dielectric region 4, the lower side of the insulating dielectric region 4 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the insulating dielectric region 4 is connected to the outer side of the drift layer 2 and the outer side of the P-type well region 3.

[0048] P-type source region 5, the lower side of the P-type source region 4 is connected to the upper side of the silicon carbide substrate 1, and the inner side of the P-type source region 5 is connected to the outer side of the insulating dielectric region 4;

[0049] Gate dielectric layer 6, the lower side of which is connected to the upper side of the protrusion 22 and the upper side of the P-type well region 3;

[0050] A gate metal layer 7, the lower side of which is connected to the upper side of the gate dielectric layer 6;

[0051] Source metal layer 8, which is connected to the P-type source region 5, insulating dielectric region 4, P-type well region 3 and N-type source region 31 respectively;

[0052] And a drain metal layer 9, which is connected to the lower side of the silicon carbide substrate 1.

[0053] In this embodiment, preferably, the silicon carbide substrate 1 and the drift layer 2 are both N-type, and the pillar region 21 is P-type.

[0054] In this embodiment, preferably, the thickness of the column region 21 is 40-60% of the thickness of the drift layer 2.

[0055] In this embodiment, preferably, the doping concentration of the pillar region 21 is greater than the doping concentration of the drift layer 2.

[0056] In this embodiment, preferably, the doping concentration of the P-type source region 5 is greater than the doping concentration of the drift layer 2.

[0057] In this embodiment, preferably, the width of the insulating dielectric region 4 is 2-5 μm.

[0058] like Figures 1 to 15 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0059] Step 1: Deposit metal on the lower side of silicon carbide substrate 1 to form drain metal layer 9; Epitaxially grow on silicon carbide substrate 1 to obtain first drift region 23;

[0060] Step 2: Form a barrier layer a above the first drift region 23, etch the barrier layer a to form a via, and perform ion implantation into the first drift region 23 to form the first source region 51;

[0061] Step 3: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, etch the first drift region 23 to the upper side of the silicon carbide substrate 1, and deposit the first insulating dielectric layer 41.

[0062] Step 4: Remove the blocking layer a and epitaxially generate the second drift region 24. The drift layer 2 includes the first drift region 23 and the second drift region 24.

[0063] Step 5: Form a barrier layer a above the second drift region 24, etch the barrier layer a to form a via, and implant ions to form the second source region 52. The P-type source region 5 includes the first source region 51 and the second source region 52. The first source region 51 and the second source region 52 have the same pattern structure, and the same photomask can be used for the two photolithography processes, reducing the device process cost.

[0064] Step 6: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, etch the second drift region 24 to the upper side of the first insulating dielectric layer 41, and deposit the second insulating dielectric layer 42. The insulating dielectric region 4 includes the first insulating dielectric layer 41 and the second insulating dielectric layer 42. The first insulating dielectric layer 41 and the second insulating dielectric layer 42 have the same pattern structure, and the same photomask can be used for the two photolithography processes, reducing the device process cost.

[0065] Step 7: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, and perform ion implantation into the drift layer 2 to form the column region 21;

[0066] Step 8: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, and perform ion implantation into the drift layer 2 to form a P-type trap region 3 and a protrusion 22.

[0067] Step 9: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, and implant ions into the P-type well region 3 to form the N-type source region 31;

[0068] Step 10: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, and deposit the gate dielectric layer 6.

[0069] Step 11: Remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a to form a via, deposit metal, and form the gate metal layer 7.

[0070] Step 12: Remove the original barrier layer a, reform the barrier layer a, etch the barrier layer a to form a via, deposit metal to form the source metal layer 8, remove the barrier layer a, and complete the fabrication.

[0071] In another embodiment of this invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm. -3 The doping concentration of the N-type drift layer 2 is 1-5e17cm. -3 The doping concentration of the P-type source region 5 is 1-5e18cm. -3 The insulating dielectric region 4 can be one or a composite of silicon dioxide and silicon nitride, and the doping concentration of the P-type pillar region 21 is 6-12e17cm. -3 The doping concentration of the P-type well region is 5-8e17cm. -3 The gate dielectric layer 6 can be silicon dioxide, and the doping concentration of the N-type source region 31 is 2-8e18cm. -3 ;

[0072] The doping concentration of the N-type silicon carbide substrate 1 is to ensure a low-resistance ohmic contact with the drain metal layer 9, while simultaneously ensuring the formation of a pn junction with the P-type source region 5 to achieve reverse breakdown voltage and reduce the overall on-resistance of the device. The doping concentration of the N-type drift layer 2 represents a trade-off between the reverse breakdown voltage and on-resistance of the device. The insulating dielectric region 4 is used to laterally cut off the electric field in the device's terminal region to the left and right sides, thereby improving the device's breakdown voltage. The P-type pillar region 21 and the N-type drift layer 2 constitute the device's semi-superjunction structure, achieving a combined longitudinal and lateral breakdown voltage of the pn junction, improving the device's breakdown voltage capability while reducing its on-resistance. The P-type well region 3 forms the basis of the device's gate switch structure, and the doping concentration of the N-type source region 31 is used to reduce the contact resistance of the source metal layer 8, thereby reducing the device's on-resistance.

[0073] The thickness of the N-type silicon carbide substrate 1 is 5 μm to form a pn junction breakdown structure with the P-type source region 5, ensuring the breakdown voltage capability of this region; the thickness of the N-type drift layer 2 is 50-100 μm (including the thickness of the protrusion 22), and can be adjusted within this range according to different requirements for the breakdown voltage characteristics of the device; the thickness of the P-type pillar region 21 is 40-60% of the thickness of the N-type drift layer 2, in order to achieve vertical breakdown voltage at the bottom and horizontal-vertical combined breakdown voltage at the top while reducing the difficulty of the process; the width of the insulating dielectric region 4... The depth is 2-5μm. This is because the etching aspect ratio is difficult to achieve when the etching depth is around 50μm. This increases the margin in device structure design and improves device yield. The width of the P-type source region 5 is 2-10μm. The thickness of the contact area between the top of the P-type well region 3 and the source metal layer 8 is 500nm. The thickness of the N-type source region 31 is 200nm. The width of the N-type source region 31 is 10% of the width of the drain metal layer 9. The thickness of the source metal layer 8 is 200nm. The thickness of the gate metal layer 7 is 150nm.

[0074] In addition to isolating the device terminals, the insulating dielectric region 4 also isolates the P-type source region 5, the N-type drift layer 2, and the P-type well region 3, which can overcome the problem of mutual diffusion and improve the stability and reliability of the device.

[0075] This embodiment achieves a semi-superjunction device structure by constructing a P-type pillar region 21 in the device, thereby improving the device's withstand voltage, reducing its on-resistance, and simplifying the manufacturing process. Insulating dielectric regions, i.e., side isolation structures, are constructed on the left and right sides of the device. This structure can isolate the diffusion region of the device during the lateral diffusion of pn when the device drain is subjected to high voltage. The withstand voltage of the insulating dielectric region 4 is used to improve the device's withstand voltage and optimize the device's termination structure. Through the design of the device's semi-superjunction structure and side isolation structure, the contradiction between improving the device's withstand voltage and reducing its on-resistance is resolved, effectively improving the device's performance.

[0076] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A semi-super junction lateral isolated planar gate silicon carbide VDMOS, characterized in that: Comprise: a silicon carbide substrate, a drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer is provided with a column region and a protruding portion; a P-type well region, the lower side of which is connected to the upper side of the drift layer and the upper side of the column region, the inner side of which is connected to the outer side of the protruding portion; the P-type well region is provided with an N-type source region; an insulating medium region, the lower side of which is connected to the upper side of the silicon carbide substrate, the inner side of which is connected to the outer side of the drift layer and the outer side of the P-type well region; a P-type source region, the lower side of which is connected to the upper side of the silicon carbide substrate, the inner side of which is connected to the outer side of the insulating medium region; a gate medium layer, the lower side of which is connected to the upper side of the protruding portion and the upper side of the P-type well region; a gate metal layer, the lower side of which is connected to the upper side of the gate medium layer; a source metal layer, which is connected to the P-type source region, the insulating medium region, the P-type well region and the N-type source region, respectively; and a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. A semi-super junction lateral isolated planar gated SiC VDMOS as claimed in claim 1, wherein: The silicon carbide substrate and the drift layer are both N-type, and the column region is P-type.

3. The semi-super junction lateral isolated planar gated SiC VDMOS of claim 1, wherein: The thickness of the column region is 40-60% of the thickness of the drift layer.

4. The semi-super junction lateral isolated planar gated SiC VDMOS of claim 1, wherein: The doping concentration of the column region is greater than that of the drift layer.

5. The semi-super junction lateral isolated planar gated SiC VDMOS of claim 1, wherein: The doping concentration of the P-type source region is greater than that of the drift layer.

6. A semi-super junction lateral isolated planar gated SiC VDMOS as claimed in claim 1, wherein: The width of the insulating medium region is 2-5 μm.

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