BMS control charging and discharging circuit using gallium nitride bidirectional switch

Abstract

The utility model discloses a BMS control charging and discharging circuit using a gallium nitride bidirectional switch. The BMS control charging and discharging circuit comprises a charging and discharging management IC and a plurality of MOS transistors. A charging / discharging circuit of the charging / discharging management IC is connected to a plurality of MOS transistors. And each MOS transistor adopts a bidirectional silicon-based gallium nitride enhancement mode high electron mobility transistor. According to the utility model, a plurality of bidirectional silicon-based gallium nitride enhanced mode high electron mobility transistors are arranged in the charging circuit to break through the traditional mode that unidirectional switch tubes are used side by side, so that the size of a circuit board is smaller and the cost is lower. The bidirectional silicon-based gallium nitride enhanced mode high-electron mobility transistor is high in voltage resistance, and can bear higher short-circuit impact pulse than a conventional MOS (Metal Oxide Semiconductor) transistor. According to the utility model, only one gallium nitride device is adopted to manage charging and discharging at the same time, and the traditional design scheme that two MOS (Metal Oxide Semiconductor) are connected in parallel to perform charging and discharging management is replaced, so that the cost is saved.

Description

Technical Field

[0001] This utility model relates to charging and discharging circuits, specifically to a BMS-controlled charging and discharging circuit using a gallium nitride bidirectional switch. Background Technology

[0002] In energy storage battery management systems, MOSFETs are needed to control and protect the battery's charging and discharging process. MOSFETs can be placed at either the positive or negative terminal of the battery for control. However, when controlled at the positive terminal, oscillations may occur during the moment the MOSFET is turned off, and the resulting large instantaneous current can cause the MOSFET to break down. This problem is avoided when the negative terminal is selected for control. However, controlling the MOSFET at the negative terminal requires a dedicated drive circuit because the MOSFET requires a large current. If the turn-on or turn-off time is too long, the MOSFET's power loss will be too high, reducing its lifespan and causing it to overheat. Existing methods for fast-turn-off MOSFETs include using a driver chip or a transistor driver circuit. The former is expensive and complex; the latter cannot meet the high-current switching requirements of the MOSFET. Furthermore, existing charging and discharging technologies use separate MOSFETs to manage charging and discharging.

[0003] Therefore, it is necessary to improve the traditional charging and discharging circuit. Utility Model Content

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a BMS control charging and discharging circuit using gallium nitride bidirectional switches. The purpose of designing this charging and discharging circuit is to break away from the traditional parallel use of unidirectional switching transistors, thereby making the circuit board smaller and less expensive.

[0005] To solve the above technical problems, the present invention is implemented through the following solution: The present invention provides a BMS control charging and discharging circuit using a gallium nitride bidirectional switch, including a charging and discharging management IC and multiple MOS transistors;

[0006] The charging control pin CHG of the charging and discharging management IC is connected to the first end of resistor R35 and the first end of the first RC filter circuit, respectively. The second end of the first RC filter circuit is grounded to SNR, and the second end of resistor R35 is connected to the charging input line.

[0007] The grounding pin BATN of the charge / discharge management IC is grounded to SNR.

[0008] The secondary control pin SUB of the charge / discharge management IC is connected to the positive terminals of Zener diodes TVS2 and TVS4 respectively. The negative terminal of Zener diode TVS2 is connected to the P- pin of the power supply, and the negative terminal of Zener diode TVS4 is grounded to SNR.

[0009] The VCC pin of the charge / discharge management IC is connected to the first end of resistor R40 and the first end of capacitor C50, respectively. The second end of resistor R40 is connected to the negative terminal of Zener diode TVS5. The positive terminal of Zener diode TVS5 is connected to pin B4 of the power supply. The second end of capacitor C50 is grounded to SNR.

[0010] The capacitor C50 is connected in parallel with a capacitor C51 and a Zener diode ZD3, wherein the positive terminal of the Zener diode ZD3 is grounded to SNR;

[0011] The discharge control pin DSG of the charge / discharge management IC is connected to the first end of resistor R36 and the first end of the second RC filter circuit, respectively. The second end of the second RC filter circuit is grounded to SNR. The second end of resistor R36 is connected to the discharge output line.

[0012] The gate control pin (GATE) of the charge / discharge management IC is connected to the first end of resistor R37, and the second end of resistor R37 controls the gate (G) of each MOS transistor.

[0013] The MOS transistors are configured in four groups. The D1 terminals of each MOS transistor are interconnected and then grounded to SNR and connected to a resistor RN3. The other end of the resistor RN3 is connected to the power supply SNP and ground GND. The D2 terminals of each MOS transistor are interconnected and then connected to the PAKN pin of the charge / discharge management IC.

[0014] The MOS transistor is a bidirectional silicon-based gallium nitride enhancement-mode high electron mobility transistor.

[0015] Furthermore, the first RC filter circuit includes a capacitor C48 and a resistor R38 connected in parallel.

[0016] Furthermore, the second RC filter circuit includes a capacitor C49 and a resistor R39 connected in parallel.

[0017] Furthermore, the second end of the resistor R37 is also connected to the positive terminal of the Zener diode TVS6 and the positive terminal of the Zener diode TVS7, respectively;

[0018] The negative terminal of the Zener diode TVS6 is connected to the first end of the resistor R68, and the second end of the resistor R68 is grounded to SNR.

[0019] The negative terminal of the Zener diode TVS7 is connected to the first end of resistor R69, and the second end of resistor R69 is connected to the PAKN pin of the charge / discharge management IC.

[0020] Furthermore, the bidirectional silicon-based gallium nitride enhancement-mode high electron mobility transistor used is model INV100FQ030A.

[0021] Furthermore, a resistor is connected between the second end of the resistor R37 and the gate G of each MOS transistor.

[0022] Compared with the prior art, the beneficial effects of this utility model are:

[0023] 1. The charging circuit of this utility model is equipped with multiple bidirectional gallium nitride enhancement mode high electron mobility transistors to break the traditional mode of using unidirectional switching transistors side by side, thereby making the circuit board smaller and the cost lower.

[0024] 2. The bidirectional silicon-based gallium nitride enhancement mode high electron mobility transistor of this invention has high withstand voltage and can withstand higher short-circuit impact pulses than conventional MOS transistors.

[0025] 3. This utility model uses only one gallium nitride device to manage charging and discharging, replacing the traditional design that requires two MOS devices in parallel for charging and discharging management, thus saving costs. Attached Figure Description

[0026] Figure 1 This invention relates to a charge and discharge management circuit.

[0027] Figure 2 This invention relates to a circuit consisting of multiple MOS transistors connected to a charge / discharge management circuit. Detailed Implementation

[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments, so that the advantages and features of the present utility model can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present utility model. Obviously, the embodiments described in this utility model are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0029] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0030] Example 1: The specific structure of this utility model is as follows:

[0031] Please refer to the appendix. Figure 1-2This utility model discloses a BMS control charging and discharging circuit using a gallium nitride bidirectional switch, comprising a charging and discharging management IC and multiple MOS transistors. The pin functions of the charging and discharging management IC are as follows: CHG is the charging control pin, BATH is the battery connection pin, SUB is the secondary control pin, GATE is the gate connection pin, VCC is the power supply pin, DSG is the discharging control pin, NC is the spare pin, and PAKN is the package pin.

[0032] The charging control pin CHG of the charge / discharge management IC is connected to the first end of resistor R35 and the first end of the first RC filter circuit, respectively. The second end of the first RC filter circuit is grounded to SNR. The second end of resistor R35 is connected to the charging input line. The first RC filter circuit includes a capacitor C48 and a resistor R38 connected in parallel.

[0033] The grounding pin BATN of the charge / discharge management IC is grounded to SNR.

[0034] The secondary control pin SUB of the charge / discharge management IC is connected to the positive terminals of Zener diodes TVS2 and TVS4 respectively. The negative terminal of Zener diode TVS2 is connected to the P- pin of the power supply, and the negative terminal of Zener diode TVS4 is grounded to SNR.

[0035] The VCC pin of the charge / discharge management IC is connected to the first end of resistor R40 and the first end of capacitor C50, respectively. The second end of resistor R40 is connected to the negative terminal of Zener diode TVS5. The positive terminal of Zener diode TVS5 is connected to pin B4 of the power supply. The second end of capacitor C50 is grounded to SNR.

[0036] The capacitor C50 is connected in parallel with a capacitor C51 and a Zener diode ZD3, wherein the positive terminal of the Zener diode ZD3 is grounded to SNR;

[0037] The discharge control pin DSG of the charge / discharge management IC is connected to the first end of resistor R36 and the first end of the second RC filter circuit, respectively. The second end of the second RC filter circuit is grounded to SNR. The second end of resistor R36 is connected to the discharge output line. The second RC filter circuit includes a capacitor C49 and a resistor R39 connected in parallel.

[0038] The gate control pin (GATE) of the charge / discharge management IC is connected to the first terminal of resistor R37. The second terminal of resistor R37 controls the gate (G) of each MOS transistor. The second terminal of resistor R37 is also connected to the anodes of Zener diodes TVS6 and TVS7, respectively. The cathode of Zener diode TVS6 is connected to the first terminal of resistor R68, and the second terminal of resistor R68 is grounded (SNR). The cathode of Zener diode TVS7 is connected to the first terminal of resistor R69, and the second terminal of resistor R69 is connected to the PAKN pin of the charge / discharge management IC. A resistor is connected between the second terminal of resistor R37 and the gate (G) of each MOS transistor.

[0039] The MOS transistors are configured in four groups. The D1 terminals of each MOS transistor are interconnected and then grounded to SNR and connected to a resistor RN3. The other end of the resistor RN3 is connected to the power supply SNP and ground GND. The D2 terminals of each MOS transistor are interconnected and then connected to the PAKN pin of the charge / discharge management IC.

[0040] The MOS transistor is a bidirectional gallium nitride enhancement-mode high electron mobility transistor (HEMT) based on silicon. The model number of this bidirectional gallium nitride enhancement-mode HEMT is INV100FQ030A. Example 2:

[0041] The following is the principle of the charging and discharging circuit of this utility model:

[0042] like Figure 1-2 As shown, this utility model's INV100FQ030A model MOS transistor has four transistors: MOS transistor Q25, MOS transistor Q27, MOS transistor Q29, and MOS transistor Q31. The current flows bidirectionally between the D1 and D2 terminals of the four INV100FQ030A model MOS transistors. The charge / discharge management IC will be referred to as U5 below.

[0043] When the CHG charging drive signal and the DSG discharging drive signal are output at a high level, they pass through resistors R35 and R36 to pin 1 and pin 8 of U5, respectively. At this time, pin 6 of U5 outputs a high level of 5V-5.6V, which supplies power to the gate of each MOS transistor through resistor R37. The D1 and D2 terminals of each MOS transistor are turned on simultaneously, entering the normal charging and discharging state.

[0044] When the CHG charging drive signal is low and the DSG discharging drive signal outputs a high level, each MOS transistor acts as a diode, with D2 being positive and D1 being negative, and current can only flow from D2 to D1.

[0045] When the CHG charging drive signal is high and the DSG discharging drive signal is low, each MOS transistor acts as a diode, with D1 being positive and D2 being negative, and current can only flow from D1 to D2.

[0046] When the CHG charging drive signal is low and the DSG discharging drive signal outputs a low level, each MOS transistor acts as a bidirectional diode, with both D1 and D2 terminals cut off, and none of the MOS transistors operate.

[0047] In summary, the charging circuit of this invention incorporates multiple bidirectional gallium nitride enhancement-mode high electron mobility transistors (HEMTs) to break away from the traditional parallel use of unidirectional switching transistors, thereby enabling a smaller circuit board and lower cost. The bidirectional gallium nitride HEMTs of this invention have high voltage withstand capabilities, able to withstand higher short-circuit surge pulses than conventional MOS transistors. This invention uses only one gallium nitride device to manage charging and discharging simultaneously, replacing the traditional design that requires two MOS transistors in parallel for charging and discharging management, thus saving costs.

[0048] The above description is only a preferred embodiment of the present utility model and does not limit the patent scope of the present utility model. Any equivalent structural or procedural transformations made based on the contents of the present utility model specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present utility model.

Claims

1. A BMS control charge-discharge circuit using a gallium nitride bidirectional switch, characterized by, The charging and discharging management IC and a plurality of MOS transistors are included. The charging control pin CHG of the charging and discharging management IC is connected to the first end of the resistor R35 and the first end of the first RC filter circuit, and the second end of the first RC filter circuit is grounded SNR, and the second end of the resistor R35 is connected to the charging input circuit. The ground pin BATN of the charging and discharging management IC is grounded SNR. The secondary control pin SUB of the charging and discharging management IC is connected to the anode of the voltage stabilizing diode TVS2 and the anode of the voltage stabilizing diode TVS4, the cathode of the voltage stabilizing diode TVS2 is connected to the P-pin of the power supply, and the cathode of the voltage stabilizing diode TVS4 is grounded SNR. The VCC pin of the charging and discharging management IC is connected to the first end of the resistor R40 and the first end of the capacitor C50, the second end of the resistor R40 is connected to the cathode of the voltage stabilizing diode TVS5, and the second end of the capacitor C50 is grounded SNR. The capacitor C50 is connected in parallel with the capacitor C51 and the voltage stabilizing diode ZD3, and the anode of the voltage stabilizing diode ZD3 is grounded SNR. The discharging control pin DSG of the charging and discharging management IC is connected to the first end of the resistor R36 and the first end of the second RC filter circuit, and the second end of the second RC filter circuit is grounded SNR, and the second end of the resistor R36 is connected to the discharging output circuit. The gate control pin GATE of the charging and discharging management IC is connected to the first end of the resistor R37, and the second end of the resistor R37 controls the gate G of each MOS transistor. The MOS transistor is provided with four groups, the D1 end of each MOS transistor is connected to the ground SNR after being connected to each other and connected to a resistor RN3, the other end of the resistor RN3 is connected to the SNP of the power supply and the ground GND, and the D2 end of each MOS transistor is connected to the PAKN pin of the charging and discharging management IC after being connected to each other. The MOS transistor is a bidirectional silicon-based gallium nitride enhancement mode high electron mobility transistor.

2. The BMS control charge-discharge circuit using a gallium nitride bidirectional switch according to claim 1, wherein The first RC filter circuit includes the capacitor C48 and the resistor R38 connected in parallel.

3. The BMS control charge-discharge circuit using a gallium nitride bidirectional switch according to claim 1, wherein The second RC filter circuit includes the capacitor C49 and the resistor R39 connected in parallel.

4. The BMS control charge-discharge circuit using a gallium nitride bidirectional switch according to claim 1, wherein, The second end of the resistor R37 is also connected to the anode of the voltage stabilizing diode TVS6 and the anode of the voltage stabilizing diode TVS7. The cathode of the voltage stabilizing diode TVS6 is connected to the first end of the resistor R68, and the second end of the resistor R68 is grounded SNR. The cathode of the voltage stabilizing diode TVS7 is connected to the first end of the resistor R69, and the second end of the resistor R69 is connected to the PAKN pin of the charging and discharging management IC.

5. The BMS control charge-discharge circuit using a gallium nitride bidirectional switch according to claim 1, wherein, The model of the bidirectional silicon-based gallium nitride enhancement mode high electron mobility transistor is INV100FQ030A.

6. The BMS control charge-discharge circuit using a gallium nitride bidirectional switch according to claim 1, wherein, The resistor is connected between the second end of the resistor R37 and the gate G of each MOS transistor.

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