DEMOS device and integrated circuit
By introducing a P-type radiation hardening buffer and an isolation region to isolate the source and drain regions in DEMOS devices, the leakage path problem of DEMOS devices under total dose irradiation is solved, the radiation resistance is improved and the performance impact is reduced, achieving a cost-effectiveness balance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2026-03-20
AI Technical Summary
When improving the radiation resistance of DEMOS devices, conventional methods change the main structure and size of the device, affecting its performance and incurring high costs. It is difficult to effectively solve the total dose radiation problem without changing the process.
In DEMOS devices, a P-type radiation hardening buffer is introduced around the source region. By setting up the radiation hardening buffer and the isolation region to isolate the source and drain regions, a single-sided abrupt junction is formed, reducing the formation of leakage channels and keeping the main structure and process of the device basically unchanged.
Without altering the main structure and process of the device, the radiation resistance of the DEMOS device is significantly improved, the impact of total dose irradiation on the device is reduced, the negative impact on performance is minimized, and the cost is lower.
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Figure CN224022142U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of semiconductor, concretely relates to a DEMOS device and integrated circuit. BACKGROUND
[0002] Electronic systems used in special application occasions such as aerospace, aviation and space station have higher requirements on the anti-radiation capability of components (including integrated circuits). The radiation effects of electronic components are most typical in total dose radiation effects and single particle effects. Among them, the total dose radiation effect is mainly the charge accumulation effect caused by the damage of cosmic rays to the SiO2 chemical bond in the isolation region of the device.
[0003] The conventional total dose anti-radiation reinforcement method is divided into three categories of system level, device level and process level anti-radiation reinforcement. The system level anti-radiation reinforcement is mainly based on redundant design, which can greatly improve the anti-radiation performance, but occupies a large chip space and has high cost. The device level anti-radiation reinforcement is mainly through special design of the device structure to enhance the anti-total dose radiation capability. In the conventional device level anti-radiation reinforcement method, the typical designs include ring gate, large head gate, inverse proportional gate and P+ protection ring reinforcement design. Although this method can effectively improve the anti-radiation capability of components, it strictly limits the channel size of the device, has a great influence on the performance of the device, and also makes the shape of the gate more complex, which brings great restriction to design, process and parameter modeling. The process level anti-radiation reinforcement, such as silicon surface layer high concentration implantation at the bottom of the isolation region, improves the difficulty of being inverted and thus improves the anti-radiation capability. Although this method can improve the anti-radiation capability to a certain extent, it cannot fundamentally solve the problem of total dose radiation effect.
[0004] Therefore, how to solve the total dose radiation problem and reduce the influence on the performance of the device without changing the main structure and size of the device and the process as much as possible is an urgent problem in the anti-radiation field. UTILITY MODEL CONTENTS
[0005] In order to overcome the above defects, the utility model is provided to solve the total dose radiation problem and reduce the influence on the performance of the device without changing the main structure and size of the device and the process as much as possible.
[0006] In the first aspect, the utility model provides a DEMOS device, which comprises:
[0007] a substrate;
[0008] a well region extending from the surface of the substrate into the substrate;
[0009] a drift region located on one side of the well region;
[0010] a gate structure, the gate structure comprising a gate dielectric layer and a gate electrode which are arranged in a stack, and the gate structure covering part of the well region and part of the drift region;
[0011] a source-drain implant region located inside the well region, the source-drain implant region comprising a source region and a drain region, a channel region being formed between the source region and the drain region, the source region and the drain region being located on two sides of the gate structure respectively, and the drain region being located in the drift region;
[0012] a radiation-hardened buffer region located inside the well region and surrounding the source region; wherein the substrate, the well region and the radiation-hardened buffer region are of a first doping type, and the doping type of the source-drain implant region and the doping type of the drift region are of a second doping type different from the first doping type;
[0013] an isolation region located on the surface of the substrate, and a footprint of the isolation region on the substrate surface surrounding a footprint of the radiation-hardened buffer region on the substrate surface and a footprint of the drain region on the substrate surface.
[0014] Further, in the DEMOS device described above, the doping concentration of the radiation-hardened buffer region is the same as the doping concentration of the well region.
[0015] Further, in the DEMOS device described above, the doping concentration of the radiation-hardened buffer region and the doping concentration of the well region are both light doping concentrations.
[0016] The doping concentration of the source region and the doping concentration of the drain region are both heavy doping concentrations.
[0017] Further, in the DEMOS device described above, the radiation-hardened buffer region and the well region are formed by the same process.
[0018] Further, in the DEMOS device described above, the width of the radiation-hardened buffer region is between 0.1um and 1um.
[0019] Further, in the DEMOS device described above, the source-drain implant region comprises a first sub-implant region surrounding the source region and a second sub-implant region surrounding the drain region; wherein the first sub-implant region and the second sub-implant region are connected.
[0020] The first sub-implant region comprises a first edge along the gate width direction, a second edge along the gate width direction and a third edge along the gate length direction, wherein the footprints of the first edge and the second edge on the substrate surface extend into the footprint of the gate electrode on the substrate surface.
[0021] Further, in the DEMOS device described above, the distance d1, at which the orthographic projection of the first side and the second side on the substrate surface extends into the orthographic projection of the gate on the substrate surface, satisfies the following condition:
[0022] 10 < d1 < 100 nm.
[0023] Further, in the DEMOS device described above, the isolation region is a dielectric isolation.
[0024] Further, the DEMOS device described above further comprises:
[0025] a lightly doped drain region between the drain region and the channel region.
[0026] In a second aspect, the utility model provides a kind of integrated circuit, comprising at least one DEMOS device as described in any one of the above.
[0027] The DEMOS device and integrated circuit provided by the utility model isolate the source-drain region from the isolation region by setting the anti-radiation reinforcement buffer region around the source region, which changes the main structure of the original DEMOS device relatively less and has relatively simple process, and under the premise of ensuring the channel length between the source region and the drain region, even if the total dose irradiation effect causes the well region and the silicon surface layer under the entire isolation region to be inverted, the anti-radiation reinforcement buffer region prevents the formation of a leakage channel between the source region and the drain region, which theoretically completely solves the influence of total dose irradiation on the device and improves the anti-radiation capability. BRIEF DESCRIPTION OF DRAWINGS
[0028] The disclosure of the utility model will become more easily understood with reference to the accompanying drawings. Those skilled in the art will readily understand that these drawings are merely intended to illustrate, and are not intended to limit the scope of protection of the utility model. In addition, similar numbers in the drawings are used to represent similar structures or regions, wherein:
[0029] Figure 1 is a structural schematic diagram of an existing N-type DEMOS device;
[0030] Figure 2 is a cross-sectional view of the device structure in Figure 1
[0031] Figure 3 is a structural schematic diagram of an NMOS structure in an existing CMOS device;
[0032] Figure 4 is a structural schematic diagram of an N-type DEMOS device according to an embodiment of the utility model;
[0033] Figure 5 is a cross-sectional view of the device structure in Figure 4 A cross-sectional view of a device structure in the middle. DETAILED DESCRIPTION
[0034] In order to make the above objectives, characteristics and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of different ways beyond the specific details set forth herein without departing from the scope of the present application. It is therefore contemplated that the present application covers any and all modifications, variations, combinations or equivalents that fall within the scope of the present application. Thus, the present application should not be limited by the specific embodiments disclosed in the following description.
[0035] In the description of the present application, the terms "first", "second", and the like are used only for the purpose of description and are not to be construed as indicating or implying relative importance or an indicated number thereof. In addition, in the present application, unless otherwise explicitly specified and limited, the terms "connected", "connected" and the like should be broadly understood, for example, it can be directly connected, or indirectly connected through an intermediate medium, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0036] Total ionizing dose effect (TID) refers to the cumulative dose absorbed by the sample during irradiation, which is the ionizing radiation effect of the cumulative dose, and the process of device failure caused by irradiation accumulation. The most sensitive area of total dose irradiation effect is the area covered by the isolation region on the substrate surface. For conventional drain extended metal oxide semiconductor (DEMOS) process, due to the need for physical isolation, STI (Shallow Trench Isolation) or LOCOS (Local Oxidation of Silicon) isolation technology is often used. The area where STI or LOCOS is located is the isolation region in direct contact with the Si substrate, and thus is most sensitive to total dose irradiation.
[0037] Figure 1 To Figure 2 Take an N-type DEMOS device with a LOCOS isolation process as an example to illustrate its total dose irradiation effect. As shown in FIG. 1, the N-type DEMOS device is formed on a Si substrate 1. The N-type DEMOS device includes a P-type well 2, a N-type well 3, a P-type source region 4, a N-type drain region 5, a P-type body region 6, a N-type body region 7, a P-type body contact region 8, a N-type body contact region 9, a P-type source contact region 10, a N-type drain contact region 11, a P-type gate region 12, a N-type gate region 13, a P-type gate contact region 14, a N-type gate contact region 15, a P-type source electrode 16, a N-type drain electrode 17, a P-type body electrode 18, a N-type body electrode 19, a P-type source electrode 20, a N-type drain electrode 21, a P-type gate electrode 22, and a N-type gate electrode 23. Figure 1As shown, a conventional N-type DEMOS device includes an active region 1 and an isolation region 2, wherein the isolation region 2 uses dielectric isolation. The active region 1 forms the main structure of the device, including an N+ source region 11, an N+ drain region 12, and a channel region defined by the gate structure 7. The N+ source region 11 and the N+ drain region 12 are located on both sides of the channel region. The area outside the active region 1 is the isolation region 2, where the silicon surface is covered with a thick oxide layer to form a physical isolation region between devices. As those skilled in the art will know, this N-type DEMOS device may also include a P-type substrate 3, a P-well region 4, N+ source / drain injection regions 5', and an N-drift region 10. The P-well region 4 extends from the surface of the P-type substrate 3 into the P-type substrate 3. The N-drift region 10 is located on one side of the P-well region 4, and the N+ drain region 12 is located in the P-well region 4. The N+ source / drain implantation region 5' is located within the P-well region 4 and is used only for the implantation of the N+ source region 11 and the N+ drain region 12. Due to the obstruction of the thick oxide layer in the isolation region 2, the N+ source / drain implantation cannot actually be implanted into the substrate 3 below it. Among them, P-type can be used as the first doping type, and N-type can be used as the second doping type.
[0038] like Figure 2 As shown, after total dose irradiation, a large number of electron-hole pairs are generated in the thick oxide layer. Due to their lighter mass, electrons escape the silicon oxide layer through the surface barrier of the SiO2 / Poly gate under the influence of the electric field. Holes, due to their heavier mass and higher interface barrier, cannot cross the SiO2 / Si interface and gradually accumulate at the interface under the influence of the electric field, forming a cluster of positive charges. The thicker the oxide layer, the more significant this charge accumulation effect, meaning the more severe the damage to the oxide layer caused by the irradiation. When the charge accumulates to a certain extent, the resulting positive electric field will cause inversion of the surface layer of the P-well region 4 near the interface, creating a potential leakage path between the source and drain. Figure 2 (As indicated by the arrow), which in turn leads to leakage in the device.
[0039] Therefore, for N-type DEMOS devices, total dose irradiation mainly causes the accumulation of positive charges to lead to the inversion of the well region at the bottom of the field region, which in turn forms a potential leakage channel and ultimately weakens the isolation effect of the field region.
[0040] Generally, considering both cost and radiation resistance, device structure optimization is a relatively ideal radiation hardening solution. However, in practical applications, when optimizing the structure of complex high-voltage devices such as DEMOS devices in BCD process platforms, it has been found that using the same optimization methods as for CMOS devices results in limited improvement in radiation resistance.
[0041] Specifically, Figure 3The NMOS structure in the CMOS device can include an active region 1' and an isolation region 2', wherein the isolation region 2' is isolated by a dielectric. The active region 1' forms the main structure of the device, including an N+ source region 11', an N+ drain region 12', a channel region defined by a gate structure 7', and the N+ source region 11' and the N+ drain region 12' are located on both sides of the channel region. The region outside the active region 1' is the isolation region 2', and a thick oxide layer is formed on the silicon surface of the region to form a physical isolation region between devices. Those skilled in the art can know that the NMOS device can also include a P-type substrate 3', a P-well region 4', and an N+ source / drain implant region 5''. The P-well region 4' extends from the surface of the P-type substrate 3' into the P-type substrate 3'. The N+ drain region 12' is located in the P-well region 4'. The N+ source / drain implant region 5'' is located in the P-well region 4' and is only used for implantation of the N+ source region 11' and the N+ drain region 12'. Due to the blocking of the thick oxide layer, the N+ source / drain implant cannot actually be implanted into the substrate 3' under the isolation region 2'. The P-type can be used as the first doping type, and the N-type can be used as the second doping type.
[0042] Continuing to refer to Figure 3 , in order to improve the radiation resistance of the CMOS device, a P+ isolation ring 8' is formed in the active region 1', and the source / drain region is separated from the isolation region by the P+ isolation ring 8', which is similar to adding an "isolation band" between the source / drain region and the isolation region to prevent the formation of a leakage channel between the source / drain region through the thick oxide layer due to radiation. Although this scheme can effectively improve the radiation resistance of the device, it also has obvious disadvantages: (1) The isolation region includes a peripheral buffer N+ active region 9' and a P+ isolation ring 8', which occupies a large area of the device. (2) The P+ isolation ring 8' is in direct contact with the N+ source / drain to form a double-edge abrupt PN junction, which has a great impact on the voltage resistance of the device, especially for the drain region which needs to withstand high voltage.
[0043] It should be noted that Figure 3 , due to the presence of the P+ isolation ring 8', the N+ source / drain implant region 5' is actually the region excluding the P+ isolation ring 8'.
[0044] Referring to Figure 1 and Figure 3 , compared with the CMOS device of Figure 3 , the structure of the DEMOS device is more complex, and the specific differences are as follows:
[0045] First, the source / drain of the DEMOS device is no longer symmetrically distributed about the gate, and is not on the same active region 1';
[0046] Second, the isolation region 2 of the DEMOS device occupies a larger area (the isolation region 2 is a weak anti-radiation region), and the source / drain active region 1 is also divided by the isolation region, resulting in a larger field oxide contact area between the source / drain active region and the isolation region, and a higher requirement for anti-radiation reinforcement;
[0047] Third, in order to improve the breakdown voltage of the device, the N+ drain region 12 has a large area of N- drift region 10 covering the drain region, and the N- drift region 10 makes a part of the silicon under the isolation region 2 also N-type, further reducing the source / drain region spacing and increasing the risk of leakage;
[0048] Fourth, the drain region of the DEMOS device needs to withstand a higher voltage (6-100V). Thus, the traditional anti-radiation reinforcement method, such as the P+ protection ring, has a more obvious effect on the intrinsic performance of such devices, and also brings greater challenges to improving the anti-radiation capability of DEMOS through traditional device structure optimization.
[0049] Therefore, in order to solve the above technical problems, the utility model adopts the following technical scheme.
[0050] Figure 4 is a structure schematic view of an N-type DEMOS device according to an embodiment of the utility model, Figure 5 is Figure 4 a cross-sectional view of the device structure in Figure 4 to Figure 5 As shown in Figure 1 , the DEMOS device is based on the DEMOS device shown in Figure 4 , the mask plate layout of the N+ source / drain implantation region 5 is optimized to obtain the shape of the mask plate layout of the N+ source / drain implantation region 5 in , so that after implanting the N+ source region 11 and the N+ drain region 12, the N+ source region 11 is no longer in direct contact with the isolation region 2, but a P-type ring 6, that is, an anti-radiation reinforcement buffer region 6, is formed between them. Wherein, the P-type anti-radiation reinforcement buffer region 6 surrounds the N+ source region 11, and the orthographic projection of the isolation region 2 on the surface of the P-type substrate 3 surrounds the orthographic projection of the anti-radiation reinforcement buffer region 6 on the surface of the P-type substrate 3, and surrounds the orthographic projection of the N+ drain region 12 on the surface of the P-type substrate 3. In this way, when the charge accumulates to a certain extent, the positive electric field formed will invert the surface layer of the P-well region 4 near the interface, but due to the existence of the P-type anti-radiation reinforcement buffer region 6, a leakage channel cannot be formed between the N+ source region 11 and the N+ drain region 12.
[0051] Continuing to refer to Figure 1 and Figure 5 , the DEMOS device of the embodiment is relative to Figure 1The gate, the source region and the drain region of the DEMOS device shown are basically unchanged, so the design of the DEMOS device does not bring great constraints, the N+ drain region 12 of the DEMOS is less affected, the overall performance of the DEMOS is relatively less affected, and the P-type anti-radiation reinforcement buffer region 6 is only in the N+ source region 11.
[0052] The DEMOS device of the embodiment isolates the source and drain regions from the isolation region 2 by setting the anti-radiation reinforcement buffer region 6 around the source region, changes the main structure of the original DEMOS device relatively less, and the process is relatively simple. On the premise of ensuring the channel length between the source region and the drain region, even if the total dose irradiation effect causes the silicon surface layer under the well region 4 and the entire isolation region 2 to be inverted, due to the existence of the anti-radiation reinforcement buffer region 6, a leakage channel cannot be formed between the source region and the drain region, greatly reducing the influence of total dose irradiation on the device.
[0053] In a specific implementation process, the P-type anti-radiation reinforcement buffer region 6 is a P-doped type, which can make the doping concentration of the anti-radiation reinforcement buffer region 6 the same as the doping concentration of the well region 4, so that the P-anti-radiation reinforcement buffer region 6 and the P-well region 4 can be formed by using the same process. Figure 1 Compared with the process of , no additional process is needed. That is, after the P-well region 4 is formed, the N+ source and drain implantation region 5 according to the scheme is used to perform implantation, and the P-well region 4 between the N+ source region 11 and the N+ drain region 12 and the isolation region 2 is used as the P-type anti-radiation reinforcement buffer region 6.
[0054] In a specific implementation process, since the doping concentration of the anti-radiation reinforcement buffer region 6 is a light doping concentration, and the doping concentration of the source region and the doping concentration of the drain region are both heavy doping concentrations, the depletion region between the P-anti-radiation reinforcement buffer region 6 and the N+ source region 11 can be ensured to be wide, and the P-anti-radiation reinforcement buffer region 6 is only in the N+ source region 11, so that the withstand voltage capability of the N+ drain region 12 is not affected by the setting of the anti-radiation reinforcement buffer region 6.
[0055] In a specific implementation process, the wider the P-anti-radiation buffer region is, the better, but considering the actual chip area limitation requirement, the P-anti-radiation buffer region width can be set to between 0.1um and 1um according to different technology nodes.
[0056] Continuing to refer to Figure 3 and Figure 4 , Figure 3 the parasitic PN junction of the source region is a double-sided abrupt junction, and Figure 4The parasitic PN junction of the source region of the DEMOS device is a single-sided abrupt junction, the concentration gradient of the P-type region is more gentle, and the voltage resistance capability is stronger, which not only enhances the radiation resistance capability, but also reduces the adverse effects on the device performance, and does not need to increase the process additionally, and the cost is low.
[0057] In a specific implementation process, the DEMOS device further includes a lightly doped drain (LDD) region (not shown in the figure), and the conventional LDD region covers all active regions of the device, that is, so-called universal injection, so that there is a risk that the P-buffer region in the utility model and even the inversion type may be injected in the lightly doped drain region, therefore, the injection of the lightly doped drain region in the utility model is changed from the universal injection in the active region in the prior art to injection according to the mask layout of the optimized N+ source and drain injection region 5.
[0058] Continuing to refer to Figure 4 , the N+ source and drain injection region 5 includes a first sub-injection region 51 surrounding the N+ source region 11 and a second sub-injection region 52 surrounding the N+ drain region 12; wherein the first sub-injection region 51 is connected with the second sub-injection region 52, so that the N+ source and drain injection region 5 forms a closed region.
[0059] As shown in Figure 5 , the first sub-injection region 51 includes a first edge 511 along the gate width direction, a second edge 512 along the gate width direction and a third edge 513 along the gate length direction, the orthogonal projection of the first edge 511 and the second edge 512 on the substrate 3 surface extends into the orthogonal projection of the gate on the substrate 3 surface, and the deep distance d1 satisfies the following condition: 10 < d1 < 100 nm. Such a setting is to ensure that even if there is a fluctuation in the N+ source and drain injection photolithography alignment in mass production, at least one of the N+ source region 11 and / or the N+ drain region 12 will not be in direct contact with the isolation region 2, so as to ensure that there is no leakage channel between the N+ source region 11 and the N+ drain region 12.
[0060] In the description of the embodiment, the gate width direction refers to the direction from the source region to the drain region or from the drain region to the source region (corresponding to the horizontal direction in the figure), that is, the gate width direction is consistent with the channel length direction; the gate width direction is perpendicular to the gate length direction (corresponding to the vertical direction in the figure), unless otherwise specified.
[0061] In a specific implementation process, the DEMOS device of the above embodiment can be obtained according to the following preparation process flow:
[0062] S1, forming a P-well region 4;
[0063] S2, forming an N-drift region 10;
[0064] S3, forming an active region 1;
[0065] S4, forming gate oxide;
[0066] S5, forming polysilicon gate;
[0067] A thin gate oxide layer is formed on the P-well region 4, and a polysilicon layer is formed on the thin gate oxide layer to form a polysilicon gate. The specific forming process can refer to the prior art, and will not be described here.
[0068] S6, NLDD region injection;
[0069] The mask plate of the NLDD region and the N+ source / drain injection region 5 Figure 1 That is, the NLDD region injection in the prior art is different from the general injection in the active region.
[0070] S7, forming a side wall;
[0071] The forming process of the side wall can refer to the prior art, and will not be described here.
[0072] S8, N+ source region 11 and N+ drain region 12 injection, and P-anti-radiation reinforcement buffer region 6 is formed at the same time;
[0073] Because the injection dose of the N+ source region 11 and the N+ drain region 12 is much larger than that of the P-well region 4, in order to prevent the P-well region 4 from being inverted by the general injection in the prior art, the N+ source region 11 and the N+ drain region 12 are injected according to the mask plate of the N+ source / drain injection region 5 which is optimized in the embodiment, and the P-well region 4 between the N+ source region 11 and the isolation region 2 is taken as the P-anti-radiation reinforcement buffer region 6. Figure 4
[0074] S9, metal silicide process;
[0075] S10, contact hole process;
[0076] S11, metal interconnection process.
[0077] The forming processes of S1 to S5, S7, and S9 to S11 can refer to the prior art, and will not be described here.
[0078] The technical scheme of the utility model has been described in combination with the preferred embodiments shown in the drawings, but those skilled in the art can easily understand that the protection scope of the utility model is obviously not limited to these specific embodiments. Without deviating from the principles of the utility model, those skilled in the art can make equivalent changes or replacements to the related technical features, and the technical schemes after the changes or replacements will all fall within the protection scope of the utility model.
Claims
1. A DEMOS device, characterized in that, include: Substrate; A trap region extends from the surface of the substrate into the substrate; The drift region is located on one side of the well region; A gate structure comprising a stacked gate dielectric layer and a gate, wherein the gate structure covers a portion of the well region and a portion of the drift region; The source / drain injection region is located inside the well region. The source / drain injection region includes a source region and a drain region. A channel region is formed between the source region and the drain region. The source region and the drain region are located on opposite sides of the gate structure, and the drain region is located within the drift region. A radiation hardening buffer is located inside the well region and surrounds the source region; wherein the substrate, the well region, and the radiation hardening buffer are of a first doping type, and the doping type of the source / drain injection region and the doping type of the drift region are of a second doping type different from the first doping type; An isolation region is located on the surface of the substrate, and the orthographic projection of the isolation region on the substrate surface surrounds the orthographic projection of the radiation hardening buffer zone on the substrate surface, and surrounds the orthographic projection of the drain region on the substrate surface.
2. The DEMOS device according to claim 1, characterized in that, The doping concentration of the radiation hardening buffer is the same as that of the well region.
3. The DEMOS device according to claim 2, characterized in that, The doping concentration of the radiation hardening buffer zone and the doping concentration of the well region are both light doping concentrations; Both the source region and the drain region have heavy doping concentrations.
4. The DEMOS device according to claim 1, characterized in that, The radiation-hardened buffer zone and the trap area are formed using the same process.
5. The DEMOS device according to claim 1, characterized in that, The width of the radiation-hardened buffer zone is between 0.1µm and 1µm.
6. The DEMOS device according to any one of claims 1 to 5, characterized in that, The source-drain injection region includes a first sub-injection region surrounding the source region and a second sub-injection region surrounding the drain region; wherein the first sub-injection region and the second sub-injection region are connected. The first sub-injection region includes a first side along the gate width direction, a second side along the gate width direction, and a third side along the gate length direction, wherein the orthographic projections of the first side and the second side on the substrate surface extend into the orthographic projection of the gate on the substrate surface.
7. The DEMOS device according to claim 6, characterized in that, The distance d1 by which the orthographic projections of the first side and the second side onto the substrate surface extend into the orthographic projection of the gate onto the substrate surface satisfies the following condition: 10 < d1 < 100 nm.
8. The DEMOS device according to any one of claims 1 to 4, characterized in that, The isolation zone uses media isolation.
9. The DEMOS device according to any one of claims 1 to 4, characterized in that, Also includes: A lightly doped drain region is located between the drain region and the channel region.
10. An integrated circuit, characterized in that, It includes at least one DEMOS device as described in any one of claims 1 to 9.